Ulllted States Patent [19]
`F0ng et al.
`
`US005939831A
`[11] Patent Number:
`[45] Date 0f Patent:
`
`5,939,831
`Aug. 17, 1999
`
`[54] METHODS AND APPARATUS FOR PRE-
`STABILIZED PLASMA GENERATION FOR
`
`5,273,609 12/1993 Moslehi ....................... .. 315/111.21 X
`5,282,899
`2/1994 Balmashnov et al. .
`118/723 R
`
`MICROWAVE CLEAN APPLICATIONS
`
`Inventors: Gary Fong, cupertino; Fong Chang,
`Los Gatos; Long Nguyen, Fremont, all
`of Calif.
`
`[73] Assignee: Applied Materials, Inc., Santa Clara,
`Calif
`
`5,403,434
`
`4/1995 Moslehi . . . . . . . . . . . . . . . . .
`
`. . . . .. 134/12
`
`.438/905 X
`5,468,686 11/1995 Kawamoto ..
`YaChl ................................ ..
`X
`FOREIGN PATENT DOCUMENTS
`
`4-199816
`7/1992 Japan .............................. .. 315/111.21
`Primary Examiner—R0bert Pascal
`Assistant Examiner—Justin P. Bettendorf
`Attorney, Agent, or Firm—ToWnsend & Townsend & CreW
`
`NOV‘ 13’ 1996
`[22] Flled:
`[51] Int. Cl? ...................................................... .. B08B 6/00
`[52] US. Cl. .................... .. 315/11121; 134/11; 438/714;
`438/905
`315/111 21. 438/714
`905:13’4/1 1 12’
`’
`i
`’
`'
`
`iiiiiiiiiiiii
`
`’
`
`[58] Field of Search
`
`The present invention provides systems, methods and appa
`rams for high temperature (at least about 50W800° C-)
`Processing of Semiconductor wafers- The Systems, methods
`and apparatus of the present invention alloW multiple pro
`cess steps to be performed in situ in the same chamber to
`reduce total processing time and to ensure high quality
`processing for high aspect ratio devices. Performing mul
`tiple process steps in the same chamber also increases the
`control of the process parameters and reduces device dam
`age. In particular, the present invention can provide high
`temperature deposition, heating and efficient cleaning for
`forming dielectric ?lms having thickness uniformity, good
`gap ?ll Capability, high density, 10W moisture, and other
`desired characteristics.
`
`20 Claims, 42 Drawing Sheets
`
`[56]
`
`References Cited
`
`U-S- PATENT DOCUMENTS
`204/165
`4 576 692 3/1986 Fukura et al
`iiiiiiiiiiiiii ":"i38/714 X
`475797623
`4/1986 Suzuki et a1:
`156/643
`4,872,947 10/1989 Wang et al.
`118/719
`4,951,601
`8/1990 Maydan e161. ..
`156/345
`5,082,517
`1/1992 Moslehi ......... ..
`5,266,364 11/1993 Tamura et al. ........................ .. 427/571
`
`150
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`U.S. Patent
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`Aug. 17,1999
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`Aug. 17,1999
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`U.S. Patent
`
`Aug. 17, 1999
`
`Sheet 5 0f 42
`
`5,939,831
`
`RECEIVE DESIRED
`TEMPERATURE Tdes
`
`/ I67
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`TEMPERATURE TIk)
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`

`
`U.S. Patent
`
`Aug. 17, 1999
`
`Sheet 6 0f 42
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`5,939,831
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`U.S. Patent
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`Aug. 17,1999
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`Sheet 7 0f 42
`
`5,939,831
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`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 8 of 42
`
`5,939,831
`
`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 9 0f 42
`
`5,939,831
`
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`
`FIG. 5.
`
`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 10 0f 42
`
`5,939,831
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`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 11 0f 42
`
`5,939,831
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`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 12 0f 42
`
`5,939,831
`
`FIG 7B.
`
`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 13 0f 42
`
`5,939,831
`
`FIG‘.
`
`8.
`
`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 14 of 42
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`U.S. Patent
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`Aug. 17,1999
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`Sheet 20 of 42
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`Aug. 17,1999
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`Aug. 17,1999
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`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 24 of 42
`
`5,939,831
`
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`/70.
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`

`
`U.S. Patent
`
`Aug. 17,1999
`
`Sheet 25 of 42
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`U.S. Patent
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`Aug. 17,1999
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`Aug. 17,1999
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`Sheet 27 of 42
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`Aug. 17,1999
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`Aug. 17,1999
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`Aug. 17,1999
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`Aug. 17,1999
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`U.S. Patent
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`Aug. 17,1999
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`
`1
`METHODS AND APPARATUS FOR PRE-
`STABILIZED PLASMA GENERATION FOR
`MICROWAVE CLEAN APPLICATIONS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is related to concurrently filed and com-
`monly assigned patent application Ser. No. 08/749,283 (filed
`Nov. 13, 1996) entitled “HEATER/LIFT ASSEMBLY FOR
`HIGH TEMPERATURE PROCESSING CHAMBER,” hav-
`ing Jonathan Frankel, Hari Ponnekanti, Inna Shmurun, and
`Visweswaren Sivaramakrishnan listed as co-inventors; and
`to concurrently filed and commonly assigned patent appli-
`cation Ser. No. 08/746,748 (filed Nov. 13, 1996) entitled
`“CHAMBER LINER FOR HIGH TEMPERATURE PRO-
`
`CESSING CHAMBER,” having Jonathan Frankel and
`Visweswaren Sivaramakrishnan listed as co-inventors; and
`to concurrently filed and commonly assigned patent appli-
`cation Ser. No. 08/747,830 (filed Nov. 13, 1996) entitled
`“SUBSTRATE PROCESSING APPARATUS WITH
`BOTTOM-MOUNTED REMOTE PLASMA SYSTEM,”
`having Gary Fong and Irwin Silvestre listed as co-inventors;
`and to concurrently filed and commonly assigned patent
`application Ser. No. 08/749,284 (filed Nov. 13, 1996)
`entitled “LIFT ASSEMBLY FOR HIGH TEMPERATURE
`
`PROCESSING CHAMBER,” having Jonathan Frankel
`listed as inventor; and to concurrently filed and commonly
`assigned patent application Ser. No. 08/749,286 (filed Nov.
`13, 1996) entitled “SYSTEMS AND METHODS FOR
`DETECTING END OF CHAMBER CLEAN IN ATHER-
`
`MAL (NONPLASMA) PROCESS,” having Visweswaren
`Sivaramakrishnan and Gary Fong listed as co-inventors; and
`to concurrently filed and commonly assigned patent appli-
`cation Ser. No. 08/749,925 (filed Nov. 13, 1996) entitled
`“LID ASSEMBLY FOR HIGH TEMPERATURE PRO-
`
`CESSING CHAMBER,” having Jonathan Frankel, Inna
`Shmurun, Visweswaren Sivaramakrishnan, and Eugene
`Fukshanski listed as co-inventors; and to concurrently filed
`and commonly assigned patent application Ser. No. 08/748,
`095 (filed Nov. 13, 1996) entitled “METHODS AND APPA-
`RATUS FOR CLEANING SURFACES IN ASUBSTRATE
`
`PROCESSING SYSTEM,” having Gary Fong, Li-Qun Xia,
`Srinivas Nemani, and Ellie Yieh listed as co-inventors; and
`to concurrently filed and commonly assigned patent appli-
`cation Ser. No. 08/747,982 (filed Nov. 13, 1996) entitled
`“METHODS AND APPARATUS FOR GETTERING
`FLUORINE FROM CHAMBER MATERIAL
`
`SURFACES,” having Li-Qun Xia, Visweswaren
`Sivaramakrishnan, Srinivas Nemani, Ellie Yieh, and Gary
`Fong listed as co-inventors; and to concurrently filed and
`commonly assigned patent application Ser. No. 08/748,960
`(filed Nov. 13, 1996) entitled “METHODS AND APPARA-
`TUS FOR DEPOSITING PREMETAL DIELECTRIC
`LAYER AT SUB-ATMOSPHERIC AND HIGH TEM-
`
`PERATURE CONDITIONS,” having Li-Qun Xia, Ellie
`Yieh, and Srinivas Nemani listed as co-inventors; and to
`concurrently filed and commonly assigned patent applica-
`tion Ser. No. 08/746,631 (filed Nov. 13, 1996) entitled
`“METHODS AND APPARATUS FOR SHALLOW
`
`TRENCH ISOLATION,” having Ellie Yieh, Li-Qun Xia,
`and Srinivas Nemani listed as co-inventors; and to concur-
`rently filed and commonly assigned patent application Ser.
`No. 08/746,657 (filed Nov. 13, 1996) entitled “SYSTEMS
`AND METHODS FOR CONTROLLING THE TEMPERA-
`
`TURE OF AVAPOR DEPOSITION APPARATUS,” having
`Jonathan Frankel listed as inventor; and to concurrently filed
`and commonly assigned patent application Ser. No. 08/748,
`
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`883 (filed Nov. 13, 1996) entitled “SYSTEMS AND METH-
`ODS FOR HIGH TEMPERATURE PROCESSING OF
`
`SEMICONDUCTOR WAFERS,” having Visweswaren
`Sivaramakrishnan, Ellie Yieh, Jonathan Frankel, Li-Qun
`Xia, Gary Fong, Srinivas Nemani, Irwin Silvestre, Inna
`Shmurun, and Tim Levine listed as co-inventors; and to
`concurrently filed and commonly assigned patent applica-
`tion Ser. No. 08/748,094 (filed Nov. 13, 1996) entitled
`“METHOD AND APPARATUS FOR FORMING ULTRA-
`SHALLOW DOPED REGIONS USING DOPED SILICON
`
`OXIDE FILMS,” having Ellie Yieh, Li-Qun Xia, Paul Gee,
`and Bang Nguyen listed as co-inventors. Each of the above
`referenced applications are assigned to Applied Materials
`Inc., the assignee of the present invention, and each of the
`above referenced applications are hereby incorporated by
`reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to semiconductor process-
`ing. More specifically, the invention relates to a method and
`apparatus for forming dielectric films over high aspect ratio
`features at temperatures greater than about 500° C., with the
`dielectric films having low moisture content and low shrink-
`age. Embodiments of the present invention are particularly
`useful to deposit doped dielectric films, such as borophos-
`phosilicate glass (BPSG) films, borosilicate glass (BSG)
`films, or phosphosilicate glass (PSG) films, and to form
`ultra-shallow doped regions used, for example, as source/
`drain junctions or as channel stop diffusions in shallow
`trench isolation. In addition, embodiments of the present
`invention may also be used to deposit doped dielectric films
`used as premetal dielectric (PMD) layers, intermetal dielec-
`tric (IMD) layers, or other dielectric layers. Further embodi-
`ments of the present invention may further be used to deposit
`undoped dielectric films, such as undoped silicate glass
`(USG) films used as shallow trench isolation filling oxides,
`insulating layers, capping layers, or other layers.
`One of the primary steps in fabricating modem semicon-
`ductor devices is forming a dielectric layer on a semicon-
`ductor substrate. As is well known, such a dielectric layer
`can be deposited by chemical vapor deposition (CVD). In a
`conventional thermal CVD process, reactive gases are sup-
`plied to the substrate surface where heat-induced chemical
`reactions (homogeneous or heterogeneous) take place to
`produce a desired film. In a conventional plasma process, a
`controlled plasma is formed to decompose and/or energize
`reactive species to produce the desired film. In general,
`reaction rates in thermal and plasma processes may be
`controlled by controlling one or more of the following:
`temperature, pressure, and reactant gas flow rate.
`Semiconductor device geometries have dramatically
`decreased in size since such devices were first introduced
`
`several decades ago. Since then, integrated circuits have
`generally followed the two-year/half-size rule (often called
`“Moore’s Law”) which means that the number of devices
`which will fit on a chip doubles every two years. Today’s
`wafer fabrication plants are routinely producing 0.5 pm and
`even 0.35 pm feature size devices, and tomorrow’s plants
`soon will be producing devices having even smaller feature
`sizes. As device feature sizes become smaller and integration
`density increases, issues not previously considered crucial
`by the industry are becoming of greater concern.
`In
`particular, devices with increasingly high integration density
`have features with high (for example, greater than about 3:1
`or 4:1) aspect ratios. (Aspect ratio is defined as the height-
`to-spacing ratio of two adjacent steps.)
`Increasingly stringent requirements for processes in fab-
`ricating these high integration devices are needed in order to
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`5,939,831
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`3
`produce high quality devices, and conventional substrate
`processing systems are becoming inadequate to meeting
`these requirements. One requirement is that the dielectric
`films formed in the process of fabricating such devices need
`to be uniformly deposited over these high aspect ratio
`features without leaving substantial gaps or voids. Another
`requirement is that these films need to exhibit low shrinkage
`so that subsequent heating and/or wet etching steps do not
`cause voids to open up in the deposited film. However,
`conventional substrate processing systems that
`typically
`deposit dielectric films at temperatures less than about 450°
`C. are unable to produce low moisture films having good
`gap-filling capabilities without opening substantial voids in
`subsequent heating and/or wet etching steps. As is well
`known, these gaps or voids may contribute to device per-
`formance unreliability and other problems. Dielectric films
`used, for example, as PMD or IMD layers in such devices
`need good high aspect ratio gap-fill capability to avoid
`problems caused by these gaps or voids. A further require-
`ment is that metal contamination into the wafer during the
`processing steps be minimized to avoid short circuits and
`other problems in the devices. As is well known, conven-
`tional substrate processing systems using in situ plasma
`during processing experience physical sputtering of ions
`which attack chamber surfaces, such as aluminum walls,
`resulting in metal contamination of the substrate. Use of in
`situ plasma is therefore undesirable. An improved substrate
`processing system, which does not use in situ plasma, is
`needed to provide dielectric films with the desired charac-
`teristics of low moisture, high density, low shrinkage, good
`high aspect ratio gap-filling capability.
`In addition to meeting these stringent requirements, sub-
`strate processing systems must be able to meet the higher
`demands for forming ultra-shallow doped regions, which are
`necessary for high integration devices with shrinking device
`geometries. With the advent of smaller device geometries,
`ultra-shallow doped regions in semiconductors are needed
`for various applications including, for example, source/drain
`junctions, channel stop diffusions for shallow trench
`isolation, etc. For example, MOS devices with channel
`lengths of less than 0.8 gm often require source/drain
`junctions having depths less than about 250 nanometers
`(nm) for adequate device performance. For transistors sepa-
`rated by trench isolation structures of about 0.35 pm depth,
`ultra-shallow channel stop regions having a depth on the
`order of hundreds of nm are usually required. For applica-
`tions requiring ultra-shallow doped regions, it is important
`to provide uniform dopant distribution in the doped regions
`and good control of junction depth.
`Current approaches to forming ultra-shallow doped
`regions, such as ion implantation and gaseous diffusion, are
`inadequate in some applications. With these current
`approaches, the ability to control dopant distribution and
`junction depth is limited, especially as the doped regions
`become shallower. With an approach like ion implantation,
`controlling dopant distribution is made difficult due to the
`built-up concentration of ions at the surface of the semicon-
`ductor material. Also, ion implantation causes damage to the
`semiconductor surface, and methods for repairing this sub-
`strate damage often make it more difficult to control dopant
`distribution and junction depth for ultra-shallow doped
`regions. For example, ions bombarded at relatively high
`energy levels have a tendency to tunnel or channel through
`the semiconductor material and cause damage such as point
`defects. These point defects, which may lead to irregular and
`nonuniform junction depths, may be fixed by annealing the
`implanted semiconductor material at high temperatures
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`(greater than about 900° C.). Annealing the implanted semi-
`conductor material, however, may further increase the junc-
`tion depth beyond that desired. With an approach like
`gaseous diffusion, controlling dopant distribution and junc-
`tion depth is difficult to control in forming ultra-shallow
`doped regions. As technology progresses to even smaller
`geometry devices, an alternative approach that is able to
`control the dopant uniformity and junction depth in ultra-
`shallow doped regions is needed.
`In forming ultra-shallow doped regions, one alternative
`approach to the current approaches of ion implantation and
`gaseous diffusion is the use of a doped dielectric film as a
`dopant diffusion source.
`In this alternative approach, a
`doped dielectric film is deposited onto a substrate and used
`as a source of dopants which are diffused into the substrate
`to form ultra-shallow doped regions. For example, doped
`dielectric films are deposited at temperatures less than 500°
`C.
`in a deposition chamber, and subsequently heated at
`temperatures greater than 500° C. in a different chamber,
`such as an annealing furnace, to perform the dopant diffu-
`sion to form the doped region. Controlling thickness,
`uniformity, and moisture content of the doped dielectric film
`is important in efficiently forming ultra-shallow doped junc-
`tions in the semiconductor material. Specifically, controlling
`the thickness and uniformity of the deposited doped dielec-
`tric film provides some control over the amount of dopants
`available for diffusion. Limiting the thickness of doped
`dielectric films used as diffusion sources also helps to
`increase wafer throughput by saving deposition (and subse-
`quent etching) time. Moreover, a uniformly deposited film
`with even dopant uniformity can provide a more controlled
`diffusion of dopants from the film into the substrate. As is
`well known, moisture in doped dielectric films reacts with
`dopants to bind them in a crystal structure, resulting in fewer
`dopants available for diffusion into the substrate to form
`doped regions. It is desirable to use doped dielectric films
`having a low moisture content, since these films have more
`dopants available for use in the diffusion.
`Several problems are encountered with conventional sub-
`strate processing systems when using a doped dielectric film
`as a dopant diffusion source. One problem is that
`it
`is
`difficult to obtain a high degree of control over film thick-
`ness and uniformity when using conventional systems to
`deposit the doped dielectric film. Another problem is that it
`is often difficult to ensure that adequate amounts of dopants
`in the doped dielectric film are available for diffusion into
`the substrate to form the ultra-shallow doped regions. A
`further problem is the existence of native oxides, which act
`as a barrier layer preventing dopants from diffusing into the
`substrate from the doped dielectric film, on substrate sur-
`faces where the ultra-shallow doped regions are to be
`formed. These problems are discussed in further detail
`below.
`
`Despite the advantages of using doped dielectric films as
`dopant diffusion sources to form ultra-shallow doped
`regions, the problem of being unable to control thickness
`and uniformity of the deposited doped dielectric film when
`using conventional deposition systems is of particular con-
`cern for two primary reasons. First,
`the inability to
`adequately control thickness and uniformity of the deposited
`doped dielectric film using conventional methods and appa-
`ratus undesirably results in a diminished ability to control
`the dopant uniformity and junction depth of the ultra-
`shallow doped region formed. For example, in a conven-
`tional sequential CVD chamber, a substrate rests on a belt
`and travels through various portions of the chamber. In each
`portion of the chamber, a layer having a certain thickness
`
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`5,939,831
`
`5
`may be deposited. Thickness of the deposited film may be
`controlled by changing the belt speed, which provides
`limited control. Further, control over the thickness and
`dopant uniformity of the films deposited on different wafers
`is difficult when attempting to control film thickness and
`dopant concentration using belt speed. That is, the thick-
`nesses of the deposited films on different wafers may vary
`and be unpredictable, leading to wafer-to-wafer unreliabil-
`ity. Second, being able to control
`the thickness of the
`deposited doped dielectric film, even for very thin films, is
`desirable for overall efficiency and increased wafer through-
`put. However, conventional approaches have only been
`capable of forming doped dielectric films with thicknesses
`on the order of thousands of Angstroms
`Also, it may be
`difficult to maintain the thickness of the deposited film as
`thin as possible using systems relying on belt speed to
`control thickness of the deposited film. With thicker films
`deposited conventionally, some dopants may take longer to
`diffuse into the substrate, since they have greater distances
`to travel before reaching the semiconductor material. Also,
`removal of such a thick film used as a dopant diffusion
`source by etching or other technique often increases the total
`time to process the wafer. With growing pressures on
`manufacturers to improve efficiency, it is desirable to form
`the doped dielectric film as thin as possible in order to
`decrease the time needed to deposit and then remove the
`film. It is desirable to have a method and apparatus that can
`easily control the thickness and dopant uniformity of a
`doped dielectric film (less than about 500 A thick at 10.2
`weight percentage dopant variation across the wafer) that is
`used as a dopant diffusion source.
`Another problem with using doped dielectric films as
`dopant diffusion sources for ultra-shallow doped regions is
`that adequate amounts of dopants must be available for
`diffusion into the substrate. Films with high dopant concen-
`tration are often needed to provide adequate amounts of
`dopants for uniform diffusion into the substrate to form
`ultra-shallow junctions. However, moisture absorption and
`outgassing are two problems relating to adequate dopant
`availability. Doped dielectric films, especially those with
`high dopant concentrations, tend to absorb moisture shortly
`after a wafer is exposed to ambient moisture in a clean room
`(e.g. when the wafer is transferred from the deposition
`chamber after deposition of the doped dielectric film to a
`different processing chamber for the next processing step in
`a multiple-step process). The absorbed moisture (H20) then
`reacts with the dopants in the dielectric film, causing the film
`to crystallize. Due to the crystal structure binding the
`dopants within the film, these dopants become unavailable
`for diffusion into the substrate, even after a subsequent
`heating of the wafer by rapid thermal processing or anneal-
`ing in another chamber. Moisture absorption thus reduces
`the amount of dopants for diffusion into the substrate. In
`addition to the moisture absorption problem, outgassing of
`dopants from the doped dielectric film also may occur in
`subsequent heating steps. These dopants diffuse out of the
`film away from the substrate, resulting in fewer dopants
`available to be diffused into the substrate to form ultra-
`
`shallow doped regions.
`Even if adequate dopants are available for diffusion, the
`problem of native oxides remains an important consideration
`when using doped dielectric films as diffusion sources.
`Native oxides existing on the substrate surface where ultra-
`shallow doped regions are to be formed prevent effective and
`uniform dopant diffusion into the silicon. Therefore, native
`oxides, which act as a diffusion barrier layer to the dopants,
`need to be removed. Removing native oxides has been done
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`using conventional techniques such as wet etching using
`liquid etchants, and dry etching using an in situ plasma.
`However, using liquid etchants is often difficult to control
`and may result in overetching the substrate. Substrates that
`have native oxides cleaned by conventional methods such as
`wet etching have shelf lives of less than about one week
`before native oxides begin to form again, making it desirable
`to process the wafers shortly after the native oxides have
`been removed. Using dry etching to remove native oxides
`with an in situ plasma results in plasma damage to the
`surface of the substrate.
`In addition to causing surface
`plasma damage, in situ plasma dry etching may undesirably
`result in more metal contamination, as discussed earlier.
`Accordingly,
`it is important to efficiently remove native
`oxides without damaging the substrate surface so dopants
`may diffuse into the substrate uniformly for ultra-shallow
`doped regions.
`In addition to providing dense, low moisture dielectric
`films having uniform thickness and high aspect ratio gap-
`filling capability with low metal contamination, improved
`quality and overall efficiency in fabricating integrated circuit
`devices is also important. An important way to improve
`quality and overall efficiency in fabricating devices is to
`clean the chamber effectively and economically. With grow-
`ing pressures on manufacturers to improve processing qual-
`ity and overall efficiency, eliminating the total down-time in
`a multiple-step process without compromising the quality of
`the wafers has become increasingly important for saving
`both time and money. During CVD processing, reactive
`gases released inside the processing chamber form layers
`such as silicon oxides or nitrides on the surface of a substrate
`
`being processed. Undesirable oxide deposition occurs else-
`where in the CVD apparatus, such as in the area between the
`gas mixing box and gas distribution manifold. Undesired
`oxide residues also may be deposited in or around the
`exhaust channel and the walls of the processing chamber
`during such CVD processes. Over time, failure to clean the
`residue from the CVD apparatus often results in degraded,
`unreliable processes and defective substrates. Without fre-
`quent cleaning procedures, impurities from the residue built
`up in the CVD apparatus can migrate onto the substrate. The
`problem of impurities causing damage to the devices on the
`substrate is of particular concern with today’s increasingly
`small device dimensions. Thus, CVD system maintenance is
`important for the smooth operation of substrate processing,
`as well as resulting in improved device yield and better
`product performance.
`Frequently, periodic chamber cleanings between process-
`ing of every N wafers is needed to improve CVD system
`performance in producing high quality devices. Providing an
`efficient, non-damaging clean of the chamber and/or sub-
`strate is often able to enhance performance and quality of the
`devices produced. In addition to improving the quality of the
`above-discussed chamber cleanings (which are done without
`breaking the vacuum seal), preventive maintenance chamber
`cleanings (where the vacuum seal is broken by opening the
`chamber lid to physically wipe down the chamber) are
`performed between multiple periodic chamber cleanings.
`Often, performing the necessary preventive maintenance
`chamber cleanings involves opening the chamber lid and
`any other chamber parts that might obstruct the lid, which is
`a time-consuming procedure that
`interferes with normal
`production processing.
`In light of the above, improved methods, systems and
`apparatus are needed for depositing dense, low moisture
`dielectric films with uniform thicknesses and high aspect
`ratio gap-filling capabilities. Optimally,
`these improved
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`5,939,831
`
`7
`methods and apparatus will also provide a chamber clean
`with low metal contamination. Improved methods and appa-
`ratus are also needed for forming doped dielectric films as
`dopant diffusion sources for ultra-shallow junctions. These
`methods and apparatus should be capable of efficiently
`removing native oxides to ensure effective and uniform
`dopant diffusion from the doped dielectric layer without
`causing significant surface damage to the silicon wafer.
`Further, for some applications it
`is desirable to provide
`multiple deposition and cleaning capabilities in a single
`chamber with a simplified design to minimize the time
`consumed for different types of cleanings. What is needed,
`therefore, are systems and methods that are capable of high
`quality, efficient, high temperature deposition and efficient,
`gentle cleaning. In particular, these systems and methods
`should be designed to be compatible with processing
`requirements for forming devices with high aspect ratio
`features, and for forming ultra-shallow doped regions.
`SUMMARY OF THE INVENTION
`
`The present invention provides systems, methods and
`apparatus for high temperature (at least about 500—800° C.)
`processing of semiconductor wafers. Embodiments of the
`present invention in