(19) United States
`(13) Reissued Patent
`Flamm
`
`(54) MULTI-TEMPERATURE PROCESSING
`
`USO0RE40264E
`
`US RE40,264 E
`(10) Patent Number:
`(45) Date of Reissued Patent:
`Apr. 29, 2008
`
`
`
`Green View Dr” Inventor: Daniel IJI Flamm’ Walnut Creek’ CA (Us) 94596
`
`
`
`(21) APP1-NO-110/439J45
`.
`(22) Wed‘
`
`May 14’ 2003
`
`Related U-s- Patent Documents
`
`_
`Relssue Ofr
`(64) Patent No.:
`Issued:
`APPLNQ;
`Filed;
`
`6,231,776
`May 15, 2001
`09/151,163
`sep_ 10, 1998
`
`Us Applications.
`.
`.
`.
`.
`.
`Contlnuatlon-ln- art of a l1cat1on No. 08/567,224, ?led on
`63
`Dec‘ 4, 1995,1101?” abangfned‘
`(
`)
`(60) Provisional application No. 60/058,650, ?led on Sep. 11,
`1997,
`
`(51) Int‘ Cl‘
`H05H 1/00
`H01L 21/302
`
`(2006.01)
`(2006.01)
`
`(52) us. Cl. ........................... .. 216/59; 216/67; 216/68;
`216/74; 438/714; 438/715; 204/192.32;
`156/345.52; 156/345.53
`(58) Field of Classi?cation Search ............... .. 438/715,
`438/719, 721, 725, 737, 738; 216/41, 49,
`2l6/63i67, 75, 79; 156/345.27, 345.52, 345.53
`See application ?le for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`1/1993 Cuomo et al. ....... .. 219/121.43
`5,179,264 A
`3/1994 Carman et a1. ........... .. 219/385
`5,294,778 A
`6/1994 Tsubone et al.
`428/714
`5,320,982 A
`5,556,204 A * 9/1996 Tamura et al. ..
`374/161
`
`5,571,366 A 11/1996 Ishii . . . . . . . . . . . .
`
`. . . .. 156/345
`
`438/715
`5,609,720 A * 3/1997 LenZ et al. ..
`.. 156/643.1
`5,645,683 A
`7/1997 Miyamoto .... ..
`..... .. 216/13
`5,667,631 A
`9/1997 Holland et al. .
`5,695,564 A 12/1997 Imahashi .................. .. 118/719
`
`5,700,734 A 12/1997 Ooishi ...................... .. 438/592
`5,705,433 A * 1/1998 Olson 61 31.
`438/695
`
`
`
`A 5,770,099 A
`
`
`
`IiZuka . . . . . . . . . .. 6/1998 Rice et al. . . . . .
`
`. . . .. 216/68
`
`5,863,376 A
`
`1/1999 Wicker 61 31. .
`
`156/345
`
`5,925,212 A
`
`7/1999 R166 613l. . . . . .
`
`. . . . .. 156/345
`
`.. 315/111.21
`8/1999 Fong 613l.
`5,939,831 A
`9/1999 Grosshart .................. .. 216/67
`5,948,283 A
`5,965,034 A * 10/1999 Vinogradov 613l. ........ .. 216/68
`6,008,139 A 12/1999 P3n 613l. ........... ..
`438/730
`6,033,478 A
`3/2000 Kholodenko .... ..
`118/500
`6,042,901 A
`3/2000 Denison 613l.
`427/579
`6,048,798 A
`4/2000 Gadgil 6131. ............. .. 438/714
`6,068,784 A
`5/2000 Collins 6131. .............. .. 216/68
`6,077,357 A * 6/2000 Rossman 613l. .
`118/728
`6,087,264 A * 7/2000 Shin et al. ...... ..
`438/706
`6,090,303 A
`7/2000 Collins 6131.
`216/68
`6,140,612 A 10/2000 Husain 613l. ............ .. 219/390
`6165 311 A 12/2000 Collins 6131. ............ .. 156/345
`’
`’
`1/2001 Wang 6131. .............. .. 418/723
`6,167,834 B1
`5/2002 Marks et a1‘
`639L148 B2
`11/2002 Marks 6131.
`6,486,069 B1
`6/2001 Marks 6131.
`2001/0003676 A1
`FOREIGN PATENT DOCUMENTS
`
`7/2001
`1236226 A2
`EP
`59076876 A * 5/1984
`JP
`WO-Ol/41189 A2
`W0
`7/2001
`* cited by examiner
`Primary ExamineriAnita Alanko
`(74) Attorney, Agent, or FirmiDaniel L. Flamm
`(57)
`ABSTRACT
`
`The present invention provides a technique, including a
`method and apparatus, for etching a substrate in the manu
`facture of a device. The apparatus includes a chamber and a
`substrate holder disposed in the chamber. The substrate
`holder has a selected thermal mass to facilitate changing the
`temperature of the substrate to be etched during etching
`processes. That is, the selected thermal mass of the substrate
`holder alloWs for a change from a ?rst temperature to a
`second temperature Within a characteristic time period to
`process a ?lm. The present technique can, for example,
`provide different processing temperatures during an etching
`process or the like.
`
`59 Claims, 15 Drawing Sheets
`
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`Apr. 29, 2008
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`Sheet 1 0f 15
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`US RE40,264 E
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`21 23
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`Sheet 2 0f 15
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`US RE40,264 E
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`FIG. 2A
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`Apr. 29, 2008
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`Sheet 3 0f 15
`
`US RE40,264 E
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`Sheet 4 0f 15
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`US RE40,264 E
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`LAM Ex 1018-p. 5
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`Apr. 29, 2008
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`Sheet 5 0f 15
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`US RE40,264 E
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`Apr. 29, 2008
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`Sheet 6 0f 15
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`US RE40,264 E
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`Apr. 29, 2008
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`Sheet 7 0f 15
`
`US RE40,264 E
`
`118
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`
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`
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`Apr. 29, 2008
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`Sheet 8 0f 15
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`US RE40,264 E
`
`FIG. 5A
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`Apr. 29, 2008
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`Sheet 9 0f 15
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`US RE40,264 E
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`Apr. 29, 2008
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`US RE40,264 E
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`Apr. 29,2008
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`Sheet 11 or 15
`
`US RE40,264 E
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`Apr. 29,2008
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`Sheet 12 of 15
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`US RE40,264 E
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`
`Apr. 29, 2008
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`Sheet 13 0f 15
`
`US RE40,264 E
`
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`LAM Ex 1018-p. 14
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`
`Apr. 29,2008
`
`Sheet 14 or 15
`
`US RE40,264 E
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`LAM Ex 1018-p. 15
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`Apr. 29, 2008
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`Sheet 15 0f 15
`
`US RE40,264 E
`
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`D. Polysilicon is exposed
`E. Polysilicon cleared to oxide
`
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`
`Fig. 10
`
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`
`US RE40,264 E
`
`1
`MULTI-TEMPERATURE PROCESSING
`
`Matter enclosed in heavy brackets [ ] appears in the
`original patent but forms no part of this reissue speci?
`cation; matter printed in italics indicates the additions
`made by reissue.
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This present application is a continuation-in-part of US.
`application Ser. No. 60/058,650 ?led Sep. 11, 1997, and a
`continuation-in-part of US. application Ser. No. 08/567,224
`?led Dec. 4, 1995, now abandoned which are hereby incor
`porated by reference for all purposes.
`
`BACKGROUND OF THE INVENTION
`
`This invention relates generally to plasma processing.
`More particularly, one aspect of the invention is for greatly
`improved plasma processing of devices using an in-situ
`temperature application technique. Another aspect of the
`invention is illustrated in an example with regard to plasma
`etching or resist stripping used in the manufacture of semi
`conductor devices. The invention is also of bene?t in plasma
`assisted chemical vapor deposition (CVD) for the manufac
`ture of semiconductor devices. But it will be recognized that
`the invention has a wider range of applicability. Merely by
`way of example, the invention also can be applied in other
`plasma etching applications, and deposition of materials
`such as silicon, silicon dioxide, silicon nitride, polysilicon,
`among others.
`Plasma processing techniques can occur in a variety of
`semiconductor manufacturing processes. Examples of
`plasma processing techniques occur in chemical dry etching
`(CDE), ion-assisted etching (IAE), and plasma enhanced
`chemical vapor deposition (PECVD), including remote
`plasma deposition (RPCVD) and ion-assisted plasma
`enhanced chemical vapor deposition (IAPECVD). These
`plasma processing techniques often rely upon radio fre
`quency power (rf) supplied to an inductive coil for providing
`power to produce with the aid of a plasma.
`Plasmas can be used to form neutral species (i.e.,
`uncharged) for purposes of removing or forming ?lms in the
`manufacture of integrated circuit devices. For instance,
`chemical dry etching is a technique which generally depends
`on gas-surface reactions involving these neutral species
`without substantial ion bombardment.
`In a number of manufacturing processes, ion bombard
`ment to substrate surfaces is often undesirable. This ion
`bombardment, however, is known to have harmful effects on
`properties of material layers in devices and excessive ion
`bombardment ?ux and energy can lead to intermixing of
`materials in adjacent device layers, breaking down oxide
`and “wear out,” injecting of contaminative material formed
`in the processing environment into substrate material layers,
`harmful changes in substrate morphology (e.g.
`amophotization), etc.
`Ion assisted etching processes, however, rely upon ion
`bombardment to the substrate surface in de?ning selected
`?lms. But these ion assisted etching processes commonly
`have a lower selectivity relative to conventional CDE pro
`cesses. Hence, CDE is often chosen when high selectivity is
`desired and ion bombardment to substrates is to be avoided.
`In generally most, if not all, of the above processes
`maintain temperature in a “batch” mode. That is, the tem
`perature of surfaces in a chamber and of the substrate being
`
`20
`
`25
`
`30
`
`35
`
`40
`
`50
`
`55
`
`60
`
`65
`
`2
`processed in such chamber are controlled to be at a sub
`stantially a single value of temperature during processing.
`From the above it is seen that an improved technique,
`including a method and apparatus, for plasma processing is
`often desired.
`
`SUMMARY OF THE INVENTION
`The present invention provides a technique, including a
`method and apparatus, for fabricating a product using a
`plasma discharge. One aspect of the present technique relies
`upon multi-stage etching processes for selectively removing
`a ?lm on a workpiece using diifering temperatures. It
`overcomes serious disadvantages of prior art methods in
`which throughput and etching rate were lowered in order to
`avoid excessive device damage to a workpiece. In particular,
`this technique is extremely bene?cial for removing resist
`masks which have been used to effect selective ion implan
`tation of a substrate in some embodiments. In general,
`implantation of ions into a resist masking surface causes the
`upper surface of said resist to become extremely cross
`linked and contaminated by materials from the ion bom
`bardment. If the cross-linked layer is exposed to excessive
`temperature, it is prone to rupture and forms contaminative
`particulate matter. Hence, the entire resist layer is often
`processed at a low temperature to avoid this particle prob
`lem. Processing at a lower temperature often requires exces
`sive time which lowers throughput. Accordingly, the present
`invention overcomes these disadvantages of conventional
`processes by rapidly removing a majority of resist at a higher
`temperature after an ion implanted layer is removed without
`substantial particle generation at a lower temperature.
`In another aspect, the present invention provides a process
`which utilizes temperature changes to achieve high etch
`rates while simultaneously maintaining high etch selectivity
`between a layer which is being pattered or removed other
`material layers. An embodiment of this process advanta
`geously employs a sequence of temperature changes as an
`unexpected means to avoid various types of processing
`damage to the a device and material layers. A novel inven
`tive means for effecting a suitable controlled change in
`temperature as part of a process involves the use of a
`workpiece support which has low thermal mass in compari
`son to the heat transfer means. In an aspect of this invention,
`a ?uid is utilized to change the temperature of a workpiece.
`In another aspect, the thermal capacity of a circulating ?uid
`is su?iciently greater than the thermal capacity of the
`workpiece support that it permits maintaining the workpiece
`at a substantially uniform temperature.
`Still another aspect of the invention provides an apparatus
`for etching a substrate in the manufacture of a device using
`diiferent temperatures during etching. The apparatus
`includes a chamber and a substrate holder disposed in the
`chamber. The substrate holder has a selected thermal mass to
`facilitate changing the temperature of the substrate to be
`etched. That is, the selected thermal mass of the substrate
`holder allows for a change from a ?rst temperature to a
`second temperature within a characteristic time period to
`process a ?lm. The present apparatus can, for example,
`provide different processing temperatures during an etching
`process or the like.
`The present invention achieves these bene?ts in the
`context of known process technology. However, a further
`understanding of the nature and advantages of the present
`invention may be realized by reference to the latter portions
`of the speci?cation and attached drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a simpli?ed diagram of a plasma etching
`apparatus according to the present invention;
`
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`3
`FIGS. 2Ai2E are simpli?ed con?gurations using Wave
`adjustment circuits according to the present invention;
`FIG. 3 is a simpli?ed diagram of a chemical vapor
`deposition apparatus according to the present invention;
`FIG. 4 is a simpli?ed diagram of a stripper according to
`the present invention;
`FIGS. 5Ai5C are more detailed simpli?ed diagrams of a
`helical resonator according to the present invention;
`FIG. 6 is a simpli?ed block diagram of a substrate holder
`according to the present invention;
`FIG. 7 is a simpli?ed diagram of a temperature control
`system according to an embodiment of the present inven
`tion;
`FIG. 8 is a simpli?ed diagram of a ?uid reservoir system
`according to an embodiment of the present invention;
`FIG. 9 is a [simpli?ed diagram of a] simpli?ed diagram of
`a semiconductor substrate according to an embodiment of
`the present invention; and
`FIG. 10 is a simpli?ed [?oW diagram of a heating] process
`according to the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 is a simpli?ed diagram of a plasma etch apparatus
`10 according to the present invention. This etch apparatus is
`provided With an inductive applicator, e.g., inductive coil.
`This etch apparatus depicted, hoWever, is merely an
`illustration, and should not limit the scope of the claims as
`de?ned herein. One of ordinary skilled in the art may
`implement the present invention With other treatment cham
`bers and the like.
`The etch apparatus includes a chamber 12, a feed source
`14, an exhaust 16, a product support check or pedestal 18,
`an inductive applicator 20, a radio frequency (“rf”) poWer
`source 22 to the inductive applicator 20, Wave adjustment
`circuits 24, 29 (WACs), a radio frequency poWer source 35
`to the pedestal 18, a controller 36, an agile temperature
`control means [19], and other elements. Optionally, the etch
`apparatus includes a gas distributor 17.
`The chamber 12 can be any suitable chamber capable of
`housing a product 28, such as a Wafer to be etched, and for
`providing a plasma discharge therein. The chamber can be a
`domed chamber for providing a uniform plasma distribution
`over the product 28 to be etched, but the chamber also can
`be con?gured in other shapes or geometries, e.g., ?at ceiling,
`truncated pyramid, cylindrical, rectangular, etc. Depending
`upon the application, the chamber is selected to produce a
`uniform entity density over the pedestal 18, providing a high
`density of entities (i.e., etchant species) for etching unifor
`mity.
`The product support chuck can rapidly change its tem
`perature in Ways de?ned herein as Well as others. The Wafer
`is often thermally coupled to the support check Which
`permits maintaining the Wafer temperature in a knoWn
`relationship With respect to the chuck. Coupling Will often
`comprise an electrostatic chuck or mechanical clamps,
`Which apply a pressure to bring the product into close
`proximity With the support check, Which enables a relatively
`good thermal contact betWeen the Wafer and support chuck.
`The support chuck and Wafer are often maintained at a
`substantially equal temperature. A pressure of gas is often
`applied through small openings in the support chuck behind
`the Wafer in order to improve thermal contact and heat
`transfer betWeen the Wafer and support chuck.
`The present chamber includes a dome 25 having an
`interior surface 26 made of quartz or other suitable materi
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`als. The exterior surface of the chamber is typically a
`dielectric material such as a ceramic or the like. Chamber 12
`also includes a process kit With a focus ring 32, a cover (not
`shoWn), and other elements. Preferably, the plasma dis
`charge is derived from the inductively coupled plasma
`source that is a de-coupled plasma source (“DPS”) or a
`helical resonator, although other sources can be employed.
`The de-coupled source originates from rf poWer derived
`from the inductive applicator 20. Inductively coupled poWer
`is derived from the poWer source 22. The rf signal frequen
`cies ranging from 800 kHZ to 80 MHZ can be provided to the
`inductive applicator 20. Preferably, the rf signal frequencies
`range from 5 MHZ to 60 MHZ. The inductive applicator
`(e.g., coil, antenna, transmission line, etc.) overlying the
`chamber ceiling can be made using a variety of shapes and
`ranges of shapes. For example, the inductive applicator can
`be a single integral conductive ?lm, a transmission line, or
`multiple coil Windings. The shape of the inductive applicator
`and its location relative to the chamber are selected to
`provide a plasma overlying the pedestal to improve etch
`uniformity.
`The plasma discharge (or plasma source) is derived from
`the inductive applicator 20 operating With selected phase 23
`and anti-phase 27 potentials (i.e., voltages) that substantially
`cancel each other. The controller 36 is operably coupled to
`the Wave adjustment circuits 24, 29. In one embodiment,
`Wave adjustment circuits 24, 29 provide an inductive appli
`cator operating at full-Wave multiples 21. This embodiment
`of full-Wave multiple operation provides for balanced
`capacitance of phase 23 and anti-phase voltages 27 along the
`inductive applicator (or coil adjacent to the plasma). This
`full-Wave multiple operation reduces or substantially elimi
`nates the amount of capacitively coupled poWer from the
`plasma source to chamber bodies (e.g., pedestal, Walls,
`Wafer, etc.) at or close to ground potential. Alternatively, the
`Wave adjustment circuits 24, 29 provide an inductive appli
`cator that is effectively made shorter or longer than a
`full-Wave length multiple by a selected amount, thereby
`operating at selected phase and anti-phase voltages that are
`not full-Wave multiples. Alternatively, more than tWo, one or
`even no Wave adjustment circuits can be provided in other
`embodiments. But in all of these above embodiments, the
`phase and anti-phase potentials substantially cancel each
`other, thereby providing substantially no capacitively
`coupled poWer from the plasma source to the chamber
`bodies.
`In alternative embodiments, the Wave adjustment circuit
`can be con?gured to provide selected phase and anti-phase
`coupled voltages coupled from the inductive applicator to
`the plasma that do not cancel. This provides a controlled
`potential betWeen the plasma and the chamber bodies, e.g.,
`the substrate, grounded surfaces, Walls, etc. In one
`embodiment, the Wave adjustment circuits can be used to
`selectively reduce current (i.e., capacitively coupled current)
`to the plasma. This can occur When certain high potential
`difference regions of the inductive applicator to the plasma
`are positioned (or kept) aWay from the plasma region (or
`inductor-containing-the-plasma region) by making them go
`into the Wafer adjustment circuit assemblies, Which are
`typically con?gured outside of the plasma region. In this
`embodiment, capacitive current is reduced and a selected
`degree of symmetry betWeen the phase and anti-phase of the
`coupled voltages is maintained, thereby provided a selected
`potential or even substantially ground potential. In other
`embodiments, the Wave adjustment circuits can be used to
`selectively increase current (i.e., capacitively coupled
`current) to the plasma.
`
`LAM Ex 1018-p. 18
`LAM v FLAMM
`IPR2015-01767
`
`

`
`US RE40,264 E
`
`5
`As shown, the Wave adjustment circuits are attached (e.g.,
`connected, coupled, etc.) to ends of the inductive applicator.
`Alternatively, each of these Wave adjustment circuits can be
`attached at an intermediate position aWay from the inductive
`application ends. Accordingly, upper and loWer tap positions
`for respective Wave adjustment circuits can be adjustable.
`But both the inductive applicator portions beloW and above
`each tap position are active. That is, they both can interact
`With the plasma discharge.
`A sensing apparatus can be used to sense plasma voltage
`Which is used to provide automatic turning of the Wave
`adjustment circuits and any rf matching circuit betWeen the
`rf generator and the plasma treatment chamber. This sensing
`apparatus can maintain the average AC potential at Zero or
`a selected value relative to ground or any other reference
`value. This Wave adjustment circuit provides for a selected
`potential difference betWeen the plasma source and chamber
`bodies. These chamber bodies may be at a ground potential
`or a potential supplied by another bias supply, e.g., See FIG.
`1 reference numeral 35. Examples of Wave adjustment
`circuits are described by Way of the FIGS. beloW.
`For instance, FIGS. 2A to 2E are simpli?ed con?gurations
`using the Wave adjustment circuits according to the present
`invention. These simpli?ed con?gurations should not limit
`the scope of the claims herein. In an embodiment, these
`Wave adjustment circuits employ substantially equal circuit
`elements (e.g., inductors, capacitors, transmission line
`sections, and others) such that the electrical length of the
`Wave adjustment circuits in series With the inductive appli
`cator coupling poWer to the plasma is substantially an
`integral multiple of one Wavelength. In other embodiments,
`the circuit elements provide for inductive applicators at
`other Wavelength multiples, e.g., one-sixteenth-Wave, one
`eighth-Wave, quarter-Wave, half-Wave, three-quarter Wave,
`etc. In these embodiments (e.g., full-Wave multiple, half
`Wave, quarter-Wave, etc.), the phase and anti-phase relation
`ship betWeen the plasma potentials substantially cancel each
`other. In further embodiments, the Wave adjustment circuits
`employ circuit elements that provide plasma applicators
`With phase and anti-phase potential relationships that do not
`cancel each other out using a variety of Wave length por
`tions.
`FIG. 2A is a simpli?ed illustration of a plasma source 50
`using Wave adjustment circuits and an agile temperature
`chuck 75 according to an embodiment of the present inven
`tion. This plasma source 50 includes a discharge tube 52, an
`inductive applicator 55, an exterior shield 54, an upper Wave
`adjustment circuit 57, a loWer Wave adjustment circuit 59, an
`rf poWer supply 61, and other elements. The upper Wave
`adjustment circuit 57 is a helical coil transmission line
`portion 69, outside of the plasma source region 60. LoWer
`Wave adjustment circuit 59 also is a helical coil transmission
`line portion 67 outside of the plasma source region 60. The
`poWer supply 61 is attached 65 to this loWer helical coil
`portion 67, and is grounded 63. Each of the Wave adjustment
`circuits also are shielded 66, 68.
`In this embodiment, the Wave adjustment circuits are
`adjusted to provide substantially Zero AC voltage at one
`point on the inductive coil (refer to point 00 in FIG. 2A).
`This embodiment also provides substantially equal phase 70
`and anti-phase 71 voltage distributions in directions about
`this point (refer to OO-A and OO-C in FIG. 2A) and provides
`substantially equal capacitance coupling to the plasma from
`physical inductor elements (OO-C) and (OO-A), carrying the
`phase and anti-phase potentials. Voltage distributions OO-A
`and OO-C are combined With C-D and A-B (shoWn by the
`phantom lines) to substantially comprise a full-Wave voltage
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`distribution in this embodiment Where the desired con?gu
`ration is a selected phase/anti-phase portion of a full-Wave
`inductor (or helical resonator) surrounding the plasma
`source discharge tube.
`In this embodiment, it is desirable to reduce or minimiZe
`capacitive coupling current from the inductive element to
`the plasma discharge in the plasma source. Since the capaci
`tive current increases monotonically With the magnitude of
`the difference of peak phase and anti-phase voltages, Which
`occur at points A and C in FIG. 2A, this coupling can be
`lessened by reducing this voltage difference. In FIG. 2A, for
`example, it is achieved by Way of tWo Wave adjustment
`circuits 57, 59. Coil 55 (or discharge source) is a helical
`resonator and the Wave adjustment circuits 57, 59 are helical
`resonators.
`The discharge source helical resonator 53 can be con
`structed using conventional design formulae. Generally, this
`helical resonator includes an electrical length Which is a
`selected phase portion “x” (A to 00 to C) of a full-Wave
`helical resonator. The helical resonator Wave adjustment
`circuits are each selected to jointly comprise a portion (Zn-x)
`of full-Wave helical resonators. Physical parameters for the
`Wave adjustment helical resonators can be selected to realiZe
`practical physical dimensions and appropriate Q, Z0, etc
`values. In particular, some or even all of the transmission
`line parameters (Q, Z0, etc.) of the Wave adjustment circuit
`sections may be selected to be substantially the same as the
`transmission line parameters of the inductive applicator. The
`portion of the inductive plasma applicator helical resonator,
`on the other hand, is designed and siZed to provide selected
`uniformity values over substrate dimensions Within an eco
`nomical equipment siZe and reduced Q.
`The Wave adjustment circuit provides for external rf
`poWer coupling, Which can be used to control and match
`poWer to the plasma source, as compared to conventional
`techniques used in helical resonators and the like. In
`particular, conventional techniques often match to, couple
`poWer to, or match to the impedance of the poWer supply to
`the helical resonator by varying a tap position along the coil
`above the grounded position, or selecting a ?xed tap position
`relative to a grounded coil end and matching to the imped
`ance at this position using a conventional matching netWork,
`e.g., LC network, at netWork, etc. Varying this tap position
`along the coil Within a plasma source is often cumbersome
`and generally imposes dif?cult mechanical design problems.
`Using the ?xed tap and external matching netWork also is
`cumbersome and can cause unanticipated changes in the
`discharge Q, and therefore in?uences its operating mode and
`stability. In the present embodiments, the Wave adjustment
`circuits can be positioned outside of the plasma source (or
`constrained in space containing the inductive coil, e.g., See
`FIG. 2A. Accordingly, the mechanical design (e.g., means
`for varying tap position, change in the effective rf poWer
`coupling point by electrical means, etc.) of the tap position
`are simpli?ed relative to those conventional techniques.
`In the present embodiment, rf poWer is fed into the loWer
`Wave adjustment circuit 59. Alternatively, rf poWer can be
`fed into the upper Wave adjustment circuit (not shoWn). The
`rf poWer also can be coupled directly into the inductive
`plasma coupling applicator (e.g., coil, etc.) in the Wave
`adjustment circuit design, as illustrated by FIG. 2B.
`Alternatively, other applications Will use a single Wave
`adjustment circuit, as illustrated by FIG. 2C. PoWer can be
`coupled into this Wave adjustment circuit or by conventional
`techniques such as a tap in the coil phase. In some
`embodiments, this tap in the coil phase is positioned above
`the grounded end. An external impedance matching netWork
`
`LAM Ex 1018-p. 19
`LAM v FLAMM
`IPR2015-01767
`
`

`
`US RE40,264 E
`
`7
`may then be operably coupled to the power for satisfactory
`power transfer ef?ciency from, for example, a conventional
`coaxial cable to impedances (current to voltage rations)
`existing betWeen the Wave adjustment circuit terminated end
`of the applicator and the grounded end.
`A further embodiment using multiple inductive plasma
`applicators also is provided, as shoWn in FIG. 2D. This
`embodiment includes multiple plasma applicators (PA 1,
`PA2. .
`. PAn). These plasma applicators respectively provide
`selected combinations of inductively coupled poWer and
`capacitively coupled poWer from respective voltage poten
`tials (V1, V2. .
`. Vn). Each of these plasma applicators
`derives poWer from its poWer source (PS1, PS2. .
`. PSn)
`either directly through an appropriate matching or coupling
`netWork or by coupling to a Wave adjustment circuit as
`described. Alternatively, a single poWer supply using poWer
`splitters and impedance matching netWorks can be coupled
`to each (or more than tWo) of the plasma applicators.
`Alternatively, more than one poWer supply can be used
`Where at least one poWer supply is shared among more than
`one plasma applicator. Each poWer source is coupled to its
`respective Wave adjustment circuits (WACl, WAC2. .
`.
`WACn).
`Generally, each plasma applicator has an upper Wave
`adjustment circuit (e.g., WACla, WAC2a. .
`. WACna) and a
`loWer Wave adjustment circuit (e.g., WAClb, WAC2b. .
`.
`WACnb). The combination of upper and loWer Wave adjust
`ment circuits are used to adjust the plasma source potential
`for each plasma source Zone. Alternatively, a single Wave
`adjustment circuit can be used for each plasma applicator.
`Each Wave adjustment circuit can provide substantially the
`same impedance characteristics, or substantially distinct
`impedance characteristics. Of course, the particular con?gu
`ration used Will depend upon the application.
`For instance, multiple plasma applicators can be used to
`employ distinct excitation frequencies for selected Zones in
`a variety of applications. These applications include ?lm
`deposition using plasma enhanced chemical deposition,
`etching by Way of ion enhanced etching or chemical dry
`etching and others. Plasma cleaning also can be performed
`by Way of the multiple plasma applicators. Speci?cally, at
`least one of the plasma applicators Will de?ne a cleaning
`plasma used for cleaning purposes. In one embodiment, this
`cleaning plasma can have an oxygen containing species.
`This cleaning plasma is de?ned by using an oxygen
`discharge, Which is sustained by microWave poWer to a
`cavity or resonant microWave chamber abutting or surround
`ing a conventional dielectric vessel. Of course, a variety of
`other processes also can be performed by Way of this
`multiple plasma applicator embodiment.
`This present application