United States Patent [19]
`Nakamura et a1.
`
`IllllllllllllllllllllllllllI!!!lllllllllllllllllllllllllllllllllllllllllll
`
`005316616A
`5,316,616
`[11] Patent Number:
`[45} Date of Patent: May 31, 1994
`
`[54] DRY ETCHING WITH HYDROGEN
`BROMIDE OR BRQMINE
`[75] Inventors: Moritaka Nakamura, Yokohama;
`Takashi Kurimoto, Hashima;
`Katsuhiko lizuka, Kawasaki, all of
`Japan
`[73] Assignee: Fujitsu Limited, Kawasaki, Japan
`[21] Appl. No.: 68,615
`[22] Filed;
`May 27’ 1993
`
`.
`
`.
`
`.
`
`-
`
`apan .
`
`56-93319 7/1981 Japan .
`57-7936 l/ 1982 Japan .
`57'59331 4/1982 Japan ‘
`japan '
`58_6O567 4/1983 Japan _
`59-103338 6/1984 Japan .
`60-158627 8/1985 Japan ................................. .. 156/643
`61-61424 3/1986 Japan.
`62-30330 2/1987 Japan .
`62-32618 2/1987 Japan .
`62411432 5/ 1937 Japan -
`62 145933 6/1987 Japan .
`OTHER PUBLICATIONS
`.
`.
`.
`Chen et al., “Ta ered Via Hole”, IBM Technical D1s
`closure Bulletimpvol. 26, No. 12, May 1984, p. 6282.
`Keaton ct a1., Temperature and Flow Effects in Alumi
`num Etching Using Bromine-Containing Plasmas, J.
`V81;- Sci Tef>h1101- B6(1)Ja11-/F¢b- 1988 PP- 72-76
`$1111°h1dT1L9h1°1 111-, ggw-femgerzwe lyffllf'w 1011518111
`mg an
`lcrowave asma tc mg a
`neon, pp y.
`81.88- 88.11 81 <81 888- 111 1888 pp- 818-818.
`H1_rofum1 Uchida, Submieron Trench Etching Under
`H1gh_Pressure, 1046B Extended Abstracts/Electro
`chemical Soc1ety 87-2 (1987) Princeton, N.J., pp.
`1038-1039‘
`Ahmed M. El-Masry et al., Magnetically Enhanced
`Reactive Ion Etching of Silicon in Bromine Plasmas, J. of
`Vac. Sci. Technol B6 (1988) Jan-Feb. No. 1, Wood
`bury’ NY" USA’ pp‘ 257461
`H. Okano et al. Down-Flow Process in VLSIManufactur
`ing, Extended Abstracts of the 20th (1988 International)
`Conference on Solid State Devices and Materials, To
`g1?’ 198%)?‘ 3149-535 G J
`5
`("m '"‘_e’— ' My °n°
`Ass's'ant Ex“m'”e’*T°dd J- Burns
`Attorney/488111, 0rF1'rm—ArmStr011g, Westerman,
`Ha?0ri,McLe1and & Naughton
`[57]
`ABSTRACT
`Plasma etching with hydrogen bromide or bromine as
`an etching gas allows a precise control of attaining
`vertical etching or taper etching with a desired taper
`angle by controlling a temperature of a mass to be
`etched, which mass is a phosphorus-doped n-type poly
`crystalline silicon, phosphorus-doped single crystalline
`or phosphorus-doped silicides semiconductor wafer.
`6 Claims, 7 Drawing Sheets
`
`[63]
`
`Related US. Application Data
`Continuation of Ser. No. 670,516, Mar. 18, 1991, aban-
`doned, which is a continuation of Ser. No. 307,710,
`Feb. 8 1989 abandoned.
`’
`,
`’
`_
`,
`,
`_
`“mg” Apl’hc‘m“ Pmmy m“
`[301
`Feb. 9, 1988 [JP]
`Japan .............................. .. 63-026654
`Ju],19,1988 [JP]
`Japan _ _ _ _ _ _ ,
`_ _ , _ __ 63.173244
`Sep. 28, 1988 [JP]
`Japan .......................... .. 63-240940
`Nov. 15, 1988 [JP]
`Japan .............................. .. 63-286880
`5
`1251 138%. 3.11111‘:$3.‘::JJJJJJJJJJJJ..........J‘i;a/8%?i52658‘?
`156/659.1’_l56/662’
`[58] Field of Swch
`156/643 6:26 6581
`204/19’2 32’192
`References ,Cited
`‘
`,
`‘
`
`[56]
`
`US. PATENT DOCUMENTS
`
`3,994,793 11/1976 Harvilchuek et al. ....... .. 204/192.22
`i’iég’ggé
`lljlcvmstem """""""""
`156/65'9 1
`4305915 3/1985 can?‘ "" "
`156/643
`"" "
`4’720’322 V1988 gm; 6
`'
`4,744,861 5/1988 Matsunaga et a1. ........ .. 156/6591
`4,798,650 l/l989 Nakamura et al. .
`156/643
`4,799,991 1/1989 Dockrey ................ .. 156/643
`4,842,683 6/1989 Cheng et a1.
`156/643
`4,943,344 7/1990 Taehi et al. . . . . .
`. . . .. 156/662
`4,986,877 1/1991 Tachietal.
`156/646
`5,007,982 4/1991 T5011 .................................. .. 156/646
`FOREIGN PATENT DOCUMENTS
`
`0250092 5/ 1937 Eufopcan Pat- Off- -
`0272143 12/1937 European Pat- Off- -
`0289131 3/1983 European Pat- 0“ -
`5:22: '
`56-90525 7/ 1981 Japan .
`
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`LAM Exh 1006-pg 1
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`US. Patent
`
`May 31, 1994
`
`Sheet 1 of 7
`
`5,316,616
`
`PRIOR ART
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`US. Patent
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`May 31, 1994
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`Sheet 2 of 7
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`PRIOR ART
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`U.S. Patent
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`May 31, 1994
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`Sheet 3 of 7
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`5,316,616
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`U.S. Patent
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`May 31, 1994
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`Sheet 4 of 7
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`5,316,616
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`

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`US. Patent
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`May 31, 1994
`
`Sheet 5 of 7
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`5,316,616
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`LAM Exh 1006-pg 6
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`US. Patent
`
`May 31, 1994
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`5,316,616
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`US. Patent
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`May 31, 1994
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`Sheet 7 of 7
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`

`
`1
`
`DRY ET CHING WITH HYDROGEN BROMIDE OR
`BROMINE
`
`This application is a continuation of application Ser.
`No. 07/670,516, ?led Mar. 18, 1991 now abandoned
`which application was a continuation of Ser. No.
`07/307,710, ?led Feb. 8, 1989 now abandoned.
`
`15
`
`5,316,616
`2
`(1) Phosphorus is diffused and phosphorus ions are
`then implanted to a ?rst polycrystalline silicon layer, to
`make the ion implanted surface portion of the layer
`more receptive to etching. Then isotropic etching is
`carried out on the polycrystalline silicon layer, and thus
`the polycrystalline silicon layer is taper etched. [Japa- \
`nese Unexamined Patent Publication Nos. 58-4932 and
`53-73086 and Japanese Examined Patent Publication
`No. 60-782]. Nevertheless, this process is complicated,
`since a diffusion of phosphorus and ion implantation is
`necessary before the etching. Also, it is dif?cult to con
`trol a width of a pattern during isotropic etching.
`(2) Etching with an etching gas to which a depositing
`gas such as C2H6, C2114, is added to provide a simulta
`neous etching and deposition to form a tapered pattern.
`(Japanese Unexamined Patent Publication Nos.
`59-103338, 62-30330 and 62-32618]. This method allows
`a deposition on a wall of an etching chamber, which
`results in contamination by particles and reduces the
`product yield.
`(3) A resist mask is tapered and etching is effected
`with a low etching selectivity between polycrystalline
`silicon and the resist. [Japanese Unexamined Patent
`Publication (Kokai) No. 61-61424]. In this method,
`since the thickness of the resist is varied, it is dif?cult to
`control the width of a pattern.
`(4) Alternate etching and ashing of a resist mask.
`[Japanese Unexamined Patent Publication (Kokai) No.
`56-93319 and 57-59331]. This process is complicated
`and control of the width of a pattern is difficult, since
`the thickness of the resist mask is reduced.
`(5) Isotropic etching followed by anisotropic etching.
`The isotropic etching is stopped when only an upper
`part of a polycrystalline silicon layer is etched, and then
`the anisotropic etching is carried out. [Japanese Unex
`amined Patent Publication No. 57-7936 and 56-90525].
`This process also is complicated, and the control of the
`width of a pattern is difficult.
`(6) A mask having an overhanging portion having a
`lower surface facing upward is used, so that the flow of
`ions is disturbed and thus a tapered pattern is formed.
`[Japanese Examined Patent Publication No. 57-42154].
`It is not easy, however, to form a resist mask having an
`overhanging portion as above, and it is difficult to con
`trol the width of an etched pattern.
`Therefore, the main object of the present invention is
`to provide a process for anisotropically etching a mate
`rial such as polycrystalline silicon and silicides, which
`process is simple and easily controlled. Another object
`of the present invention is to provide a process for taper
`etching such a material, which process is simple and
`able to control the taper angle of an etched pattern. A
`further object of the present invention is to provide a
`process for vertically etching such a material with a
`high etching selectivity, without side-etching.
`SUMMARY OF THE INVENTION
`The above and other objects, features and advantages
`are attained by a process for selectively etching a mass
`such as silicon or silicon-bearing material, comprising:
`providing an etching mask over the masilo expose an
`area of the mass to be etched; and providing a plasma of
`an etching gas in contact with the mass, the etching gas
`containing hydrogen bromide, bromine or a combina
`tion thereof as a main reactive component that reacts
`with the mass, whereby the exposed area of the mass is
`selectively etched to form a mass having an etched
`portion and a side wall along a periphery of the etching
`
`40
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to dry etching a mate
`rial such as polycrystalline silicon and silicides with
`hydrogen bromide or bromine.
`2. Description of the Related Art
`As a result of the increased degree of integration and
`switching speed of integrated circuits IC’s, an insulating
`?lm such as a gate insulating ?lm must be made thinner,
`for example, 30 nm to 50 nm, and further, a multilayer
`technology for electrical conductive materials such as
`polycrystalline silicon must be utilized. This processing
`of such a polycrystalline silicon determines rate length,
`which in?uences the characteristics of an ?eld effect
`transistor PET, and thus during etching of the polycrys
`talline silicon, the width of a pattern must be strictly
`controlled and a high etching selectivity of the poly
`crystalline silicon obtained in relation to an‘ underlying
`gate insulating layer. To accomplish the above, vertical
`etching methods, such as reactive ion etching, can be
`used, but if a lower layer, for example, a ?rst polycrys
`talline silicon layer, is vertically etched, the thickness of
`an upper layer, for example, a second polycrystalline
`silicon layer, becomes thicker at a portion of a step of
`the vertically etched ?rst polycrystalline silicon layer
`than at the other flat portion. This thicker portion of the
`second polycrystalline silicon layer remains after the
`second polycrystalline silicon layer is etched, and leads
`to a short circuiting of adjacent patterns of the second
`polycrystalline silicon layer through the remaining por
`tion. If the second polycrystalline silicon layer is over
`etched for an extended time, to completely remove the
`polycrystalline silicon at the step portion, the width of a
`pattern is narrowed and the underlying insulating layer
`is excessively etched.
`One solution to the above problems is the use of a
`vertical etching process having a high selectivity, so
`that an underlying layer is not excessively etched. To
`obtain this high selectivity, a chlorine-bearing or ?uo
`rine-bearing etching gas is widely used, but etching
`with a chlorine or ?uorine-bearing gas tends to cause
`side-etching, due to the isotropic nature thereof, and it
`becomes difficult to control the width of a pattern. To
`protect the side wall of a pattern from such an etching
`gas, a carbon-bearing gas may be used, but use of a
`carbon-bearing gas increases the etching rate of an insu
`lating layer, whereby the selectivity of etching of a
`polycrystalline silicon, etc. in relation to an insulating
`layer is reduced. Further, a polymer containing carbor
`is deposited onto a wall of an etching chamber, which
`causes contamination and a reduction of the product
`yield.
`Another solution is to form a pattern of a ?rst poly
`crystalline silicon layer having a tapered shape, i.e., a
`declined, not vertical, side wall, on which a second
`polycrystalline silicon layer is deposited and then
`etched.
`The known methods of taper etching are as follows:
`
`35
`
`45
`
`60
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`LAM Exh 1006-pg 9
`
`

`
`5,316,616
`3
`mask; wherein an angle of inclination of the side wall is
`controlled by selecting a temperature of the mass during
`the etching.
`Japanese Examined Patent Publication No. 58-14507,
`corresponding to US. Pat. anplication Ser. No. 594,418,
`?led on Jul. 9, l975.now abandoned, suggests that a
`bromine or a bromine compound may be used for a
`vertical etching of silicon, but in this publication, only
`carbon tetrachloride is actually used in experiments,
`and bromine or a bromine compound is mentioned
`merely as a possible alternative. Furthermore, this pub
`lication states that a target electrode must be heated,
`since the boiling point of SiBr, at which it is thought to
`be vaporized, is 153° C. The present inventors have,
`however, surprisingly found that a vertical etching of
`silicon, etc., can be carried out at a temperature lower
`than 150' C., and further, that a taper etching can be
`obtained at a temperature of —40° C. to 50° C., in which
`process the taper angle of the etching is precisely con
`trolled in accordance with the temperature.
`US. Pat. No. 4,490,209 issued on Dec. 25, 1984 to
`Hartman discloses a plasma etching which allows an
`anisotropic etching of silicon, in which a gaseous mix
`ture of a chlorine-bearing species and hydrogen bro
`mide is used. In this patent, however, a chlorine-bearing
`species must be used as a main reactive component and
`hydrogen bromide added in a small amount of about 1
`to about 10%, to allow a near perfect anisotropic etch
`ing. This process is different from the process of the
`present invention, in which hydrogen bromide or bro
`mine is used as a main etching or reactive component
`and not only a vertical etching but also a taper etching
`can be carried out, and the taper angle controlled as
`desired.
`,
`Therefore, in accordance with the present invention,
`a taper etching having an inclination angle of the side
`wall of an etched mass of less than 90“ is obtained at a
`temperature of the mass etched of —40° C. to +50° C.,
`and a substantially vertical etching is carried out at a
`temperature of the etched mass of 50° C. to 150° C. The
`relationship between the angle of inclination of the side
`wall of the mass etched and the temperature of the mass
`etched is expressed as follows:
`
`25
`
`30
`
`35
`
`15
`
`20
`
`4
`not include a carbon-bearing material which can come
`into contact with a plasma of an etching gas. Such a
`carbon-bearing material disadvantageously reduces the
`etching selectivity of a material to be etched. And the
`content of carbon in the etching gas is preferably less
`than 120 ppm, more ‘preferably less than 40 ppm, based
`on the total weight of the etching gas.
`In accordance with the present invention, there is
`also provided a process for selectively etching a mass,
`comprising: providing an etching mask of an organic
`material over the mass to expose an area of the mass to
`be etched; providing a plasma of an etching gas in
`contact with the mass, the etching gas containing hy
`drogen bromide as a main reactive component that
`reacts with the mass, whereby the exposed area of the
`mass is selectively etched; and providing, around the
`mass having the etching mask of the organic material
`thereover, an atmosphere containing excited oxygen
`atoms separated from a plasma thereof.
`When plasma etching is carried out using hydrogen
`bromide as an etching gas and an organic resist as a
`mask, followed by ashing the organic resist mask, a thin
`?lm remains in the form of a fence along the periphery
`of an original pattern of the organic resist mask. This
`thin ?lm may result in contamination by particles and
`reduce the product yield. This thin ?lm in the form of a
`fence can be removed by cleaning with a dilute fluoric
`acid, but this may damage an underlying layer, for ex
`ample, a gate oxide ?lm, and thus cannot be used in the
`fabrication of semiconductor devices. Silicon oxide and
`nitride layers may be used as a mask, without raising the
`above problem, instead of an organic mask, but the use
`of these layers complicates the process.
`As a result of attempts to solve this problem, the
`inventors found that the thin ?lm in the form of a fence
`is formed from carbon, bromine, oxygen, hydrogen and,
`if present, silicon, etc., during plasma etching with hy
`drogen bromide, and that this thin ?lm cannot be re
`moved by oxygen plasma ashing but can be removed by
`treatment with an excited oxygen-atom-containing at
`mosphere separated from a generated plasma. Here, an
`excited oxygen-atom-containing atmosphere is formed
`by transportation of excited oxygen atoms, mainly in
`the state of neutral atoms, from a plasma, mainly in the
`state of ions, generated by an electrical discharge or
`microwave irradiation, the transportation of excited
`oxygen atoms being caused by a pressure difference.
`Therefore, an excited oxygen-atom-containing atmo
`sphere can be formed downstream of an oxygen plasma.
`The organic resist used for plasma etching with hy
`drogen bromide can be removed by oxygen plasma
`ashing, except for a portion of 'the fence-like thin ?lm.
`Therefore, treatment of the organic mask in an excited
`oxygen-atom-containing atmosphere can be combined
`1 with a normal oxygen plasma ashing before or after the
`former treatment.
`The excited oxygen atom-containing atmosphere
`may be formed from mainly oxygen gas (02 to which a
`halogen-bearing gas such as CF4, nitrogen or water may
`be added to increase the generation of oxygen atom.
`The general conditions for ashing with an excited
`oxygen-atom-containing atmosphere are shown as fol
`lows:
`
`where 6 stands for the inclination angle of the side wall
`of the etched mass and t stands for the temperature of
`the mass during etching, the inclination angle 6 having
`a dispersion of :5". Note, the temperature mentioned
`above is that of the mass to be etched, not that of an
`atmosphere surrounding the mass to be etched. Further
`more, for a p-type or non-doped polycrystalline silicon,
`at a temperature of an etched mass of more than 150° C.,
`a taper etching having an inclination angle of the side
`wall of the etched mass of more than 90'’ can be ob
`tained. For an n-type polycrystalline silicon, at a tem
`perature of more than 150° C., side etching or undercut
`pro?le is obtained.
`As described above, a carbon-bearing etching gas
`may cause deposition of a polymer onto a wall of an
`etching chamber, which may result in contamination by
`particles in products. Further, a carbon-bearing etching
`gas may reduce the etching selectivity of a material
`such as polycrystalline silicon on silicides. Accordingly,
`the etching gas used in a process of the present inven
`tion preferably does not contain a carbon-bearing com
`ponent. Similarly, the etching chamber preferably does
`
`50
`
`60
`
`65
`
`Temperature of mass to be ashed
`Gas pressure
`
`0-170‘ C.
`01-10 Torr
`
`LAM Exh 1006-pg 10
`
`

`
`5
`-continued
`Oxygen gas concentration
`Gases added to ox en as
`CF4
`N;
`H20
`Plasma generating
`microwave power
`Treatment time
`
`0.1-5 s/m
`
`0.1-25%
`3-l00%
`IOU-300%
`HID-3W0 W
`
`5-6(X) sec
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1A to 1C show the main steps of dry etching
`an upper layer of polycrystalline silicon on a lower
`layer of polycrystalline silicon;
`FIG. 2 is a perspective view showing an etching
`residue resulting from dry etching as shown in FIGS.
`1A to IC;
`FIG. 3 a schematics] view of an apparatus for plasma
`etching used in a process according to the present in
`vention;
`FIGS. 4A To 4E are sectional views of patterns
`etched in accordance with a process of the present
`invention;
`FIG. 5 shows relationships of the taper angle obtain
`able by the dry etching and the temperature of a wafer
`during etching;
`FIG. 6 is a schematical view of an apparatus for
`plasma etching used in an Example of the present inven
`tion;
`FIG. 7 shows a relationship of the etching selectivity
`of polycrystalline silicon to SiOz and the carbon content
`in etching gas;
`FIG. 8 is a schematical view of an apparatus for
`down?ow treating;
`_
`FIGS. 9A and 9B show front and side views of an
`apparatus for ashing; and
`FIGS. 10A to 10D schematically show patterns ob
`tainable by various ashing processes.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`Before describing the present invention in detail, the
`prior art is brie?y illustrated using FIGS. 1A to IC
`illustrate the steps of an reaction ion etching RIE of an
`45
`upper polycrystalline silicon layer on a step portion of a
`lower polycrystalline silicon layer. In FIG. 1A, 1 de
`notes a silicon substrate, 2 an insulating ?lm, 3 a ?rst
`polycrystalline silicon layer, 4 an insulating ?lm, and 5
`a second polycrystalline silicon layer deposited by
`CVD. The second layer 5 has different thickness A and
`B over ?at and step portions of the ?rst layer 3; wherein
`the thickness B of the second layer over the step portion
`is larger than the thickness A over the ?at portion.
`When this structure is subject to RIE, a portion 7 of the
`second polycrystalline silicon layer near the step por
`tion of the ?rst polycrystalline silicon layer 3 remains
`unetched, as seen in FIG. 1B. This remaining portion 7
`may cause a short circuit between adjacent wiring pat
`terns of the second polycrystalline silicon layer, as seen
`in FIG. 2. If the second polycrystalline silicon layer 5 is
`subject to overetching, to completely remove the por
`tion 7, the insulating ?lms 2 and 4 are undesirably exces
`sively etched as seen in FIG. 1C. This is because of a
`relatively low selectivity of etching between the poly
`crystalline silicon and the insulating ?lms.
`The present invention is now described in more de
`tail.
`
`55
`
`65
`
`15
`
`25
`
`30
`
`35
`
`5,316,616
`6
`FIG. 3 shows a reactive ion etching (RIE) apparatus
`used in the following example. In this apparatus, a wafer
`11 is electrostatically mounted to an electrostatic chuck
`12 by applying a voltage of $1500 V to the chuck 12
`through low pass ?lters 13, from a DC power source 14.
`A gas, for example, helium under a pressure of 0-20
`Torr, is introduced between the wafer and the chuck 12,
`through a gas inlet 21 from a pressure-adjusting unit
`(not shown), to facilitate thermal conduction. The tem
`perature of the electrode 15 is controlled by cooling
`water 16. When the electrode 15 is to be cooled to less
`than 0° C., the cooling liquid is composed of methanol,
`a mixture of water and ethylene glycol, or a mixture of
`water and methanol. An etching chamber 22 is evacu
`ated through an exhaust port 20 by a vacuum pump (not
`shown). An etching gas is introduced to the chamber 22
`through a gas introducing port 19, and a high frequency
`wave is applied to the gas by an RF generator 18
`through a matching box 17, to generate a plasma and
`thereby carry out an etching.
`The temperature of the wafer 11 during etching is
`detected by a ?uorescent thermometer 24. A fluores
`cent material 26 is applied on a rear side surface of the
`wafer 11, and a pulse light is irradiated to the ?uores
`cent material 26 through a glass ?ber 23 passing through
`a pore 25 of the electrode 15, and a ?uorescent light
`generated from the ?uorescent material 26 is observed
`through the same glass ?ber 23 to determine the temper
`ature of the wafer 11. The fluorescent thermometer 24
`used is the LUXTRON 750 marketed by LUXTRON
`(1060 Terra Bella Avenue, Mountain View, CA 94043,
`U.S.A.). This thermometer can advantageously pre
`cisely determine the wafer temperature without inter
`ference by noise from the RF, since it uses a glass ?ber;
`unlike a conventional thermocouple which cannot
`block the noise from the RF. This precise determination
`of the water temperature is essential to the present in
`vention.
`The temperature of a wafer depends on the etching
`gas, pressure, RF power, etc., but can be controlled,
`even when these conditions are ?xed, by changing the
`temperature of the cooling liquid 16 to change the tem
`perature of the electrode 15, by changing the kind or
`pressure of the gas such as He introduced between the
`wafer 11 and the electrostatic chuck 12, or by changing
`the voltage applied to the chuck 12 to change the force
`attracting the wafer 11, to change the thermal conduc
`tion between the wafer 11 and the electrode 15.
`FIGS. 4A to 4D show cross sections of a phosphorus
`doped n-type polycrystalline silicon (resistance 60
`O/crn2) pattern etched in accordance with the present
`invention and using an apparatus shown in FIG. 3. In
`FIGS. 4A and 4B, reference numeral 38 denotes a mask
`of a photoresist, SiO2, Si3N4, etc., 33 denotes a poly
`crystalline silicon layer to be etched, 32 denotes an
`underlying insulating ?lm of S102, etc., and 31 denotes
`a silicon substrate. The etching conditions are as fol
`lows: a gas of Br; (16 SCCM)+I-Ie (57 SCCM), a pres
`sure of 0.1 Torr, a power of 300 W, and 100% overetch
`ing after etching the polycrystalline silicon layer 33.
`FIG. 4A shows a pattern etched at 80° C.; FIG. 4B a
`pattern etched at 0° C.; and FIG. 4C a pattern etched at
`160° C.; and FIG. 4D a pattern etched at 200° C. In
`these ?gures the angle of inclination of a side wall 39 of
`the etched pattern 33 is designated by the mark 0. The
`angle 0 is about 90° in FIG. 4A, about 60° in FIG. 4B.
`As seen in these ?gures, varied etching shapes are ob
`tainable by changing only the temperature of a wafer.
`
`LAM Exh 1006-pg 11
`
`

`
`8
`EXAMPLE 4
`A sample prepared in accordance with the proce
`dures of Example 3 was etched under the same condi
`tions as in Example 2, followed by an overetching of the
`polycrystalline silicon for the same time as required for
`the former etching.
`The results are shown in Table 1.
`
`EXAMPLE 5
`The same sample as in Example 1 was etched under a
`supply of an etching gas of 25 SCCM - HBr+ 57 SCCM
`- He, a pressure of 0.12 Torr, a power of 350 W, He
`supplied between the wafer and the chuck at 10 Torr, a
`cooling liquid temperature of — 15° C., and an electrode
`temperature of — 10° C. The maximum wafer tempera
`ture was 5° C.
`The results are shown in Table 1.
`
`EXAMPLE 6
`As in Example 5, etching was carried out under a
`cooling liquid temperature of 20‘ C., an electrode tem
`perature of 20° C., and an He pressure of 2 Torr. The
`maximum wafer temperature was 50’ C. Overetching
`was carried out for the same time as required for the
`former etching.
`The rebults are shown in Table 1.
`TABLE 1
`Wafer Etchingl)
`Etchingz)
`temp.
`rate
`(‘C.)
`(nm/min) selectivity
`0
`150
`10
`50
`200
`23
`0
`150
`30
`50
`200
`50
`5
`100
`15
`50
`170
`27
`
`Mask
`Resist
`R6515!
`SiO;
`S02
`RCSiSl
`Resist
`
`' Etching
`inclination
`angle 0
`57°
`82"
`62'
`89"
`62'
`92°
`
`Ex.
`l
`2
`3
`4
`5
`6
`
`5
`
`15
`
`20
`
`25
`
`35
`
`5,316,616
`7
`FIG. 5 shows the relationship between the inclination
`angle 0 of an etched polycrystalline silicon and a tem
`perature of the wafer, in which n-type doped and non
`doped polycrystalline silicons are etched with a mask of
`a photoresist or SiOg. In FIG. 5, the black triangles
`represent an n-type doped polycrystalline silicon etched
`with a photoresist mask; the black circles represent an
`n-type doped polycrystalline silicon etched with an
`SiOz mask; the white triangles represent a non-doped
`polycrystalline silicon etched with a photoresist mask;
`and, the white circles represent a non-doped polycrys
`talline silicon etched with an SiOg mask. As seen in
`FIG. 5, an angle of inclination of an etched pattern of
`less than 90° is obtained at a wafer temperature of —40°
`to +50‘ and the inclination angle is increased with an
`increase of the wafer temperature in the above tempera
`ture range. This relationship is represented by the for
`mula: 0=t/2+65;t_5, i.e., t/2+60§0§t/2+70,
`wherein t stands for the wafer temperature. At a wafer
`temperature of 50° C. to 150° C., the polycrystalline
`silicons are etched substantially vertically, i.e., the incli
`nation angle 0 is about 90°. At a wafer temperature of
`more than 150° C., for a non-doped polycrystalline
`silicon, the inclination angle _0 of the etched polycrystal
`line silicons may be more than 90° as shown in FIG. 4E.
`Note that, at a wafer temperature of more than about
`150° C., the photoresist may be burnt and special heat
`treatment such as deep UV cure is required. Accord
`ingly, a desired inclination angle 0 of an etched poly
`crystalline silicon pattern can be obtained by changing
`the wafer temperature. At a wafer temperature of less
`than —40° C., an appropriate etching cannot be carried
`and needle-like residues remain.
`
`EXAMPLE 1
`An SiOz layer having a thickness of 20 nm, on which
`a phosphorus-doped polycrystalline silicon layer (resis
`tance 20 ?/cmz) was deposited to a thickness of 400 nm,
`was thermally grown on the surface of a silicon sub
`strate. A photoresist pattern was formed on the phos
`phorus-doped polycrystalline silicon layer by a usual
`photolithography technique. The substrate or wafer
`was mounted in the apparatus as shown in FIG. 3, and
`an RIE was carried out under a supply of an etching gas
`of 16 SCCM - Br2+57 SCCM - He, a pressure of 0.1
`Torr, a power of 300 W, He supplied between the wafer
`and the electrostatical chuck at 10 Torr, a cooling liquid
`temperature of — 15° C., and an electrode temperature
`of -10° C. The maximum wafer temperature was 0° C.
`The results are shown in the following Table 1. The
`width of the etched polycrystalline silicon pattern was
`the same as that of the mask.
`
`. I)Etching rate is that of the polycrystalline silicon
`2)Etching selectivity is that of polycrystalline silicon to SiOZ.
`‘The angles 82', 89' and 92' are considered substantially vertical.
`
`45
`
`50
`
`EXAMPLE 2
`The procedures of Example 1 were repeated except
`that the cooling liquid temperature was 25° C., the elec
`trode temperature was 25" C., and the He pressure was
`2 Torr. The maximum wafer temperature was 50° C.
`The results are shown in Table 1.
`
`55
`
`EXAMPLE 3
`After a phosphorus-doped polycrystalline silicon
`layer was deposited, and a CVD SiOz layer having a
`thickness of 100 nm was grown thereon and patterned
`by a usual photolithography technique using RIE with
`photoresist. After removing the photoresist, the proce
`dures of Example 1 were repeated.
`The results are shown in Table 1.
`
`65
`
`EXAMPLES 7-14
`A sample prepared as in Example 3 was etched under
`a supply of an etching gas of 50 SCCM - HBr, a power
`of 0.1 Torr, a power of 300 W (a power density of 0.66
`W/cmZ), and He supplied between the wafer and the
`chuck at 10 Torr. The electrode temperature was con
`trolled by heating with a heater arranged in the elec
`trode, to within 80° C. to 300° C.
`The results are shown in Table 2.
`TABLE 2
`Etching
`Wafer Etching
`inclination
`Etching
`temp.
`rate
`(‘C.)
`(nm/min) selectivity angle 0
`Mask
`80' C.
`300
`30
`vertical (90°)
`SiO;
`SiO; 100' C.
`310
`31
`vertical (90')
`SiO; 130' C.
`320
`32
`vertical (90')
`SiO; 150' C.
`330
`33
`vertical (90')
`SiOg
`160' C.
`320
`32
`slightly undercut
`(as in FIG. 4C)
`undercut
`(as in FIG. 4D)
`undercut
`(as in FIG. 4D)
`undercut
`(as in FIG. 4D)
`
`Ex.
`7
`8
`9
`10
`ll
`
`12
`
`13
`
`SiO;
`
`180' C.
`
`310
`
`26
`
`SiOg 200° C.
`
`300
`
`14
`
`SD; 300' C.
`
`240
`
`LAM Exh 1006-pg 12
`
`

`
`5,316,616
`10
`about 290 nm/min, with an etching selectivity of the
`polycrystalline silicon to the $10; was 82.
`The results are shown in Table 3.
`
`9
`EXAMPLE 15
`FIG. 6 shows a parallel plan-type apparatus for RIE
`used in these Examples, in which 41 denotes a wafer, 42
`an etching chamber, 43 an upper electrode, 44 a lower 5
`electrode, 45 an electrostatic chuck, 46 a block of quartz
`glass for holding a wafer, 47 a DC power source for
`eleetrostatical attraction of a wafer, 48 a high frequency
`power, 49 a gas inlet, and 50 a gas outlet. The wafer
`temperature was determined by a ?uorescent thermom- 10
`eter, not shown. The walls of the etching chamber 42
`and the surface of the upper ‘electrode 42 are covered
`with quartz glass or a material that does not contain
`carbon.
`
`EXAMPLE 17
`The procedures of Example 15 were