TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`DW OR N PACKAGE
`(TOP VIEW)
`
`20
`19
`18
`17
`16
`15
`14
`13
`12
`11
`
`VCC
`SYSTEM CLOCK
`I/O CLOCK
`ADDRESS INPUT
`DATA OUT
`CS
`REF +
`REF –
`INPUT A10
`INPUT A9
`
`1 2 3 4
`
`5 6 7 8 9 1
`
`
`
`0
`
`INPUT A0
`INPUT A1
`INPUT A2
`INPUT A3
`INPUT A4
`INPUT A5
`INPUT A6
`INPUT A7
`INPUT A8
`GND
`
`I/O CLOCK
`ADDRESS INPUT
`DATA OUT
`CS
`REF +
`
`FN PACKAGE
`(TOP VIEW)
`
`YSTEM CLOCK
`CC
`
`V S
`
`INPUT A0
`INPUT A1
`INPUT A2
`
`3 2 1 20 19
`18
`17
`16
`15
`14
`9 10 11 12 13
`
`4 5 6 7 8
`
`REF–
`INPUT A10
`INPUT A9
`GND
`INPUT A8
`
`INPUT A3
`INPUT A4
`INPUT A5
`INPUT A6
`INPUT A7
`
`
`
`
`
`D 10-Bit Resolution A/D Converter
`D Microprocessor Peripheral or Standalone
`Operation
`D On-Chip 12-Channel Analog Multiplexer
`D Built-In Self-Test Mode
`D Software-Controllable Sample-and-Hold
`Function
`D Total Unadjusted Error . . . ±1 LSB Max
`D Pinout and Control Signals Compatible
`With TLC540 and TLC549 Families of 8-Bit
`A/D Converters
`D CMOS Technology
`
`PARAMETER
`Channel Acquisition Sample Time
`Conversion Time (Max)
`Samples Per Second (Max)
`Power Dissipation (Max)
`
`VALUE
`5.5 m s
`21 m s
`32 × 103
`6 mW
`
`
`
`description
`
`The TLC1541 is a CMOS A/D converter built
`around a 10-bit switched-capacitor successive-
`approximation A/D converter. The device is
`designed for serial interface to a microprocessor
`or peripheral using a 3-state output with up to four
`control inputs (including independent SYSTEM
`CLOCK, I/O CLOCK, chip select [CS], and
`ADDRESS INPUT). A 2.1-MHz system clock for
`the TLC1541, with a design
`that includes
`simultaneous read/write operation, allows high-
`speed data transfers and sample rates up to
`32 258 samples per second. In addition to the
`high-speed converter and versatile control logic,
`there is an on-chip, 12-channel analog multiplexer
`that can be used to sample any one of 11 inputs
`or an internal self-test voltage and a sample-and-
`hold function that operates automatically.
`
`AVAILABLE OPTIONS
`PACKAGE
`PLASTIC CHIP
`CARRIER
`(FN)
`TLC1541CFN
`
`SMALL
`OUTLINE
`(DW)
`TLC1541CDW
`
`PLASTIC
`DIP
`(N)
`TLC1541CN
`
`TLC1541IDW
`
`TLC1541IFN
`
`TLC1541IN
`
`TA
`
`0°C to 70°C
`– 40°C to 85°C
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`
`PRODUCTION DATA information is current as of publication date.
`Products conform to specifications per the terms of Texas Instruments
`standard warranty. Production processing does not necessarily include
`testing of all parameters.
`
`Copyright  1996, Texas Instruments Incorporated
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`1
`
`TCL Ex. 1212, Page 1
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`description (continued)
`
`
`
`The converters incorporated in the TLC1541 feature differential high-impedance reference inputs that facilitate
`ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally
`switched-capacitor design allows low-error conversion in 21 m s over the full operating temperature range.
`The TLC1541 is available in DW, FN, and N packages. The C-suffix versions are characterized for operation
`from 0°C to 70°C. The I-suffix versions are characterized for operation from –40°C to 85°C.
`
`REF+
`14
`
`REF–
`13
`
`10-Bit
`Switched-Capacitors
`Analog-to-Digital
`Converter
`
`10
`
`10
`
`Output
`Data
`Register
`
`10-to-1 Data
`Selector and
`Driver
`
`16
`
`DATA
`OUT
`
`Sample and
`Hold
`
`4
`
`Input Address
`Register
`
`functional block diagram
`
`12-Channel
`Analog
`Multiplexer
`
`1 2 3 4 5 6 7 89 1
`
`1
`12
`
`ANALOG
`INPUTS
`
`Self-Test
`Reference
`
`4
`
`Input
`Multiplexer
`
`2
`
`4
`
`Control Logic
`and I/O
`Counters
`
`ADDRESS
`INPUT
`
`I/O CLOCK
`
`CS
`SYSTEM
`CLOCK
`
`17
`
`18
`15
`
`19
`
`typical equivalent inputs
`
`INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
`
`INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
`
`1 kW TYP
`
`INPUT
`A0 – A10
`
`Ci = 60 pF TYP
`(equivalent input
`capacitance)
`
`INPUT
`A0 – A10
`
`5 MW TYP
`
`2
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL Ex. 1212, Page 2
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`
`
`operating sequence
`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`I/O
`CLOCK
`
`CS
`
`ADDRESS
`INPUT
`
`DATA
`OUT
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`Access
`Cycle B
`
`Sample
`Cycle B
`
`See Note C
`
`MSB
`
`LSB
`
`B3 B2 B1 B0
`
`Don’t Care
`
`Don’t Care
`
`tconv
`
`See Note A
`
`twH(CS)
`
`HI-Z State
`
`Access
`Cycle C
`
`Sample
`Cycle C
`
`MSB
`
`LSB
`
`C3 C2 C1 C0
`
`Don’t Care
`
`A9
`
`A8 A7 A6 A5 A4 A3 A2 A1 A0
`
`B9
`
`B8 B7 B6 B5 B4 B3 B2 B1 B0
`
`Previous Conversion Data A
`
`A9
`
`Conversion Data B
`
`HI-Z
`State
`
`B9
`
`LSB MSB
`
`MSB
`
`MSB
`(see Note B)
`NOTES: A. The conversion cycle, which requires 44 system clock periods, initiates on the tenth falling edge of the I/O clock after CS goes low
`for the channel whose address exists in memory at that time. When CS is kept low during conversion, the I/O clock must remain
`low for at least 44 system clock cycles to allow the conversion to complete.
`B. The most significant bit (MSB) is automatically placed on the DATA OUT bus after CS is brought low. The remaining nine bits (A8–A0)
`clock out on the first nine I/O clock falling edges.
`C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a
`chip-select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in
`address data until the minimum chip-select setup time elapses.
`
`LSB MSB
`
`absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
`
`Supply voltage, VCC (see Note 1)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`6.5 V
`Input voltage range, VI (any input)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`–0.3 V to VCC + 0.3 V
`Output voltage range, VO
`–0.3 V to VCC + 0.3 V
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`±10 mA
`Peak input current (any input)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`±30 mA
`Peak total input current (all inputs)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`0°C to 70°C
`Operating free-air temperature range, TA: C suffix
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`–40°C to 85°C
`I suffix
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`–65°C to 150°C
`Storage temperature range, Tstg
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`260°C
`Case temperature for 10 seconds, TC: FN package
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`260°C
`Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package
`. . . . . . . . . . .
`† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
`functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
`implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
`NOTE 1: All voltage values are with respect to digital ground with REF – and GND wired together (unless otherwise noted).
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`3
`
`TCL Ex. 1212, Page 3
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`recommended operating conditions
`
`Supply voltage, VCC
`Positive reference voltage, Vref + (see Note 2)
`Negative reference voltage, Vref – (see Note 2)
`Differential reference voltage, Vref + – Vref – (see Note 2)
`Analog input voltage (see Note 2)
`High-level control input voltage, VIH
`Low-level control input voltage, VIL
`Input/output clock frequency, fclock(I/O)
`System clock frequency, fclock(SYS)
`Setup time, address bits before I/O CLOCK↑, tsu(A)
`Hold time, address bits after I/O CLOCK↑, th(A)
`
`Setup time, CS low before clocking in first address bit, tsu(CS)
`(see Note 3 and Operating Sequence)
`
`Pulse duration, CS high during conversion, twH(CS) (see Operating Sequence)
`
`Pulse duration, SYSTEM CLOCK high, twH(SYS)
`Pulse duration, SYSTEM CLOCK low, twL(SYS)
`Pulse duration, I/O CLOCK high, twH(I/O)
`Pulse duration, I/O CLOCK low, twL(I/O)
`
`fclock(SYS) ≤ 1048 kHz
`fclock(SYS) > 1048 kHz
`fclock(I/O) ≤ 525 kHz
`fclock(I/O) > 525 kHz
`
`
`
`SystemSystem
`
`I/O
`I/O
`
`C suffix
`
`
`
`UNIT
`V
`V
`V
`V
`V
`V
`V
`MHz
`MHz
`ns
`ns
`System
`clock
`cycles
`System
`clock
`cycles
`ns
`ns
`ns
`ns
`
`
`
`nsns
`
`ns
`ns
`
`
`
`°C°C
`
`MIN
`4.75
`2.5
`– 0.1
`1
`0
`2
`
`0
`fclock(I/O)
`400
`0
`
`3
`
`44
`
`210
`190
`404
`404
`
`0
`
`MAX
`NOM
`5.5
`5
`VCC VCC + 0.1
`0
`2.5
`VCC VCC + 0.2
`VCC
`
`0.8
`1.1
`2.1
`
`30
`20
`100
`40
`70
`
`85
`– 40
`I suffix
`NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
`to REF – convert as all zeros (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF – voltage.
`Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
`3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three system clock cycles (or less) after
`a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in
`an address until the minimum chip select setup time elapses.
`4. The amount of time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
`of normal room temperature, the devices function with input clock transition time as slow as 2 m s for remote data acquisition
`applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
`
`
`
`Clock transition time (see Note 4)Clock transition time (see Note 4)
`
`
`
`Operating free-air temperature TAO erating free-air tem erature, TA
`
`4
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL Ex. 1212, Page 4
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`
`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`electrical characteristics over recommended operating temperature range,
`VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 1.1 MHz, fclock(SYS) = 2.1 MHz (unless otherwise noted)
`TYP† MAX
`PARAMETER
`TEST CONDITIONS
`MIN
`UNIT
`IOH = 360 m A
`High-level output voltage (terminal 16)
`VCC = 4.75 V,
`2.4
`V
`Low-level output voltage
`VCC = 4.75 V,
`IOL = 3.2 mA
`V
`VO = VCC,
`CS at VCC
`VO = 0,
`CS at VCC
`VI = VCC
`VI = 0
`CS at 0 V
`Selected channel at VCC,
`Unselected channel at 0 V
`
`0.4
`10
`– 10
`2.5
`– 2.5
`2.5
`
`0.005
`– 0.005
`1.2
`
`0.4
`
`1
`
`
`
`m Am A
`
`m A
`m A
`mA
`
`m A
`m A
`
`Selected channel at 0 V,
`Unselected channel at VCC
`CS at 0 V
`Vref+ = VCC,
`
`– 0.4
`
`1.3
`7
`5
`
`– 1
`
`3
`55
`15
`
`mA
`
`
`
`pFpF
`
`VOH
`VOL
`
`
`
`IOZIOZ
`
`IIH
`IIL
`ICC
`
`
`
`High impedance state output currentHigh-impedance-state output current
`
`High-level input current
`Low-level input current
`Operating supply current
`
`Selected channel leakage current
`Selected channel leakage current
`
`ICC + Iref
`
`Supply and reference current
`
`Analog inputs
`
`CiCi
`Control inputs
`† All typical values are at VCC = 5 V and TA = 25°C.
`
`
`
`Input capacitanceInput capacitance
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`5
`
`TCL Ex. 1212, Page 5
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`operating characteristics over recommended operating temperature range,
`VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 1.1 MHz, fclock(SYS) = 2.1 MHz
`PARAMETER
`TEST CONDITIONS
`Linearity error
`See Note 5
`Zero-scale error
`See Notes 2 and 6
`Full-scale error
`See Notes 2 and 6
`Total unadjusted error
`See Note 7
`
`MIN
`
`EL
`EZS
`EFS
`ET
`
`Self-test output code
`
`Input A11 address = 1011 (see Note 8)
`
`0111110100
`(500)
`
`tconv
`
`Conversion time
`Total access and conversion time
`
`Channel acquisition time (sample cycle)
`
`See Operating Sequence
`
`
`
`MAX
`± 1
`± 1
`± 1
`± 1
`1000001100
`(524)
`
`21
`31
`
`6
`
`UNIT
`LSB
`LSB
`LSB
`LSB
`
`m s
`m s
`I/O
`clock
`cycles
`
`tv
`
`See Figure 1
`
`10
`
`ns
`
`Time output data remains valid after I/O
`CLOCK↓
`Delay time, I/O CLOCK↓ to DATA OUT valid
`ns
`400
`td
`ns
`150
`Output enable time
`ten
`ns
`150
`Output disable time
`tdis
`ns
`300
`tr(bus) Data bus rise time
`ns
`300
`tf(bus) Data bus fall time
`NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
`to REF – convert as all zeros (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF – voltage.
`Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
`5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
`6. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
`difference between 1111111111 and the converted output for full-scale input voltage.
`7. Total unadjusted error includes linearity, zero-scale, and full-scale errors.
`8. Both the input address and the output codes are expressed in positive logic. The A11 analog input signal is internally generated and
`used for test purposes.
`
`6
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL Ex. 1212, Page 6
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`
`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`PARAMETER MEASUREMENT INFORMATION
`
`1.4 V
`
`3 kW
`
`Output
`Under Test
`CL
`(see Note A)
`
`Test
`Point
`
`Output
`Under Test
`CL
`(see Note A)
`
`Test
`Point
`
`3 kW
`
`Output
`Under Test
`CL
`(see Note A)
`
`VCC
`
`3 kW
`
`Test
`Point
`
`LOAD CIRCUIT FOR
`td, tr, AND tf
`
`See Note B
`
`LOAD CIRCUIT FOR
`tPZH AND tPHZ
`
`See Note B
`
`LOAD CIRCUIT FOR
`tPZL AND tPLZ
`
`CS
`
`SYSTEM
`CLOCK
`
`50%
`
`Output Waveform 1
`(see Note C)
`
`See Note B
`
`Output Waveform 2
`(see Note C)
`
`tPZL
`
`tPZH
`
`tPLZ
`
`10%
`
`tPHZ
`
`90%
`
`50%
`
`50%
`
`VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
`
`VCC
`
`0 V
`
`VCC
`
`0 V
`
`VOH
`
`0 V
`
`I/O CLOCK
`
`DATA OUT
`
`0.4 V
`
`td
`
`Output
`
`tr(bus)
`
`2.4 V
`
`0.4 V
`
`tf(bus)
`
`VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
`
`2.4 V
`0.4 V
`
`VOLTAGE WAVEFORMS FOR DELAY TIME
`
`NOTES: A. CL = 50 pF
`B.
`ten = tPZH or tPZL and tdis = tPHZ or tPLZ.
`C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
`Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
`Figure 1. Load Circuits and Voltage Waveforms
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`7
`
`TCL Ex. 1212, Page 7
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`simplified analog input analysis
`
`APPLICATION INFORMATION
`
`
`
`Using the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 V to
`VS within 1/2 LSB can be derived as follows:
`The capacitance charging voltage is given by
`(
`)
`VC = VS 1–e –tc/RtCi
`
`(1)
`
`(2)
`
`(3)
`
`(4)
`
`(5)
`
`where
`
`Rt = Rs + ri
`
`The final voltage to 1/2 LSB is given by
`VC (1/2 LSB) = VS – (VS/2048)
`
`Equating equation 1 to equation 2 and solving for time (tc) gives
`VS –(VS/2048) = VS 1–e(
`)
`–tc/RtCi
`
`and
`
`tc (1/2 LSB) = Rt × Ci × ln(2048)
`Therefore, with the values given, the time for the analog input signal to settle is
`) × 55 pF × ln(2048)
`tc (1/2 LSB) = (Rs + 1 kW
`This time must be less than the converter sample time shown in the timing diagrams.
`
`Driving Source†
`
`TLC1541
`
`VS
`
`Rs
`
`VI
`
`ri
`
`1 kW
`
` MAX
`
`VC
`
`Ci
`55 pF MAX
`
`VI = Input Voltage at INPUT A0 – A10
`VS = External Driving Source Voltage
`Rs = Source Resistance
`ri = Input Resistance
`Ci = Input Capacitance
`
`† Driving source requirements:
`• Noise and distortion levels for the source must be at least
`equivalent to the resolution of the converter.
`• Rs must be real at the input frequency.
`
`Figure 2. Equivalent Input Circuit Including the Driving Source
`
`8
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`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL Ex. 1212, Page 8
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`
`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`PRINCIPLES OF OPERATION
`
`The TLC1541 is a complete data acquisition system on a single chip. The device includes such functions as sample
`and hold, 10-bit A/D converter, data and control registers, and control logic. For flexibility and access speed, there
`are four control inputs: chip select (CS), address input, I/O clock, and system clock. These control inputs and a
`TTL-compatible, 3-state output are intended for serial communications with a microprocessor or microcomputer. The
`TLC1541 can complete conversions in a maximum of 21 m s, while complete input-conversion output cycles can be
`repeated at a maximum of 31 m s.
`The system and I/O clocks are normally used independently and do not require any special speed or phase
`relationships between them. This independence simplifies the hardware and software control tasks for the device.
`Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
`software need only be concerned with addressing the desired analog channel, reading the previous conversion result,
`and starting the conversion by using I/O CLOCK. SYSTEM CLOCK drives the conversion-crunching circuitry so that
`the control hardware and software need not be concerned with this task.
`
`When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature
`allows each of these terminals, with the exception of the CS terminal, to share a control logic point with its counterpart
`terminals on additional A/D devices when using additional TLC1541 devices. In this way, the above feature serves
`to minimize the required control logic terminals when using multiple A/D devices.
`
`The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
`the conversion result. A normal control sequence is:
`
`1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two
`rising edges and then a falling edge of SYSTEM CLOCK after a low CS transition before recognizing the
`low transition. This technique protects the device against noise when the device is used in a noisy
`environment. The MSB of the previous conversion result automatically appears on DATA OUT.
`
`2. A new positive-logic multiplexer address shifts in on the first four rising edges of I/O CLOCK. The MSB of
`the address shifts in first. The negative edges of these four I/O clock pulses shift out the second, third, fourth,
`and fifth most-significant bits of the previous conversion result. The on-chip sample-and-hold begins
`sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically
`involves the charging of internal capacitors to the level of the analog input voltage.
`
`3. Five clock cycles are then applied to the I/O CLOCK, and the sixth, seventh, eighth, ninth, and tenth
`conversion bits shift out on the negative edges of these clock cycles.
`
`4. The final tenth-clock cycle is applied to the I/O CLOCK. The falling edge of this clock cycle completes the
`analog sampling process and initiates the hold function. Conversion is then performed during the next 44
`system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low
`for at least 44 system-clock cycles to allow for the conversion function.
`
`CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
`conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. When glitches occur on I/O
`CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, when
`CS goes high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset
`condition, which aborts the conversion in progress.
`
`A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
`4 before the 44 system-clock cycles occur. Such action yields the conversion result of the previous conversion and
`not the ongoing conversion.
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`9
`
`TCL Ex. 1212, Page 9
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
`TLC1541
`10-BIT ANALOG-TO-DIGITAL CONVERTER
`WITH SERIAL CONTROL AND 11 INPUTS
`
`SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996
`
`
`
`PRINCIPLES OF OPERATION
`
`It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling-circuitry
`points must be minimized. In this case, the following special points must be considered in addition to the requirements
`of the normal control sequence previously described.
`
`1. This device requires the first two clocks to recognize that CS is at a valid low level when the common clock
`signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock
`signal is used for the conversion clock also.
`
`2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
`recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
`negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
`Also, upon shifting in the address, CS must be raised after the tenth valid (12 total) I/O CLOCK. Otherwise,
`additional common-clock cycles are recognized as I/O CLOCK cycles and shift in an erroneous address.
`
`For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
`This device accommodates these applications. Although the on-chip sample-and-hold begins sampling upon the
`negative edge of the fourth valid I/O CLOCK cycle, the hold function does not initiate until the negative edge of the
`tenth valid I/O CLOCK cycle. Thus, the control circuitry can leave the I/O CLOCK signal in its high state during the
`tenth valid I/O CLOCK cycle until the moment at which the analog signal must be converted. The TLC1541 continues
`sampling the analog input until the eighth valid falling edge of the I/O CLOCK. The control circuitry or software then
`immediately lowers the I/O CLOCK signal and holds the analog signal at the desired point in time and starts the
`conversion.
`
`10
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`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`TCL Ex. 1212, Page 10
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806
`
`

`
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`Copyright  1998, Texas Instruments Incorporated
`
`TCL Ex. 1212, Page 11
`TCL et al. v. Ericsson
`IPR2015-01674, -01676, -01761, -01806