(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2001/0003676 A1
`(43) Pub. Date:
`Jun. 14, 2001
`Marks et al.
`
`US 20010003676A1
`
`(54) COBALT SILICIDE ETCH PROCESS AND
`APPARATUS
`
`(75) Inventors: Steven Marks, Petaluma, CA (US);
`Leslie G. J erde, Novato, CA (US);
`Stephen P. DeOrnellas, Santa Rosa,
`CA (US)
`
`Correspondence Address:
`Sheldon R. Meyer
`FLIESLER, DUBB, MEYER & LOVEJOY LLP
`Suite 400
`Four Embarcadero Center
`San Francisco, CA 94111-4156 (US)
`
`(73) Assignee: Tegal Corporation
`
`(21)
`(22)
`
`Appl. No.:
`
`09/760,402
`
`Filed:
`
`Jan. 12, 2001
`
`Related US. Application Data
`
`(62) Division of application No. 09/454,814, ?led on Dec.
`3, 1999.
`
`Publication Classi?cation
`
`Int. Cl.7 ................................................ .. H01L 21/302
`US. Cl. .......................................... .. 438/710; 438/712
`
`(51)
`(52)
`(57)
`ABSTRACT
`Method and apparatus for etching a silicide stack including
`etching the silicide layer at a temperature elevated from that
`used to etch the rest of the layers in order to accomplish
`anisotropic etch.
`
`680
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`SUPPLY
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`SUPPLY
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`F’CIVER
`SUPPLY
`
`EXHIBIT 2004
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`Patent Application Publication
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`Jun. 14, 2001
`
`Sheet 1 0f 8 US 2001/0003676 Al
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`FIG. - 1
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`EXHIBIT 2004
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`Patent Application Publication
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`Jun. 14, 2001
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`Sheet 2 of 8
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`US 2001/0003676 A1
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`EXHIBIT 2004
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`Patent Application Publication
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`Jun. 14, 2001
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`Sheet 3 of 8
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`US 2001/0003676 A1
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`Patent Application Publication
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`Jun. 14, 2001
`
`Sheet 4 0f 8 US 2001/0003676 A1
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`EXHIBIT 2004
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`Patent Application Publication
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`Jun. 14, 2001
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`Sheet 5 0f 8 US 2001/0003676 A1
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`EXHIBIT 2004
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`Patent Application Publication
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`Jun. 14, 2001
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`Patent Application Publication
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`Jun. 14, 2001
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`Sheet 8 0f 8 US 2001/0003676 A1
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`EXHIBIT 2004
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`US 2001/0003676 A1
`
`Jun. 14, 2001
`
`COBALT SILICIDE ETCH PROCESS AND
`APPARATUS
`
`silicide. Further, the other layers can include, by Way of
`eXample, an oXide layer and/or polysilicon layers.
`
`FIELD OF THE INVENTION
`
`[0001] The present invention relates to silicide etch pro
`cesses and apparatus generally and, in particular, to cobalt
`silicide etch processes and apparatus.
`
`BACKGROUND OF THE INVENTION
`
`[0002] Since the sheet resistance of metal silicides is much
`loWer than polysilicon, metal silicides are commonly used as
`a cladding on polysilicon to reduce poWer consumption and
`the RC time constant in microelectronic integrated circuits.
`Of all knoWn silicides, cobalt silicide has the loWest sheet
`resistance and is thus the most desirable silicide for micro
`electronic integrated circuit use. The introduction of sili
`cides, and particularly of cobalt silicide, for microelectronic
`integrated circuit fabrication has, hoWever, been limited by
`the severe dif?culty of etching these materials. The reason
`for the etch dif?culty of cobalt silicide is that cobalt has no
`knoWn compounds that can serve as volatile etch reaction
`products at temperatures beloW 500° C. (Handbook of
`Chemistry and Physics).
`
`SUMMARY OF THE INVENTION
`
`[0003] Accordingly, the present invention has been devel
`oped to solve the problem of the etching of silicides and, in
`particular, cobalt silicide. The invention includes both a
`method and apparatus for accomplishing this task.
`[0004] The method of processing a silicide layer Which is
`included in a layer stack positioned on a substrate includes
`the steps, in any order, of performing a process Which can
`hold the substrate at a ?rst temperature and changing the
`temperature of the substrate in order to process the silicide
`layer at a second temperature.
`
`[0005] A method and apparatus of the invention provides
`for processing a silicide layer Which is included in the layer
`stack With another layer including the steps, in any order, of
`processing the silicide layer at an elevated temperature and
`processing another layer at a loWer temperature.
`
`[0006] More speci?cally, the process includes etching a
`layer stack including the silicide and at least one of an oXide
`and a polysilicon. The process includes performing the
`etching of the silicide at an elevated temperature and per
`forming the etching of the other layers at loWer tempera
`tures. Such a process can occur in a single etch reactor or in
`tWo etch reactors, With the silicide etch step occurring in a
`different reaction than the polysilicon etch step. By such a
`mechanism, anisotropic etching of both the silicide and the
`other layers can be accomplished. Additionally such a
`method utiliZes the rapid cooling and/or heating of the Wafer
`in order to bring the Wafer temperature to the appropriate
`range for etching of the relevant layer.
`[0007] In another preferred aspect of the invention, the
`silicide layer is etched at a temperature of 150° C. or above
`While the remaining layers of the layer stack are etched at
`approximately 80° C. or beloW.
`
`[0008] In an aspect of the invention, the silicide layer can
`preferably include cobalt silicide. Other silicide layers can
`include tantalum silicide, titanium silicide, or molybdenum
`
`[0009] The novel method is carried out in a novel appa
`ratus Which is designed for handling hard to process silicide
`?lms as Well as for effectively handling the remaining ?lm.
`Such an apparatus, preferably, has a high selectivity to oXide
`?lms. In particular, the unique apparatus includes a reactor
`having a tri-electrode con?guration. En one embodiment,
`the method is carried out in such a tri-electrode reactor
`having ?rst and second electrodes and a side peripheral
`electrode. The second electrode is provided With high and
`loW frequency poWer supplies. The side peripheral electrode
`can alternatively be provided With a high frequency poWer
`supply. This reactor includes a chuck Which can rapidly
`change and maintain the temperature of the Wafer at advan
`tageous levels in order to process silicide layers and, alter
`natively, to process other layers, including by Way of
`eXample, oXide layers and polysilicon layers.
`[0010] Alternatively, the silicide ?lms can be processed in
`a tri-electrode reactor chamber Wherein the chuck electrode
`is provided With loW and high frequency poWer supplies.
`The side peripheral electrode can be grounded or ?oating.
`Alternatively, the side peripheral electrode can be supplied
`With a loW frequency poWer supply. With such an arrange
`ment it is again preferable that the chuck is con?gurated in
`order to be able to rapidly change the temperature of the
`Wafer. Preferably for such an arrangement, other layers such
`as oXide and polysilicon layers can be processed in a
`separate reactor Which is ?rst described herein above With
`the high frequency poWer supply communicating With the
`side peripheral electrode.
`
`[0011] It is to be understood that the above described
`reactors are generally considered capacitively coupled reac
`tors and that other reactors including inductively coupled
`reactors can be used and be in accordance With the inven
`tion. Thus, still alternatively, the invention can be practical
`in an inductively coupled di-electrode or tri-electrode reac
`tor. In one embodiment, the top inductive coil electrode
`Would be at a high frequency and the bottom electrode
`associated With the chuck Would be at a loW frequency. Both
`steps of etching a silicide layer and a non-silicide layer could
`be performed in the same chamber. Such a inductively
`coupled reaction had multiple etch chambers, if desired, a
`silicide etch step could be performed in one chamber and a
`non-silicide etch step could be performed in another cham
`ber.
`
`[0012] Accordingly, an object of the invention includes
`using a unique combination of one or more of a preferred
`reactor con?guration, Wafer temperature and processing
`conditions to successfully meet the microelectronic inte
`grated circuit fabrication requirements for suicides generally
`and cobalt silicide in particular.
`[0013] The volatility problem With potential etch reaction
`products for cobalt makes the etchability of cobalt silicide
`similar in difficulty to platinum or iridium since these
`elements also have no knoWn volatile reaction products at
`conventional etch process Wafer temperatures. This inven
`tion teaches the use of the above reactor con?gurations, or
`other comparable reactors, the use of elevated Wafer tem
`peratures, the use of suitable hard mask materials, the
`process settings for gas chemistry, pressure, and RF poWer,
`and high speed changes in Wafer temperature to etch each of
`
`EXHIBIT 2004
`
`

`
`US 2001/0003676 Al
`
`Jun. 14, 2001
`
`the materials of a cobalt polycide stack. In particular the
`invention addresses the following in a variety of combina
`tions:
`
`[0014] 1. The Wafer temperature range, gas chemistry,
`pressure, and RF poWer, required to achieve high etch rate,
`and anisotropic etching of cobalt silicide With minimal etch
`rate and pro?le microloading.
`
`[0015] 2. The Wafer temperature range to simultaneously
`meet all the etch requirements of both the cobalt silicide and
`polysilicon layers in the cobalt polycide stack.
`
`[0016] 3. The use of rapid Wafer temperature changes,
`through a suitably designed Wafer chuck to etch each layer
`in the cobalt polycide stack to meet all etch requirements.
`
`[0017] 4. The use of suitable hard mask materials to
`facilitate elevated Wafer temperature etching and meet the
`mask requirements for etching cobalt polycide stack struc
`tures.
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`[0018] FIG. 1 depicts a side elevational vieW of the
`polysilicon stack partially etched in accordance With the
`invention.
`
`[0019] FIG. 2 depicts the ?rst embodiment of a reactor for
`carrying out the method of the invention.
`
`[0020] FIG. 3 depicts a second embodiment of a reactor
`for carrying out the method of the invention.
`
`[0021] FIG. 4 depicts a ?rst embodiment of a chuck
`mechanism for carrying out the method of the invention.
`
`[0022] FIG. 5 depicts a second embodiment of a chuck
`mechanism for carrying out the method of the invention.
`
`[0023] FIG. 6 depicts another embodiment of a reactor for
`carrying out the method of the invention.
`
`[0024] FIG. 7 depicts yet a further embodiment of a
`reactor for carrying out the method of the invention.
`
`[0025] FIG. 8 depicts a graph of Wafer temperature With
`respect to helium pressure in a Wafer backside delivery
`space for a chuck.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`[0026] The present method is bene?cial for etching a layer
`stack, including silicides and in particular a cobalt silicide.
`A cobalt polysilicide stack is depicted in FIG. 1. The
`embodiment depicted in FIG. 1 has been partially anisotro
`pically etched using the method of the invention. In FIG. 1,
`layers depicted include a photoresist mask layer 120, of the
`hard mask layer 122 such as a layer comprised of SiO2, a
`cobalt silicide layer (CoSi2) 124, a doped polysilicon layer
`126, a gate oXide layer (particularly SiO2) 128, and the
`silicon substrate 130. Other stacks of different materials With
`different silicides are Within the spirit and scope of the
`invention. The relative thicknesses of the various layers in a
`typical polyside stack in A units is given by the beloW Table
`1.
`
`TABLE 1
`
`Photoresist Mask
`Oxide hard Mask
`CoSi2
`
`Polysilicon Gate Oxide
`
`Silicon Substrate
`
`2000-5000 A
`1500-2000 A
`700-750 A
`
`700-750 50-60 A
`
`Various
`
`[0027] As the gate oXide layer is relatively thin, there is a
`requirement that the inventive process and reactor have a
`high selectivity to such oXide layer. There also needs to be
`a high selectivity to the hard mask so that there is little or no
`pattern degradation in the transfer of the pattern due to the
`erosion of the mask. It is bene?cial that this be accomplished
`and that the stack be etched anisotropically. Such results can
`occur With the stack When, by Way of example, the suicide
`layer is etched With the Wafer temperature above about 150°
`C. and preferably in the range of 170° C.-250° C. HoWever,
`the polysilicon layer and the oXide layers are preferably
`etched at a temperature of around 80° C. or beloW in order
`that they are anisotropically etched. With the capacitively
`coupled reactors described herein, the polysilicon etch can
`be in the range of about 80° C. to about 5° C. and be
`anisotropic. With the inductively coupled reactors described
`herein, the polysilicon etch can be in the range of about 80°
`C. to about negative 20° C. and be anisotropic. Above
`around 80° C. the polysilicon layer Will be etched isotropi
`cally, Which for many applications Would be undesirable.
`Accordingly, the present invention is able to accurately and
`rapidly control the temperature of the substrate so that in one
`reactor chamber, as shoWn for eXample in FIG. 2, layers of
`a single Wafer can be etched at a ?rst temperature and the
`Wafer temperature can be changed rapidly so that etching
`can occur at a second temperature, With both etch processes
`being anisotropic.
`[0028] With respect to the reactor of FIG. 2, anisotropic
`etching for the cobalt silicide layer can be successfully
`carried out using the parameters speci?ed beloW in Table 2.
`In this table, the etch gas is chlorine and the temperature of
`the Wafer during etching for the cobalt silicide layer is
`speci?ed. The pressure speci?ed is that of the main reactor
`chamber and the poWer applied to the high frequency and
`loW frequency poWer supplies is speci?ed. The high fre
`quency poWer supply is operated at 13.56 MHZ While the
`loW frequency poWer supply is operated at about 450 KHZ.
`In this process, the cobalt silicide is etched isotropically With
`etch times on the order of 20 sec. to 30 sec.
`
`TABLE 2
`
`Process
`
`
`
`FloW Cl2 SCCM
`
`
`
`Wafer Temp° C.
`
`
`
`Pressure (mT)
`
`
`
`HF: Watts
`
`
`
`LF: Watts
`
`1
`2
`3
`4
`
`90
`50
`70
`70
`
`220
`220
`220
`200
`
`6.5
`3.5
`5
`10
`
`800
`800
`800
`800
`
`200
`270
`140
`140
`
`[0029] A more preferred process than that speci?ed in
`Table 2 Would be With the temperature of the Wafer held at
`approximately 20° C.-30° C. loWer than the temperature
`speci?ed in Table 2 for purposes of etching the cobalt
`silicide layer. For this process, the chuck used Was that
`
`EXHIBIT 2004
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`

`
`US 2001/0003676 A1
`
`Jun. 14, 2001
`
`depicted in FIG. 4, Which chuck Will be described more
`fully herein below. This chuck is able to control the tem
`perature of the Wafer by controlling the pressure of helium
`held on the back side of the Wafer. Preferably, the helium is
`held at a pressure of about less than 1 torr in order to achieve
`the higher temperatures in the Wafer, With the range being
`150° C. and above. With helium pressuriZed at about 5-10
`torr on the back side of the Wafer, the Wafer settles to a loWer
`temperature of about 80° C. or beloW for etching of the oxide
`and polysilicon layers. It is to be understood that alterna
`tively the How rate of chlorine can be in the range of about
`5 SCCM to about 200 SCCM.
`
`[0030] On high density devices a phenomenon called
`microloading introduces etch rate variations. Microloading
`is a change in the local etch rate relative to the area of the
`material being etched. In one example of microloading, a
`large sparse area (leaving feW features after etching), Will
`load the etching process With removed material, sloWing the
`etching rate doWn in that area, While a smaller less sparse
`etch area proceeds at a faster rate. HoWever, in other
`situations, microloading can occur in dense areas. This
`arrangement is highly desirable for anisotropic etch With
`pro?les of greater than 86° and also for eliminating the
`above indicated microloading.
`
`[0031] For etching a cobalt silicide layer using the reactor
`of FIG. 6, the folloWing parameters of Table 3 are used.
`
`TABLE 3
`
`Main Chamber Pressure
`HF (MHZ)
`LF (KHZ)
`Cl2 Total FloW
`Wafer Backside Pressure
`SideWall Temperature
`Top Electrode Temperature
`Etch Time
`
`3.5-6.5 mT
`500-800 Watts
`50-270 Watts
`5-200 SCCM
`0T—10T
`80° C.
`80° C.
`20-30 sec
`
`[0032] This table indicates that the pressure in the cham
`ber is approximately 5 millitorr and that the pressure of the
`helium on the back side of the Wafer is about 5 torr in order
`to ensure that the Wafer is maintained at an elevated tem
`perature in order to have anisotropic etching of the cobalt
`silicide. Etch results from this process are shoWn beloW in
`Table 4.
`
`TABLE 4
`
`Wafer Temperature
`
`Etch Rate
`
`Pro?le of CoSi2
`
`90 c.
`130 C.
`170 C.
`210 C.
`
`2800 A/min
`3600 A/min
`4800 A/min
`5600 A/min
`
`80 degrees
`83 degrees
`84 degrees
`85 degrees
`
`[0033] With respect to Table 4, it is evident that the etch
`rate and the pro?le Was a function of temperature. The
`temperature is adjusted by adjusting the backside pressure.
`Typically the best results are achieved betWeen 170° C. and
`220° C. At about 250° C. the side Wall are almost vertical at
`about 89°.
`
`[0034] It is also to be understood that While the above
`chart shoWs that the How rate of chlorine is approximately
`50-90 SCCM, that additionally mixtures of chlorine and
`
`argon could be used. In such a process the chlorine gas ?oW
`rate Would be on the order of about 50 SCCM (but With a
`range of about 5 SCCM to about 200 SCCM) and the argon
`gas ?oW rate Would be on the order of about 20 SCCM.
`
`Tri-Electrode Reactors of FIGS. 2 and 3
`[0035] Referring to the ?gures and in particular to FIG. 2,
`a side cross-sectional vieW of an embodiment of the plasma
`etch reactor 220 of the invention is depicted. This reactor
`220 enhances and improves upon the reactor depicted and
`described in US. Pat. No. 4,464,223, Which patent is incor
`porated herein by reference.
`
`[0036] Reactor 220 includes a reactor chamber 222 Which
`is bounded by a grounded upper electrode 224, a side
`peripheral electrode 226, and a bottom electrode 228. In a
`preferred embodiment, the side peripheral electrode 226 is
`connected to a poWer supply 230 Which provides poWer to
`the side peripheral electrode 226 preferably at 13.56 MHZ at
`a poWer level of preferably up to about 1100 Watts. It is to
`be understood that this is a high frequency poWer supply
`(preferably in the radio frequency range) and that the fre
`quency preferably can range from about 2 MHZ to about 950
`MHZ. The poWer can also preferably be supplied in the range
`of 200 Watts to 3,000 Watts With a voltage of betWeen 100
`volts to 5,000 volts.
`
`[0037] A second poWer supply 232 is connected to the
`bottom electrode 228. The second poWer supply 232 is
`preferably operated at 450 KHZ With the poWer being
`preferably supplied at 30 Watts, and at a voltage of 200 volts.
`This is the loW frequency poWer supply. It is to be under
`stood that this poWer supply (preferably in the radio fre
`quency range) can be operated in the range of about 10 KHZ
`to about 1 MHZ With a poWer range of 2 Watts to 1,000 Watts,
`and a voltage range of 5 volts to 3,000 volts. It is to be
`understood that With current technology, the loWer limit of
`the high frequency poWer supply can overlap With the upper
`limit of the high frequency poWer supply as long as the high
`frequency and the loW frequency values actually chosen are
`spaced apart by 1 or 2 MHZ. As ?ltering netWorks improve
`such spacing may be eliminated. Also connected to the
`bottom electrode 228 is a DC poWer supply 234. The
`high-frequency poWer applied to the side electrode 226
`controls ion ?ux, While loW-frequency poWer applied to the
`bottom electrode 228 independently controls ion energy.
`
`[0038] It is the control of the poWer supplies and princi
`pally the high frequency poWer supply Which advanta
`geously controls the density of etch plasma in order to
`provide superior etch characteristics. Further, it is the design
`of reactor 220 Which provides the enhanced plasma density
`range from Which the optimal plasma density can be selected
`by the control of the poWer supply.
`[0039] Associated With the grounded upper electrode 224
`is a central noZZle 236 Which directs a jet of process gas into
`the reactor chamber 222 directed at the semiconductor Wafer
`248. The jets of process gas from the noZZle 236 are able to
`effectively reach the surface of the semiconductor Wafer 248
`and provide a fresh, uniform distribution of process gas over
`the entire surface of the semiconductor Wafer 248. Such
`noZZle design is one of many embodiments that could Work
`With the present invention.
`[0040] Immediately above the grounded upper electrode
`224 and the noZZle 236 is an exhaust stack 238, Which is
`
`EXHIBIT 2004
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`

`
`US 2001/0003676 A1
`
`Jun. 14, 2001
`
`used to exhaust spent gas species from the reactor chamber
`222. It is to be understood that a pump (not shoWn) is
`secured to the exhaust stack 238 in order to evacuate the gas
`species from the reactor chamber 222.
`
`[0041] As can be seen in FIG. 2, immediately beloW the
`upper electrode 224 and noZZle 236 is a protruding, periph
`eral baffle 240. Baf?e 240 is comprised of insulating mate
`rial, and protrudes into the exhaust path 242 betWeen the
`noZZle 236 and the housing 244 of the plasma etch reactor
`220. Protruding baffle 240 ensures that there is a good
`mixture of the various gas species from the noZZle 236 and
`the solid source 250 in the reactor chamber 222.
`
`[0042] Immediately beloW the protruding baffle 240 and in
`this embodiment incorporated into the side peripheral elec
`trode 226 is a magnet or plurality of magnets 246. Also
`preferably incorporated in upper electrode 224 is a magnet
`or plurality of magnets 247. Either one or both of these
`magnets 246 and 247 de?ne a magnetic con?nement cham
`ber about and coincident With the reactor chamber 222. This
`magnetic con?nement chamber ensure that the charged ion
`species in the reactor chamber do not leak therefrom, and
`that the charge ion species are concentrated about the
`semiconductor Wafer 248. This magnetic con?nement cham
`ber inhibits the charged ion species from contacting on the
`Walls of the reactor chamber 222.
`
`[0043] Covering the side peripheral electrode 226 and the
`magnets 246 is the above referenced side peripheral solid
`source 250. This solid source 250 provides for an innovative
`source of a gaseous species Which can be sputtered through
`the bombardment of, for example, radio frequency excited
`ions Which knock or erode atoms of the gas species from the
`solid source 250 into the reaction chamber 222. The erosion
`of gaseous species from the surface of the solid source can
`be affected by pulsing one or both of the above AC poWer
`supplies. As a further advantage, as portions of the surfaces
`of the solid source erode, no particles can be formed on the
`eroding surface by the combination of gaseous species.
`Thus, contamination from such particles formed on eroding
`portions of the solid surface are eliminated.
`
`[0044] Immediately beloW the solid source 250 is the
`electrostatic Wafer chuck 252 Which positions the semicon
`ductor Wafer 248 relative to the reactor chamber 222. Wafer
`centering ring 253 centers the Wafer 248 on the Wafer chuck
`252. In this embodiment, the Wafer chuck 252 as Well as the
`bottom electrode 228 can be moved vertically doWnWard in
`order to insert and remove the Wafer 248. As can be seen in
`FIGS. 2 and 3, a backside gas delivery space 255 is
`depicted. As described more fully With a description of the
`chuck, a gas such as helium can be selectively delivered to
`space 255 in order to selectively control the temperature of
`Wafer 248.
`
`[0045] In this embodiment, if desired, the side peripheral
`electrode 226 and the magnets 246 can be cooled using a
`cooling Water manifold 254. It is further to be understood
`that the solid source 250 can be heated if desired using a hot
`Water manifold 256. Other methods of heating the solid
`source 250, and particularly the front exposed surface
`thereof, include resistive and inductive heating, and radiant
`heat provided by lamps and other sources of photons.
`
`[0046] The protruding baffle 240 as Well as the con?gu
`ration of the magnets and the process gas jets from the
`
`noZZle, and the gas species eroded from the solid source,
`provide for a high density plasma adjacent to the surface of
`the semiconductor Wafer. This con?guration greatly
`increases the range of densities that can be achieved Within
`the reactor chamber 222. The exact density required can be
`selected from the greater range of densities by controlling
`the poWer provided to the peripheral electrode 226 by the
`poWer source 230. The poWer source can be turned doWn if
`there is a desire to reduce the erosion rate of gas species from
`the solid source, and to reduce the density of the plasma.
`Alternatively, the poWer source may be turned up in order to
`increase the density of the plasma in the reactor chamber
`222.
`
`[0047] By Way of example only, if a polysilicon layer is
`being etched, the poWer provided by high frequency poWer
`source 230 Would be turned doWn as a less dense plasma and
`a higher erosion or generation rate is required from the solid
`source 250. Alternatively, if a silicide is being etched, the
`poWer Would be turned up as a denser plasma and a loWer
`erosion or generation rate Would be desired from the solid
`source. Further, the loWer frequency poWer source can also
`be adjusted to affect the results of the etching process in the
`above invention.
`
`[0048] The above range of operation is not possible With
`prior devices. It is to be understood that one or more of the
`above features can be used to enlarge the plasma density
`range and thus improve the etch process and fall Within the
`spirit and scope of the invention.
`
`[0049] An alternative embodiment of the reactor 220 is
`shoWn in FIG. 3. Similar components are numbered With
`similar numbers as discussed hereinabove. In FIG. 3, the
`noZZle 236 has been modi?ed in order to improve the
`uniformity of the mixture of the gaseous species in reactor
`chamber 222. As can be seen in FIG. 3, the noZZle 236
`includes a manifold 270 Which can channel the process
`gases in a number of directions. From manifold 270 there are
`horiZontal ports 272, 274 Which direct jets of the process
`gases horiZontally and parallel to the upper electrode 224.
`Port 276 directs jets of the gas vertically doWnWard directly
`onto the Wafer 248. Ports 278 and 280 channel jets of the
`process gases in a direction skeWed to the horiZontal, and
`principally toWard the periphery of the Wafer 248 in order to
`assure a uniform distribution of process gases and/or a good
`mixture of the gas species sputtered or otherWise eroded
`from the solid source 250 and the jets of process gases. In
`this embodiment, it is also the combination of the ports of
`the manifold 270 and the protruding baffle 240 Which
`ensures that a good mixture of (1) the gas species sputtered
`or eroded from the solid source 250, and (2) the process
`gases from the ports of the noZZle 236, are presented to the
`surface of the semiconductor Wafer 248.
`
`[0050] In this alternative embodiment, if desired, a second
`loW frequency poWer supply 231 can be communicated With
`the peripheral electrode 226. This poWer supply Would
`preferably have a frequency of 450 KHZ. This poWer supply
`Would be in all aspects similar to poWer supply 232. The
`high frequency poWer supply 230 Would control the plasma
`density While the loW frequency poWer supply 231 Would
`control the erosion rate of gaseous species from the solid
`source. This Would be an alternative to having the high
`frequency poWer supply control both the density of the
`plasma and the rate of erosion in the solid source.
`
`EXHIBIT 2004
`
`

`
`US 2001/0003676 A1
`
`Jun. 14, 2001
`
`[0051] Etching in prior art devices is usually performed in
`the 300 to 500 millitorr range, Which range is one to tWo
`orders of magnitude higher than the loW pressures contem
`plated by the reactor of the present invention. For etching of
`submicron features required by state-of-the-art semiconduc
`tor devices, loW pressure operations are desirable. HoWever,
`at loW pressures, it is more difficult to maintain a high
`density plasma.
`[0052] For the embodiments of FIGS. 2 and 3, the present
`embodiment contemplates a magnetic ?eld Which contains
`the plasma at a loW pressure (3-5 millitorrs), With a high
`plasma density (1011 cm3 at the Wafer), and With loW ion
`energy (less than 15 to 30 electron volts). Magnetic con
`tainment is not required for an inductively coupled reactor or
`for that matter for a capacitively coupled reactor. For such
`inductively coupled reactions, magnetic coupling generally
`enhances plasma uniformity, but is not needed to enhance
`plasma density. Generally, loW pressure operation Would be
`at about 150 millitorr or about 100 millitorr or less and
`preferably about 20 millitorr or about 10 millitorr or less.
`For submicron (sub 0.5 microns) devices, the plasma source
`must operate at a loW pressure With a high density of
`activated gases at the Wafer and a loW ion energy in order to
`deliver superior etching results. A loW pressure plasma
`improves the overall quality of the etch by minimiZing the
`undercutting of the Wafer features as Well as the effect of
`microloading, both of Which can adversely affect overall
`yield. LoW pressure, hoWever, requires a high density
`plasma at the Wafer to increase the number of plasma
`particles reacting With a ?lm on the semiconductor Wafer
`being etched in order to maintain a fast etch rate. A fast etch
`rate is one factor leading to a higher average throughput.
`Further, loW ion energy leads to improved etch selectivity
`and minimiZes Wafer damage. Both of Which improve over
`all yield.
`
`[0053] The reactor 220 of the present invention can be
`used to etch a variety of different substrates or ?lms Which
`require different etch chemistry or recipe. Generally, this
`chemistry includes tWo or more of the folloWing gases:
`halogen gases, halogen containing gases, noble gases, and
`diatomic gases.
`
`Tri-Electrode Reactors of FIGS. 6 and 7
`
`[0054] Referring to the ?gures and in particular to FIG. 6,
`a side cross-sectional vieW of an embodiment of the plasma
`etch reactor 620 of the invention is depicted. This reactor
`620 enhances and improves upon the reactor depicted and
`described in US. Pat. No. 4,464,223, entitled PLASMA
`REACTOR APPARATUS AND METHOD, as US. Pat. No.
`4,579,618, entitled PLASMA REACTOR APPARATUS
`Which patents are incorporated herein by reference.
`
`[0055] Reactor 620 includes a reactor chamber 622 Which
`is bounded by a grounded upper electrode 624, a side
`peripheral electrode 626, and a bottom electrode 628. The
`side peripheral electrode 626 is grounded or has a ?oating
`potential and in operation can be charged up by the plasma.
`In a preferred embodiment, the bottom electrode 628 is
`connected to a poWer supply 630 Which provides poWer to
`the bottom electrode 626 preferably at 13.56 MHZ (or
`multiples thereof) at a poWer level of preferably 900 Watts
`and at a voltage of preferably 1,200 volts. The high fre
`quency poWer supply can operate from 10 Watts up to 2000
`
`Watts in a preferred embodiment. It is to be understood that
`this is a high frequency poWer supply (preferably in the radio
`frequency range) and that the frequency preferably can
`range from 2 MHZ to 40 MHZ and upWards to about 900
`MHZ. The poWer can also preferably be supplied in the range
`of 100 Watts to 3,000 Watts With a voltage of betWeen 200
`volts to 5,000 volts.
`
`[0056] A second poWer supply 632 is additionally con
`nected to the bottom electrode 628. The second poWer
`supply 632 is preferably operated at 450 KHZ With the poWer
`being preferably supplied at 100 Watts, and at a voltage of
`300 volts. This is the loW frequency poWer