United States Patent 1191
`Matsumura et al.
`
`[54] METHOD FOR HEAT-PROCESSING
`SEMICONDUCTOR DEVICE AND
`APPARATUS FOR THE SAME
`
`[75] Inventors: Kimiharu Matsumura, Kumamoto;
`Hiroyuki Sakai, Nishigoshi; Masaaki
`Murakami, Kumamoto; Tetsuya Oda,
`Tamana; Chizo Yamaguchi, Sencho,
`311 ofJapan
`
`_
`_
`_
`[73] Assignees: Tokyo Electron Limited, Tokyo;
`-
`Tokyo Electron Kyushu Limited,
`Kumamoto, both of Japan
`[21] Appl. No.: 538,710
`.
`Jun‘ 15’ 1990
`[22] Filed:
`[30]
`Foreign Application Priority Data
`Jun. 16,1989 [JP]
`Japan ................................ .. 1454119
`Oct. 24, 1989 [JP]
`Japan ................................ .. 1~276564
`[51] Int. Cl.5 ............................................. .. HOSB 3/68
`[52] U.S. C1. .................................. .. 364/557; 219/457;
`219/464
`[58] Field of Search ..................... .. 364/557, 505, 477;
`219/405, 411, 388, 390, 457, 464, 465
`_
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,481,406 11/1984 Muka ..................... .. 219/405 X
`4,504.730 3/1985 Shimizu
`219/405 X
`4,688,180 8/1987 Motomiya .
`364/557 X
`4,690,569 9/1987 Veitch ........................... .. 364/557 X
`
`lllllllllllllllllIlllllllllIlillllllllllllllllllllllllllllllllliillllllllll
`US005151871A
`[11] Patent Number:
`5,151,871
`[45] Date of Patent:
`Sep. 29, 1992
`
`4.794217 12/1988 Quan et a]. ................. .. 219/1067 x
`4.881.591 11/1989 Rignall ...................... .. 364/557X
`4,958,061 9/1990 Wakabayashi et a1.
`.... .. 219/411
`4,982,347 1/1991 Rackerby et a1.
`364/557
`5,001,327 3/1991 Hirasawa et a1. ................. .. 219/390
`
`FOREIGN PATENT DOCUMENTS
`58-21332 2/1983 Japan .
`61-12030 1/1986 Japan .
`61-23321 1/1986 Japan .
`61_67224 4/1936 Japan I
`61-201426 9/1986 Japan .
`61-235835 10/1986 Japan .
`6 -
`1834 12
`86 J
`.
`1 27
`./ ‘9
`apa“
`Primary Examiner—Joseph L. Dixon
`Attorney, Agenz, or Firm-Oblon, Spivak, McClelland,
`Meier & Neustadt
`ABSTRACT
`[57]
`CPU stores information Showing a timbtemperature
`relationship and applicable for either heating a semicon
`duetor wafer to a hold temperature for a predetermined
`period of time or cooling the wafer from the hold tem
`perature over a predetermined period of time, or for
`both, read the information. A conductive thin ?lm heats
`the wafer in accordance with the information. A sensor
`detects the temperature of the wafer. A control system
`controls either the heating of the wafer or the cooling
`thereof, or both, in accordance with the detected tem
`perature signal and the information.
`
`12 Claims, 8 Drawing Sheets
`
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`Sep. 29, 1992
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`Sep.29,1992
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`Sep. 29, 1992
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`U.S. Patent
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`Sep. 29, 1992
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`Sheet 5 of 3
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`5,151,871
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`US. Patent
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`Sep. 29, 1992
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`Sheet 6 of 8
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`5,151,871
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`FIG. 7
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`LAM Exh 1003-pg 7
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`US. Patent
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`Sep. 29, 1992
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`Sheet 7 of 8
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`5,151,871
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`US. Patent
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`Sep. 29, 1992
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`Sheet 8 of 8
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`5,151,871
`
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`

`
`1
`
`METHOD FOR HEAT-PROCESSING
`SEMICONDUCTOR DEVICE AND APPARATUS
`FOR THE SAME
`
`15
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`25
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`35
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`20
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`5,151,871
`2
`the heating plate. A thick heating element is embedded
`in this conventional heating plate, the plate has a great
`thickness of 30 to 50 mm and its heat capacity is large
`accordingly. This causes the‘ conventional heating plate
`not to quickly raise and lower the temperature of the
`wafer-stage in the baking unit 5. Particularly, quick
`cooling is theoretically difficult because the heating
`plate has a limitation in its cooling speed.
`As apparent from the thermal history curve shown in
`FIG. 2, the temperature of the wafer-stage can be con
`trolled only when it is kept at a baking temperature T1
`but it cannot be controlled while it is being raised and
`cooled. The thermal history curve covering the whole
`of baking temperatures cannot be therefore guaranteed
`as desired. In addition, the heat capacity of the heating
`plate is large in this case. The heating and cooling re
`sponse of the heating plate is thus made slow and those
`times D4 and D7 which are needed to raise and lower
`the temperature of the wafer-stage become long, re
`spectively.
`'
`As the thermal history curve in FIG. 3 indicates, the
`baking unit heats the semiconductor wafer stepwise in
`some cases, thereby to enhance the thermal durability of
`the resist ?lm formed on the wafer by cross linking
`polymerization. The baking unit is controlled such that
`the temperature of the wafer-stage remains at baking
`temperature T; for a predetermined time and then at
`baking temperature T3 for a predetermined time. How
`ever, neither the time D5 for heating the stage from an
`initial value to temperature T; nor the time D6 for heat
`ing it from temperature T; to temperature T3 is con
`trolled at all. These periods D5 and D6 are relatively
`long, and the sum of them is thus considerably long,
`inevitably lengthening the total baking time very much.
`Consequently, the throughput of the wafers is reduced.
`To prevent reduction of throughput, it is necessary to
`use a number of heating plates.
`As the density of semiconductor devices is made
`higher and higher, resist patterns of these devices have
`become ?ner and ?ner. The thermal history curve (or
`temperature changing pattern) of the wafer-stage at the
`stage-heating and -cooling times which was neglected
`in the case of the conventional system comes to add
`large in?uence to the resolution and light-sensitivity of
`the photoresist. 'This makes it seriously necessary to
`develop a system capable of controlling the temperature
`of the wafer-stage to obtain a thermal history curve as
`desired at the stage-heating and -cooling times.
`Particularly in the case of the conventional system,
`the temperature of the wafer-stage was not a controlled
`predetermined condition at the stage-heating and -cool
`ing times. Even when the semiconductor wafers of the
`same kinds were baking-processed, therefore, the prop
`erty of one wafer became different from those of the
`other ones, thereby damaging the reliability of the semi
`conductor wafers thus produced.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to method and appara
`tus for heat-processing semiconductor wafer or LCD
`and, more particularly, it relates to method and appara
`tus capable of controlling temperatures of these semi
`conductor wafers or LCD when these are heated up
`and cooled down.
`2. Description of the Related Art
`Various kinds of heating processes are included in the
`course of manufacturing various kinds of devices in
`which semiconductors are included. Semiconductor
`wafers are heated at the adhesion and baking processes
`in the course of photo-lithographing semiconductor
`integrated circuits, for example. More speci?cally, the
`semiconductor wafers are heated and their surfaces are
`treated with HMDS vapor at the adhesion process so as
`to promote the photoresist bonding performance on
`wafer surface. After the semiconductor wafer being
`coated with photoresist, which is baked at a certain
`temperature to remove solvent in the photoresist and to
`enhance the polymetric cross linking of photoresist.
`As shown in FIG. 1, various kinds of processing units
`1 to 6 are housed in a resist-processing system 10 to
`process the semiconductor wafers one by one. A sender
`1 is located on the inlet side of the system 10 and a
`receiver 6 on the outlet side thereof. The semiconductor
`wafer is transferred one by one from the sender 1 to an
`adhesion unit 2, and adhesion-processed by the adhesion
`unit 2. After being heated by the adhesion unit 2, the
`semiconductor wafers are forcedly cooled by a cooling
`unit 3 and coated with photoresist in a coating unit 4.
`After being coated with photoresist, they are baked by
`a baking unit 5 and transfer to the receiver 6. They are
`carried from the receiver 6 to an exposure unit (not
`shown) through an interface (not shown) and exposed
`by the exposure unit located outside the system 10.
`It is needed that the semiconductor wafers are
`forcedly cooled at a high speed by the cooling unit 3.
`This is because temperatures of the wafers must be
`accurately controlled and their surfaces must be cooled
`to have a certain temperature'so as to uniformly coat
`their surfaces with resist at a next process.
`In other words, the temperature of the wafer which
`has been processed by the conventional adhesion unit 2
`depends upon its temperature obtained when the adhe
`sion process is finished relative to it on a wafer-stage in
`the unit 2. This causes its temperature to variously
`changes and not to be kept certain. After it is adhesion
`processed by the conventional unit 2, therefore, it must
`be cooling-processed by the unit 3. The whole of the
`conventional resist-processing system thus becomes
`large in size. In addition, a forcedly-cooling time is
`added to the wafer-carrying time in the cooling unit 3 in
`the case of the conventional system, thereby reducing
`the throughput of the wafers. Further, when the time
`during which the wafer is processed through the whole
`of the system is long, it causes more particles of dust and
`the like to adhere to the semiconductor wafer. This is
`not preferable from the viewpoint of quality control.
`In the case of the conventional baking unit 5, the
`semiconductor wafer is mounted on a heating plate
`made of stainless steel or aluminum alloy and heated by
`
`50
`
`55
`
`SUMMARY OF THE INVENTION
`The object of the present invention is therefore to
`provide a simpler method of heat-processing semicon
`ductor devices whereby temperatures of the semicon~
`ductor devices can be controlled at devices-heating and
`-cooling times so as to accurately control their thermal
`history curve.
`According to an aspect of the present invention, there
`can be provided a method for heat-processing object
`comprising the steps of:
`
`65
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`5,151,871
`3
`storing. as a predetermined recipe, information show
`ing a time-temperature relationship and applicable
`for either heating the object to a predetermined
`temperature for a predetermined period of time or
`cooling the object from a predetermined tempera
`ture over a predetermined period of time, or for
`both;
`reading the information and applying the informa
`tiOn;
`heating the object by means of a conductive thin ?lm
`in accordance with the information;
`detecting the temperature of the object directly or
`indirectly; and
`controlling either the heating of the object or the
`cooling thereof, or both, in accordance with the
`detected temperature and the information.
`According to another aspect of the present invention,
`there can be provided an apparatus for heat-processing
`object comprising, a stage having a conductive thin ?lm
`for heating the object; a detecting means for detecting
`temperatures of the object; a storing means for previ
`ously storing as a predetermined recipe, information
`showing a time-temperature relationship and applicable
`for either heating the object to a predetermined temper
`ature for a predetermined period of time or cooling the
`object from a predetermined temperature over a prede
`termined period of time, or for both, and a control
`means for reading the information in the storing means,
`and for receiving signal relating to the temperatures of
`the object detected by the detecting means, and for
`30
`controlling a period of heat up and cool down respon
`sive to the information and signal while heating the
`object by said conductive thin ?lm.
`It is preferable that the apparatus further includes a
`means for forcedly cooling the object.
`It is also preferable that any of those heating plates
`which are formed according to the heating theory of
`the conductive thin film is used as the heating element.
`This is because these heating plates are smaller in heat
`capacity and more excellent in response.
`It is also preferable that any of those heat-generating
`resistance materials which are more excellent in re
`sponse and thermal durability is used as the conductive
`thin ?lm. These heat-generating resistance materials
`include metal, alloy, carbon material, polymer compos
`ite and composite ceramic (which is conductive).
`The single metal of which the conductive thin ?lm is
`chromium, nickel, platinum, tantalum, tungsten, tin,
`iron, lead, beryllium, antimony, indium, cobalt, stron
`tium, rhodium, palladium, magnesium, molybdenum,
`lithium or rubidium. Nichrome, stainless steel, bronze,
`brass, alumel and chrome] are mentioned as the alloy of
`which the conductive thin ?lm is made. Carbon black,
`graphite and the like are mentioned as the carbon mate
`rial of which the conductive thin ?lm is made. The
`55
`polymer composite for the conductive thin ?lm in
`cludes polymer graft carbon and the like. Moybdenum
`silicide is used as the composite ceramic of which the
`conductive thin ?lm is made. The composite ceramic
`includes cermet also.
`'
`It is preferable that the conductive thin ?lm is made
`of any of those materials whose electric resistances
`become smaller as temperature becomes higher or
`lower. This is because a large amount of current can
`concentrate on those areas in the conductive thin ?lm
`where temperature is relatively lower so as to increase
`the speed of raising the temperature of these areas in the
`conductive thin ?lm and to enable the ?lm to have a
`
`25
`
`35
`
`45
`
`50
`
`65
`
`4
`uniform temperature in the whole of it when the ?lm is
`heated.
`Additional objects and advantages of the invention
`will be set forth in the description which follows, and in
`part will be obvious from the description, or may be
`learned by practice of the invention. The objects and
`advantages of the invention may be realized and ob
`tained by means of the instrumentalities and combina
`tions particularly pointed out in the appended claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The accompanying drawings, which are incorpo
`rated in and constitute a part of the speci?cation, illus
`trate presently preferred embodiments of the invention
`and, together with the general description given above
`and the detailed description of the preferred embodi
`ments given below, serve to explain the principles of the
`invention.
`'
`FIG. 1 is a block diagram showing a layout of the
`resist processing system in which a conventional heat
`processing method is employed;
`FIGS. 2 and 3 are graphs showing heat curves of a
`wafer-stage which is heated and cooled according to a
`conventional method;
`FIG. 4 is a block diagram showing a layout of a resist
`processing system in which a heat-processing method is
`employed according to a present invention;
`‘FIG. 5A is a diagram showing a circuit of an adhe
`sion unit which is included in a resist processing system;
`FIG. 5B is a block diagram showing a circuit of a
`control system which is included in an adhesion unit;
`FIGS. 6A to 6C are charts intended to explain PWM
`(Pulse Wide Modulation) signal SM and cooling control
`signal SC sent from a control system to a SSR (Solid
`Stage Relay);
`FIG. 7 is a chart intended to explain the temperature
`change (include ripple of temperature) of a heating
`plate at a time when its temperature is being raised,
`lowered and kept certain;
`FIG. 8 is a diagram showing one of a recipe relating
`to a thermal history curve of a wafer-stage;
`FIG. 9 is a diagram showing another of a recipe relat
`ing to a thermal history curve of a wafer-stage;
`FIG. 10 shows longitudinal sectional view of another
`heating plate;
`FIG. 11 shows longitudinal sectional view of a heat
`processing system of a batch type; and
`FIG. 12 shows transversal sectional view of a heat
`processing system of a batch type.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Some embodiments of the present invention will be
`described in detail with reference to the accompanying
`drawings.
`As shown in FIG. 4, various kinds of processing units
`41 to 45 are housed in a resist processing system 40 and
`semiconductor wafers W are continuously processed by
`these processing units. A sender 41 is located on the
`inlet side of the system 40 while-a receiver 45 on the
`outlet side of the system 40. A cassette carrying robot
`(not shown) can run on a clean track which extends to
`a cassette stage located adjacent to the sender 41. The
`sender 41 serves to pick up the semiconductor wafers W
`one by one and transfer them to the adhesion unit 42
`where they are heated and coated with HMDS.
`The coating unit 43 is located next to the adhesion
`unit 42 and it serves to form resist ?lm of a certain
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`5,151,871
`5
`thickness on the surface of each of the semiconductor
`wafers W. The baking unit 44 is located next to the
`coating unit 43, serving to bake each of the semiconduc
`tor wafers W at a certain temperature.
`The receiver 45 is located next to the baking unit 44
`and it serves to receive the semiconductor wafers W
`which have been resist-processed.
`An exposure unit (not shown) is located exterior of
`the resist processing system 40. An interface (not
`shown) is arranged between the receiver 45 and the
`exposure unit and the semiconductor wafers W are
`transferred to the exposure unit by the interface.
`The adhesion unit 42 will be described referring to
`FIG. 5A. A case where the adhesion unit 42 includes a
`wafer-stage 12 which can serve to heat and cool the
`semiconductor wafers W will be described and this
`wafer-stage ‘12 may also be used in the baking unit 44.
`The stage 12 on which the semiconductor wafer W is
`to be mounted is arranged in a chamber of the adhesion
`unit 42. An HMDS supply tube 33 extends passing
`through the top of the chamber 11. A diffusion plate 34
`is attached to the front end of the supply tube 33, oppos
`ing to the wafer W on the table 12. The underportion of
`the diffusion plate 34 is provided with a plurality of
`apertures which are communicated with the inside of a
`bottle 31 through the supply tube 33. A bubbler 32 is
`immersed in HMDS solution in the bottle 31 and con'
`nected to a nitrogen gassupply source (not shown)
`through a pipe 32a.
`A discharge pipe 35 extends from the bottom of the
`chamber 11 to a vacuum pump (not shown).
`The semiconductor wafer W which has a size of 8
`inches is mounted on the stage 12. The diffusion plate 34
`is shaped to cover the whole area of the stage 12. An
`upper plate 13 of the stage 12 is made of alumina. It may
`35
`be instead made of ceramics if they have characters of
`insulation and thermal conductivity. The upper plate 13
`has longitudinal side and transversal side each of which
`is in a range of 160 to 180 mm, and its thickness is in a
`range of l to 20 mm, more preferably in a range of 5 to
`10 mm.
`7
`Conductive thin ?lm 14 is formed on the whole areas
`of the underside of the upper plate 13 by depositing
`metal chromium alone on the underside of the upper
`plate 13. The thickness of this conductive thin ?lm 14 is
`in a range of 0.1 to 100 pm, more preferably in a range
`of 0.5 to 2 pm.
`Pins (not shown) are attached to the stage 12 to pick
`up the semiconductor wafer W from the upper plate 13.
`The semiconductor wafer W is unloaded from the stage
`12 by the pins.
`Electrodes 15 and 16 each made of copper and
`shaped like a stripe are attached to the under'side of
`peripheral portion of the conductive thin ?lm 14. These
`electrodes 15 and 16 are connected to a power supply
`circuit 19. The power supply circuit 19 includes a com
`mercial AC power supply 17 and an SSR (solid state
`relay) 18. The SSR 18 serves as a switching element. A
`control system 20 includes a CPU 201 and a PID con
`troller 203. The control system 20 serves to apply sig
`nals SM and SC to the SSR l8 and a cooling system 23
`responsive to inputted recipes and temperature detect
`ing signal.
`'
`As shown in FIG. 5B, the PID controller 203 in the
`control system 20 is connected to the SSR 18. PWM
`65
`signal SM is inputted from the PID controller 203 to the
`SSR 18. The PID controller 203 is also connected to a
`cooling system 23 to apply signal SC to the latter. A
`
`6
`thermometer 24 which has a sensor 25 is connected to a
`digital adder 202 of the control system 20. The thermal
`sensor 25 is attached to an appropriate position on the
`underside of the conductive thin ?lm 14. A keyboard
`20a is connected to the input section of the CPU 201.
`Numeral values for creating desired adhesion process
`ing condition (or recipe including heating and other
`conditions) are inputted to the CPU 201 by the key
`board 20a. Pulse signals are applied from a pulse genera
`tor 204 to each of the CPU 201, digital adder 202 and
`PID controller 203 at a timing of one second. A address
`counter 205 is arranged between the CPU 201 and the
`pulse generator 204.
`p
`The conductive thin ?lm 14 is coated together with
`the electrodes 15, 16 and thermal sensor 25 by protec
`tion ?lm 21, which is made of tetrafluoroethylene (Te
`flon ®) and serves to protect the conductive thin ?lm
`14 and the like.
`A cooling jacket 22 is arranged under the stage 12 to
`exchange heat with the conductive thin ?lm 14 through
`the protection ?lm 21. An inner passage 22a is formed in
`the jacket 22, communicating with a coolant supply
`source in the cooling system 23, which includes a com
`pressor and an evaporator to circulate coolant through
`the jacket 22. The output section of the control system
`20 is connected to the input section of the cooling sys
`tem 23. The control system 20 serves to apply control
`signal SC to the cooling system 23 responsive to the
`recipe and temperature detecting signal so as to control
`the amount of coolant supplied from the cooling system
`23 to the jacket 22.
`A case where the surface of the semiconductor wafer
`W is adhesion-processed will be described with refer—
`ence to FIGS. 6A through 6C and 7.
`(I) A predetermined recipe is inputted to the CPU
`201 by the keyboard 20a. The recipe is a command table
`including temperature/ time point data in which temper
`ature raising and lowering‘speed is in a range of 50° to
`200° C. per minute. Heating temperature is in a range of
`100° to 150° C. and hold time is in a range of 0.1 to 1
`minute. The CPU 201 interpolates points between any
`two adjacent point data of the recipe, thereby obtaining
`a master curve (thermal history curve).
`(II) The semiconductor wafer W is carried from the
`sender 41 to the adhesion unit 42 by a handling device
`(not shown) and placed or mounted on the stage 12. The
`inlet of the chamber 11 through which the wafer W is
`carried is closed and gas in the chamber 11 is then dis
`charged through the discharge pipe 35.
`(III) PWM signal SM is applied from the PID con
`troller 203 to the SSR 18. A predetermined amount of
`current is thus added from a power supply 17 of the
`circuit 19 to the conductive thin ?lm 14 through the
`electrodes 15 and 16 to heat the conductive thin ?lm 14.
`The semiconductor wafer W on the upper plate 13 is
`heated by the conductive thin ?lm 14. When PWM
`signal SM from the PID controller 203 is changed this
`time, the amount of current supplied to the conductive
`thin ?lm 14 is switching-controlled to raise the tempera
`ture of the wafer W at a desired heat curve.
`PWM signal SM and cooling control signal SC will
`be described referring to FIGS. 6A through 6C.
`As shown in FIG. 6A, when pulse widths W1 and W;
`of each of signals SM and SC are QT (T is one cycle) or
`their duty cycles are 50%, as shown by a line L] in FIG.
`7, the temperature of the upper plate 13 is substantially
`constant. The one cycle T is equal to a second, which is
`
`45
`
`50
`
`60
`
`LAM Exh 1003-pg 12
`
`

`
`25
`
`30
`
`5,151,871
`7
`8
`determined by pulse signal applied from the pulse gen
`Using the baking unit 44 provided with this wafer
`erator 204.
`stage 120, the process of baking the wafer W is carried
`As shown in FIG. 6B, when the pulse width W1 of
`out as follows:
`signal SM in one cycle T is larger than %T or its duty
`(I) A recipe shown in FIG. 8 is inputted to the CPU
`201 by the keyboard 2011. Points P0 to P8 are set in the
`cycle exceeds 50%, as shown by a line L2 in FIG. 7, the
`temperature of the upper plate 13 is raised.
`recipe so as to surely reproduce thermal history curve. ,
`Information relating to temperatures and times at these
`As shown in FIG. 6C, when the pulse width W1 of
`points P0 to P8 is inputted as a command temperature
`signal SM in one cycle T is smaller than %T or its duty
`table to the CPU 201. In the case of this recipe, heating
`cycle is smaller than 50%, as shown by a line L3 in FIG.
`and cooling speeds are 100° C. per minute, temperature
`7, the temperature of the upper plate 13 is lowered.
`to be held is 120° C. and the time during which the
`When the pulse width of signal SM in one cycle T is
`temperature is held is 60 seconds.
`variously changed in this manner, the extent to which
`The CPU 201 interpolates points between any two
`the upper plate 13 is heated by the conductive thin ?lm
`adjacent point data of the recipe thereby a master curve.
`14 can be freely changed to raise the temperature of the
`(II) The semiconductor wafer W which has been
`wafer W at a desired heat curve. The other, when the
`coated by resist is carried from the coating unit 43 to the
`pulse width of signal SC in one cycle T is variously
`baking unit 44 and mounted on the stage 120.
`changed in this manner, the upper plate 13 is cooled by
`(III) PWM signal SM is applied from the PID con
`the cooling system 23.
`troller 203 to the SSR 18 to energize the conductive
`(IV) The temperature of the thin ?lm 14 is detected
`thin ?lm 14. The conductive thin ?lm 14 is thus heated
`by the sensor 25 of the thermometer 24 and this detec
`to heat the semiconductor wafer W on the upper plate
`tion signal is inputted to the digital adder 202. The
`13a. PWM signal SM is changed this time and the
`temperature measured is determined on the basis of the
`amount of current supplied to the conductive thin ?lm
`detection signal in the digital adder 202 and the amount
`14 is thus switching-controlled.
`of current supplied to the conductive thin ?lm 14 is
`(IV) The temperature of the thin ?lm 14 is detected
`feedback-controlled responsive to the temperature mea
`by the sensor 25 of the thermometer 24 and this detec
`sured. When the measured temperature which is deter
`tion signal is inputted to the digital adder 202. Tempera
`mined on the basis of the detection signal coincides with
`ture measured is determined on the basis of the detec
`a predetermined temperature to be held, the duty cycle
`tion signal in the digital adder 202. The amount of cur
`of signal SM is made equal to 50% to hold the tempera
`rent supplied to the conductive thin ?lm 14 is feedback
`ture of the upper plate 13 in a range of 100° to 150° C.
`controlled responsive to this temperature measured. It
`for a time period of 0.5 to 1 minute.
`is arranged by this feedback control in the course of
`(V) I-IMDS solution is sprayed onto the semiconduc
`heating the wafer W that the thermal history curve of
`tor wafer W which is held at the predetermined temper
`the wafer W passes through the points P1 and P2 and
`ature, thereby causing I'IMDS to adhere to the surface
`reaches the point P3.
`of the wafer W.
`(V) When the thermal hysteresis of the wafer W
`(VI) After the wafer W is held at the predetermined
`reaches the point P3, the duty cycle of signal SM ap
`temperature, the duty cycle of signal SM is changed
`plied from the PID controller 203 is made equal to 50%
`smaller than 50% to lower the temperature of the upper
`and the temperature of the wafer W is held certain for
`plate 13. Signal SC whose duty cycle is larger than 50%
`60 minutes. The thermal history curve of the wafer W is
`is applied from the PID controller 203 to the cooling
`checked at the point P4 in the course of holding the
`system 23 at the same time to supply coolant to the’
`temperature certain. When the temperature of the wafer
`jacket 22 so as to forcedly cool the upper plate 13.
`W reaches the point PS, the duty cycle of signal SM
`Signals SM and SC are determined this time by the PID
`applied from the PID controller 203 is changed smaller
`controller 203 responsive to the temperature of the thin
`than 50% to lower the temperature of the wafer W on
`45
`?lm 14 detected by the sensor 25.
`the upper plate 13.
`(VII) After the semiconductor wafer A is cooled, the
`(VI) As the result, the resist which has been coated
`pin is projected to pick up the wafer W from the upper
`on the semiconductor wafer W becomes such a resist
`plate 13 and carry it out of the chamber.
`?lm as has predetermined characteristics. After this
`According to the above-described embodiment, heat
`baking process, the pin is projected to pick up the semi
`curve of temperature-raising and lowering periods can
`conductor wafer W from the stage 120 and carry it from
`be controlled, as a result of the throughput of wafers
`the baking unit 44 to the receiver 45.
`increase.
`A case where the semiconductor wafer W is baked
`A case where the semiconductor wafer W is baking
`according to another recipe will be described. Descrip
`processed after it is coated by resist will be described
`tion will be omitted if it repeats the above-made one.
`referring to FIGS. 8 through 10. That portion of de
`(I) A recipe shown in FIG. 9 is inputted into the PID
`scription relating to the baking process which overlaps
`controller 203 by the keyboard 200. Points P10 to P19
`the above description relating to the adhesion process
`are set in the recipe so as to surely reproduce the ther
`will be omitted.
`mal history curve of the wafer W. Information relating
`FIG. 10 shows a wafer-stage 12a employed by the
`to temperatures and times at these points P10 to P19 is
`baking unit 44. A ceramic thin ?lm 13b is interposed
`inputted as 'a command temperature table to the CPU
`between the conductive thin ?lm l4 and an upper plate
`201. In the case of this recipe, the heating speed at a ?rst
`130 in the case of this wafer-mounted table 120. The
`step is 70° C. per minute, the temperature to be held at
`ceramic thin ?lm 13b is formed to flame-spraying ce
`a ?rst step is 90° C., the heating speed at a second step
`ramic powder onto the surface of the upper plate 130
`is 150° C. per minute, the temperature to be held at a
`which is made of aluminum alloy. The upper plate 130
`second step is 140° C. and the cooling speed is 2° C. The
`is insulated from the conductive thin plate 14 by the
`time during which the temperature is held at the ?rst
`ceramic thin ?lm 13b.
`and second steps, respectively, is 30 seconds.
`
`60
`
`35
`
`65
`
`LAM Exh 1003-pg 13
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`

`
`10
`which are small in heat capacity and excellent in tem
`perature control can be employed.
`Still further, the present invention has been applied to
`the adhesion a