SMART EXHIBIT - 1017
`
`SMART EXHIBIT - 1017
`
`

`
`SECOND AMENDED INFRINGEMENT CHART
`
`Patent:
`Patent Claim(s)
`
`U.S. Patent No. 6,243,315
`1
`
`Company:
`
`SMART MODULAR TECHNOLOGIES INC. (“SMART
`MODULAR”)
`
`SMART MODULAR PRODUCTS CONSIDERED
`
`1.
`
`2.
`
`3.
`
`All memory modules including the designation “DDR2" See Ex. 1 for a Declaration
`covering exhibits, and Ex. 2 for examples of DDR2 memory modules.
`All memory modules including the designation “DDR3" See Ex. 3 for examples of
`DDR3 memory modules.
`All memory modules including the designation “DDR4" See Ex. 4 for examples for
`DDR4 memory modules.
`
`PRELIMINARY DISCUSSION
`
`The Court Order dated June 29, 2015 accepted the Report and Recommendations from
`the Special Master Scott Woloson as to claim construction. This Second Amended Infringement
`Chart takes into account the claim construction adopted by the Court.
`
`No claim other than claim 1 has been asserted throughout this case. Hence, only claim 1
`will be considered herein.
`
`Smart Memory Modules DDR2, DDR3, and DDR4 do not directly infringe claim 1 of the
`‘315 Patent because these memory modules do not include certain claimed elements of claim 1;
`however, when a Smart Memory Module DDR2, DDR3, or DDR4 is installed in operating
`systems such as test equipment, computers, servers and the like, claim 1 of the ‘315 Patent is
`directly infringed because these operating systems provide the missing elements of claim 1.
`
`There are substantially no non-infringing uses of DDR2, DDR3, and DDR4 memory
`modules. Nor are these memory modules staples in commerce. Smart Modular tests the memory
`modules for compliance with the respective industry standards, JEDEC Specifications, and to
`collect data for marketing the memory modules. Hence, Smart Modular “adds” the missing
`claim elements for direct infringement. See Ex. 5 showing many documents from the Smart
`Modular webs sites stating that Smart Modular conducts tests on its Memory Modules to confirm
`actual performance operations.
`
`Page 1 of 7
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`SMART Exhibit - 1017 - Page 1
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`

`
`The respective designation of the memory products as “DDR2", “DDR3", and “DDR4"
`means that the respective products comply with the JEDEC STANDARDS: See Ex. 6, DDR2
`SDRAM SPECIFICATION (JESD79-2F) (hereinafter, “JESD79-2F”), under the heading,
`“NOTICES” stating “No claims to be in conformance with this standard may be made unless all
`requirements stated in the standard are met”. See Ex. 7, DDR3 SDRAM STANDARD (JESD79-
`3F)(hereinafter, “JESD79-3F”) and Ex. 8, DDR4 SDRAM STANDARD (JESD79-4-1)
`(hereinafter, “JESD79-4-1”) for the same statement under “NOTICES”.
`
`According to its web site (www.jed.org), JEDEC is a global leader in developing open
`standards for the microelectronics industry. Smart Modular is a member of JEDEC, and has a
`representative on the Subcommittee for Hybrid Modules. Hence, Smart Modular knows of the
`JEDEC Standards and its responsibility to comply with the standards for Smart Modular to
`include the designations of “DDR2", “DDR3", and “DDR4" in the designation of the Smart
`Modular memory modules.
`
`Thus, any additional company designations in addition to DDR2, DDR3, and DDR4 does
`not alter the obligation of Smart Modular to comply with the JEDEC standards because the
`JEDEC standard is directed to the use of terms “DDR2", “DDR3", and “DDR4".
`
`Page 2 of 7
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`SMART Exhibit - 1017 - Page 2
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`

`
`IT IS UNNECESSARY TO COMPARE A PATENT CLAIM TO A PRODUCT
`DIRECTLY TO PROVE PATENT INFRINGEMENT
`
`The DDR2, DDR3, and DDR4 memory modules without additional euipment do not
`infringe any of the patent claims of the ‘315 Patent because certain claim elements are missing
`from each of these memory modules. When any of these memory modules are tested, the testing
`environment adds subsystems to provide inputs and outputs such as in a computer. Hence, the
`testing of the memory modules adds the necessary subsystems to infringe claim 1.
`
`The JEDEC Standards for the DDR2, DDR3, and DDR4 memory modules, respectively,
`concentrate on the operation of the memory module, but do specify input and output terminals to
`receive and output information and commands for external subsystems. Hence, infringement
`occurs when Smart Modular carries out testing of memory modules by connecting subsystems to
`the input and output terminals.
`
`Previously, it has been the rule that to establish direct patent infringement, it is necessary
`to compare a product or process to a patent claim to show each and every element of the patent
`claim is present.
`
`This rule, however, no longer applies if there is an industry standard such as generated by
`JEDEC.
`
`The Federal Circuit has recently stated:
`
`We hold that a district court may rely on an industry standard in
`analyzing infringement. If a district court construes the claims and
`finds that the reach of the claims includes any device that practices
`a standard, then this can be sufficient for a finding of infringement.
`We agree that claims should be compared to the accused product to
`determine infringement. However, if an accused product operates
`in accordance with a standard, then comparing the claims to the
`standard is the same as comparing the claims to the accused
`product. Fujitsu Limited et al. v. Netgear Inc., 620 F. 3d 1312
`(Fed. Cir. 2010)
`
`Hence, to show direct patent infringement by Smart Modular, it is only necessary to
`compare the respective applicable JEDEC Standards for the DDR2, DDR3, and DDR4 memory
`products to claim 1 and take into account the equipment Smart Modular uses for its tests, data
`collection, and data measured for marketing purposes by connecting the equipment to input and
`output terminals of the respective memory modules. Showing compliance with the JEDEC
`Standards is essential and cannot be done with adding equipment to connect the DDR3.
`
`Page 3 of 7
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`SMART Exhibit - 1017 - Page 3
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`

`
`CLAIM CHART AND ASSOCIATED CONSTRUCTION
`
`U.S. Patent No. 6,243,315
`
`Claim 1. A memory system for use in a
`computer system, said memory system
`comprising:
`
`a plurality of volatile solid state memory
`devices that retain information when an
`electrical power source is applied to said
`memory devices within a predetermined
`voltage range and
`
`SMART MODULAR MEMORY
`MODULE DDR3
`
`The Court has determined that a “memory
`system” is “a system capable of retaining
`data”. The JESD79-3F (Ex. 7) identifies the
`DDR3 as having a memory array. See p. 18,
`Sec. 3.2, “The DDR3 SDRAM is a high-
`speed dynamic random-access memory ...”.
`In addition, p. 79 states, “The Self-Refresh
`command can be used to retain data in the
`DDR3 SDRAM, even if the rest of the system
`is powered down.
`Thus, the DDR3 memory module is within
`the scope of the preamble.
`
`The Court has determined that “memory
`device” means “integrated circuit or chip”;
`that “a plurality of volatile solid state memory
`devices” means “two or more memory
`devices in the memory system into which
`data may be written or from which data
`may be retrieved that retain information
`while a electrical power source, having a
`predetermined voltage range, is applied to
`the memory devices and when the voltage
`reaches a predetermined threshold outside
`of that range, the memory devices will no
`longer retain their current state of
`information”
`
`The JESD79-3F (Ex. 7) at p. 77 refers to the
`memory module as being a “chip”. See Sec.
`4.15 stating, “the chip enters a Refresh cycle”.
`Hence, the DDR3 is a chip.
`
`The JESD79-3F (Ex. 7) at p. 109, Sec. 6.1
`
`Page 4 of 7
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`SMART Exhibit - 1017 - Page 4
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`

`
`capable of being placed in a self refresh
`mode;
`
`The JESD793F (Ex. 7) at p. 109, Sec. 6.1
`states the absolute maximum DC Ratings. P.
`111, Sec. 7.1 shows the recommended DC
`Operating Conditions with a minimum and
`maximum for the DC voltages. Hence, the
`DDR3 requires a specific range of applied of
`voltage to retain data.
`
`The JESD793F (Ex. 7) at p. 18, Sec. 2.3
`states, “The DDR3 SDRAM is a high-speed
`dynamic random-access configured as an
`eight-bank DRAM.” The second paragraph
`describes how a bank can be selected. The
`Command Truth Table at p. 34, NOTE 3
`discusses that the selection of a bank. Hence,
`the DDR3 has eight memory units, a plurality
`of solid state memory devices.
`
`The JESD79-3F (Ex. 7) shows that the DDR3
`is capable of being refreshed p. 13, Sec. 2.10
`for CKE, (CKE0), (CKE1) “Self-Refresh
`operations (all banks idle)”; p. 17, Sec. 3.1 on
`the diagram; p. 31, Sec. 3.4.4.1 entitled
`“Partial Array Self-Refresh (PASR)”; p. 35,
`Sec. 4.2 shows an entry for “Self-Refresh”; p.
`46, Sec. 4.9.0.1 entitled, “Auto Self-Refresh”;
`and p. 79, Sec. 4.16 is entitled, “Self-Refresh
`Operation” with detailed information.
`
`Page 5 of 7
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`SMART Exhibit - 1017 - Page 5
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`

`
`a control device for selectively electrically
`isolating said memory devices from
`respective address lines and respective control
`lines so that when said memory devices are
`electrically isolated, any signals received on
`said respective address lines and respective
`control lines do not reach said memory
`devices; and
`
`The Court has determined that “control
`device” means “a device in the memory
`system that is interposed between the
`respective address lines and respective
`control lines that electrically isolates the
`memory devices”; that “selectively
`electrically isolating said memory devices
`from respective address lines and respective
`control lines’ means “inhibiting signals on
`the respective address and respective
`control lines from the memory devices such
`that signals on those lines do not arrive at
`the memory devices”; that “address lines”
`mean “lines that carry signals specifying a
`memory location to be accessed”; “control
`lines” mean “lines that carry control
`signals”; and “control signals” mean “signals
`that control the sequence of addressing
`and the memory mode”. It is noted that the
`term “control signals” does not appear in
`claim 1.
`
`During testing and evaluation of the DDR3, it
`is necessary for Smart Modular to connect
`subsystems to the DDR3 using the input and
`output terminals of the DDR3. Obviously,
`the use of the term “interposed” relates to the
`electrically operation of the control device,
`not a physical positioning.
`
`The JESD79-3F (Ex. 7) at p. 13, Sec. 2.10
`identifies address lines connected to inputs
`such as for symbols “BA0-BA2", “A0-A15",
`and “A10/AP/”. The JESD793F uses the
`terms “command signal”, and “command
`line” for the defined “control signal” and
`“control line”. At p. 14, Sec. 2.10, note the
`functions of input CS#, (CSO#), CCS1#),
`(CS2#), and CS3#; ODT, and (ODT0), and
`(ODT1). The command signals on the input
`terminals connect into the DDR3 on “control
`lines” to control the sequence and memory
`mode.
`
`Page 6 of 7
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`SMART Exhibit - 1017 - Page 6
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`

`
`JESD793C (Ex. 7), Sec. 4.17.1 states, “
`Power-down is synchronously entered when
`CKE is registered low (along with NOP or
`Deselect command). CKE is not allowed to
`go low while mode register set command,
`MPR operations, ZQCAL operations, DLL
`locking all read/write operations are in
`progress. P. 33, Sec. 4.1 shows a Command
`Truth Table and for Power Down, CKE is low
`which deactivates the internal clock signals
`and device input buffers and output drivers
`according to Sec. 2.10. The Truth Table at p.
`35 for Power-Down states in NOTE 15 that
`“X” means “don’t care” for the commands on
`input terminals RAS#, CAS#, WE#, and CS#.
`Note also Sec. 4.17.1, last paragraph states
`that input and output buffers are deactivated
`as well as a deactivation of command and
`address receivers after tCPDED has expired.
`
`For DDR3, see JEDEC, No 79-3F, Section
`4.17 describes entering Power-Down when
`there is no read or write operations. Note that
`all other signals are “Don’t Care”, thereby
`“electrically isolating” the memory device.
`The “Power Down” reduces electrical power
`consumption.
`
`a memory access enable control device
`coupled to said control device and to said
`control lines for determining when said
`memory system is not being accessed and for
`initiating a low power mode for said memory
`system wherein said control device
`electrically isolates said memory devices and
`places said memory devices in said self
`refresh mode, thereby reducing the amount of
`electrical energy being drawn from an
`electrical power supply for said computer
`system.
`
`Page 7 of 7
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`SMART Exhibit - 1017 - Page 7
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`

`
`CLAIM CHART AND ASSOCIATED CONSTRUCTION
`
`U.S. Patent No. 6,243,315
`
`Claim 1. A memory system for use in a
`computer system, said memory system
`comprising:
`
`a plurality of volatile solid state memory
`devices that retain information when an
`electrical power source is applied to said
`memory devices within a predetermined
`voltage range and
`
`SMART MODULAR MEMORY
`MODULE DDR4
`
`The Court has determined that a “memory
`system” is “a system capable of retaining
`data”. The JESD79-4-1 (Ex. 7) identifies the
`DDR4 as having a memory array in the
`description of A0-A15. See also p. 5, Sec.
`4.30.4, “... no refresh activities in the memory
`arrays ...”
`Thus, the DDR2 memory module is within
`the scope of the preamble.
`
`The Court has determined that “memory
`device” means “integrated circuit or chip”;
`that “a plurality of volatile solid state memory
`devices” means “two or more memory
`devices in the memory system into which
`data may be written or from which data
`may be retrieved that retain information
`while a electrical power source, having a
`predetermined voltage range, is applied to
`the memory devices and when the voltage
`reaches a predetermined threshold outside
`of that range, the memory devices will no
`longer retain their current state of
`information”
`
`The JESD79-4-1 (Ex. 6) at p. 123 refers to
`the memory module as being a “chip”. See
`Sec. 4.26 stating, “the chip enters a Refresh
`cycle”. Hence, the DDR4 is a chip.
`
`The JESD79-4-1 (Ex. 7) at p. 150, Table 62
`states the absolute maximum DC Ratings. P.
`151, Table 63 shows the recommended DC
`
`Page 1 of 4
`
`SMART Exhibit - 1017 - Page 8
`
`

`
`Operating Conditions with a minimum and
`maximum for the DC voltages. Hence, the
`DDR4 requires a specific range of applied of
`voltage to retain data.
`
`The JESD79-4-1 (Ex. 7) identifies the DDR4
`as having a memory array in the description
`of A0-A15. See also p. 5, Sec. 4.30.4, “... no
`refresh activities in the memory arrays ...”
`
`The JESD79-4-1 (Ex. 8) shows that the
`DDR4 is capable of being refreshed at the
`following places: p. 37, Sec. 4.9.5 entitled,
`“Self Refresh entry and exit”; p. 123, Sec.
`4.26 entitled, “Refresh Command”; and p.
`124, Sec. 4.27 entitled, “Self refresh
`Operation”.
`
`capable of being placed in a self refresh
`mode;
`
`Page 2 of 4
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`SMART Exhibit - 1017 - Page 9
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`

`
`said memory devices having address lines and
`control lines;
`a control device for selectively electrically
`isolating said memory devices from
`respective address lines and respective control
`lines so that when said memory devices are
`electrically isolated, any signals received on
`said respective address lines and respective
`control lines do not reach said memory
`devices; and
`
`The Court has determined that “control
`device” means “a device in the memory
`system that is interposed between the
`respective address lines and respective
`control lines that electrically isolates the
`memory devices”; that “selectively
`electrically isolating said memory devices
`from respective address lines and respective
`control lines’ means “inhibiting signals on
`the respective address and respective
`control lines from the memory devices such
`that signals on those lines do not arrive at
`the memory devices”; that “address lines”
`mean “lines that carry signals specifying a
`memory location to be accessed”; “control
`lines” mean “lines that carry control
`signals”; and “control signals” mean “signals
`that control the sequence of addressing
`and the memory mode”. It is noted that the
`term “control signals” does not appear in
`claim 1.
`
`During testing and evaluation of the DDR4, it
`is necessary for Smart Modular to connect
`subsystems to the DDR4 using the input and
`output terminals of the DDR4. Obviously,
`the use of the term “interposed” relates to the
`electrically operation of the control device,
`not a physical positioning.
`
`The JESD79-4-1 (Ex. 8) at p. 5, Sec. 2.6
`identifies address lines connected to inputs
`such as for symbols “BA0-BA2", and “A0-
`A15". The JESD79-4-1 uses the terms
`“command signal”, and “command line” for
`the defined “control signal” and “control
`line”. At p. 13, Sec. 2.3, RAS, CAS, WE
`(line over each) are command inputs. The
`command signals on the input terminals
`connect into the DDR4 on “control lines” to
`control the sequence and memory mode. See
`p. 24, Sec. 4.1.
`
`Page 3 of 4
`
`SMART Exhibit - 1017 - Page 10
`
`

`
`a memory access enable control device
`coupled to said control device and to said
`control lines for determining when said
`memory system is not being accessed and for
`initiating a low power mode for said memory
`system wherein said control device
`electrically isolates said memory devices and
`places said memory devices in said self
`refresh mode, thereby reducing the amount of
`electrical energy being drawn from an
`electrical power supply for said computer
`system.
`
`JESD79-4-1 (Ex. 8), p. 127, Sec. 4.28 states,
`“ Power-down is synchronously entered when
`CKE is registered low (along with Deselect
`command). CKE is not allowed to go low
`while mode register set command, MPR
`operations, ZQCAL operations, DLL locking
`all read/write operations are in progress. P.
`25, Sec. 4.2, The Truth Table for CKE states
`in NOTE 15 that “X” means “don’t care” for
`the commands on input terminals RAS, CAS,
`WE, and CS. Note that a response of “Don’t
`Care”, is the same as “electrically isolating”
`the memory device. The “Power Down”
`reduces electrical power consumption.
`
`Page 4 of 4
`
`SMART Exhibit - 1017 - Page 11
`
`

`
`CLAIM CHART AND ASSOCIATED CONSTRUCTION
`
`U.S. Patent No. 6,243,315
`
`Claim 1. A memory system for use in a
`computer system, said memory system
`comprising:
`
`a plurality of volatile solid state memory
`devices that retain information when an
`electrical power source is applied to said
`memory devices within a predetermined
`voltage range and
`
`SMART MODULAR MEMORY
`MODULE DDR2
`
`The Court has determined that a “memory
`system” is “a system capable of retaining
`data”. The JESD79-2F (Ex. 6) identifies the
`DDR2 as having a memory array in the
`description of A0-A15. See also p. 45, Sec.
`3.8, “The precharge operation engaged by the
`Auto precharge command will not begin until
`the last data of the burst write sequence is
`properly stored in the memory array.
`
`Thus, the DDR2 memory module is within
`the scope of the preamble.
`
`The Court has determined that “memory
`device” means “integrated circuit or chip”;
`that “a plurality of volatile solid state memory
`devices” means “two or more memory
`devices in the memory system into which
`data may be written or from which data
`may be retrieved that retain information
`while a electrical power source, having a
`predetermined voltage range, is applied to
`the memory devices and when the voltage
`reaches a predetermined threshold outside
`of that range, the memory devices will no
`longer retain their current state of
`information”
`
`The JESD79-2F (Ex. 6) at p. 49 refers to the
`memory module as being a “chip”. See Sec.
`3.9 stating, “the chip enters a Refresh cycle”.
`Hence, the DDR2 is a chip.
`
`Page 1 of 4
`
`SMART Exhibit - 1017 - Page 12
`
`

`
`The JESD79-2F (Ex. 6) at p. 161, Sec. 5
`states the absolute maximum DC Ratings.
`P.62, Sec. 6 shows the recommended DC
`Operating Conditions with a minimum and
`maximum for the DC voltages. Hence, the
`DDR2 requires a specific range of applied of
`voltage to retain data.
`
`The JESD79-2F (Ex. 6) identifies the DDR2
`as having a memory array in the description
`of A0-A15. See also p. 45, Sec. 3.8, “The
`precharge operation engaged by the Auto
`precharge command will not begin until the
`last data of the burst write sequence is
`properly stored in the memory array.
`
`The JESD79-2F (Ex. 6) shows that the DDR2
`is capable of being refreshed at the following
`places: p. 13 concerning the function of
`CKE, “For proper self-refresh entry and
`exit,...”; p. 62, “Currently the periodic Self-
`Refresh interval is hard coded within the
`DRAM to a vendor specific value.”
`
`capable of being placed in a self refresh
`mode;
`
`Page 2 of 4
`
`SMART Exhibit - 1017 - Page 13
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`

`
`a control device for selectively electrically
`isolating said memory devices from
`respective address lines and respective control
`lines so that when said memory devices are
`electrically isolated, any signals received on
`said respective address lines and respective
`control lines do not reach said memory
`devices; and
`
`The Court has determined that “control
`device” means “a device in the memory
`system that is interposed between the
`respective address lines and respective
`control lines that electrically isolates the
`memory devices”; that “selectively
`electrically isolating said memory devices
`from respective address lines and respective
`control lines’ means “inhibiting signals on
`the respective address and respective
`control lines from the memory devices such
`that signals on those lines do not arrive at
`the memory devices”; that “address lines”
`mean “lines that carry signals specifying a
`memory location to be accessed”; “control
`lines” mean “lines that carry control
`signals”; and “control signals” mean “signals
`that control the sequence of addressing
`and the memory mode”. It is noted that the
`term “control signals” does not appear in
`claim 1.
`
`During testing and evaluation of the DDR2, it
`is necessary for Smart Modular to connect
`subsystems to the DDR2 using the input and
`output terminals of the DDR2. Obviously,
`the use of the term “interposed” relates to the
`electrically operation of the control device,
`not a physical positioning.
`
`The JESD79-2F (Ex. 6) at p. 13, Sec. 2.3
`identifies address lines connected to inputs
`such as for symbols “BA0-BA2", and “A0-
`A15". The JESD79-2F uses the terms
`“command signal”, and “command line” for
`the defined “control signal” and “control
`line”. At p. 13, Sec. 2.3, RAS, CAS, WE
`(line over each) are command inputs. The
`command signals on the input terminals
`connect into the DDR23 on “control lines” to
`control the sequence and memory mode. See
`p. 18, Sec. 3.4.1.
`
`Page 3 of 4
`
`SMART Exhibit - 1017 - Page 14
`
`

`
`a memory access enable control device
`coupled to said control device and to said
`control lines for determining when said
`memory system is not being accessed and for
`initiating a low power mode for said memory
`system wherein said control device
`electrically isolates said memory devices and
`places said memory devices in said self
`refresh mode, thereby reducing the amount of
`electrical energy being drawn from an
`electrical power supply for said computer
`system.
`
`JESD79-2F (Ex. 6), Sec. 3.11 states, “ Power-
`down is synchronously entered when CKE is
`registered low (along with NOP or Deselect
`command). CKE is not allowed to go low
`while mode register set command, MPR
`operations, ZQCAL operations, DLL locking
`all read/write operations are in progress. P.
`33, Sec. 4.2 shows a Truth Table and for
`Power Down, CKE is low which deactivates
`the internal clock signals and device input
`buffers and output drivers according to Sec.
`2.10. The Truth Table at p. 58 for Power-
`Down states in NOTE 15 that “X” means
`“don’t care” for the commands on input
`terminals RAS, CAS, WE, and CS. Note also
`Sec.2.3 CKE LOW deactivated internal clock
`signals and device input buffers and output
`drivers.
`
`Note that a response of “Don’t Care”, is the
`same as “electrically isolating” the memory
`device. The “Power Down” reduces electrical
`power consumption.
`
`David Fink
`Fink & Johnson
`7519 Apache Plume
`Houston, TX 77071
`Tel. 713 729-4991
`Fax. 713 729-8408
`texascowboy6@gmail.com
`Attorney in Charge
`
`Page 4 of 4
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`SMART Exhibit - 1017 - Page 15