SMART EXHIBIT 1009
`
`SMART EXHIBIT 1009
`
`

`
`MICHDN
`
`ADVANCE
`
`MT48LC2M8S1(S)
`2 MEG x 8 SDRAM
`
`SYNCHRONOUS
`DRAM
`
`2 ME_G x 8SDRAM
`i.:,iJJ|EiE3sdTRn//i<)Sde|,Dl.iiijl:i\?,as‘I|§’LF REFRESH
`
`FEATURES
`
`Fully synchronous; all signals (excluding clock enable) ,
`registered to positive edge of system clock
`Meets all ]EDEC functional specifications
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`*'
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`Programmable burst—sequence: sequential or interleave
`Burst termination
`Multiple burst READ, single WRITE capability
`Hidden precharge capability with optional automatic
`precharge command
`Programmable READ latency: 1, 2 or 3 clocks
`Industry-standard x8 pinouls, timing, functions and
`packages
`Refresh modes: AUTO and SELF
`Standard and extended AUTO REFRESH rates
`High-performance CMOS silicon—gate process
`Lead—over—chip assembly architecture
`Single +3.3-V iU.3V power supply
`Low power, 3mW standby; 200mW active, typical
`LVTTL—compatiblc
`CKE—controlled power-down and suspend operations
`Mode register programming
`]EDEC—standard command set (pulsedRE)
`
`MARKING
`'10
`-12
`-13
`
`OP:-rI.ONS
`’ T‘m“"g
`(5100 MHZ)
`10115 303955
`l 583 MHZ)
`12115 “C955
`13-3ns access ( :75 MHZ)
`AUTO REFRESH
`4_[)96_cyC1e in 64,115 (15_5u5/ row)
`4,[)96-cyc1e in 1231-ns (31.25p5/row)
`SELF REFRESH
`Not allowed
`Allowed
`_
`_
`P1a5t_‘C Packages
`T5
`44'P1“ T501) (400 m11)—f0fWaTd
`Part Number Example: MT48LC2M8S1TG—10 S
`
`_
`
`GENERAL DESCRIPTION
`The MT48LC2M8Sl(S) is a randomly acccsscd, solid-
`state memory containing 16,777,216 bits organized in a X8
`configuration. It is structured as a dual 1 Meg x 8 DRAM
`
`MT4aLc2MaSHs)
`FFV A/an
`
`PIN ASSIGNMENT (Top View)
`
`‘*4"’'" 75°”
`FORWARD
`(DD‘7)
`
`MT48C2M8S1TG
`
`
`
`INVHGSFIONOHHONAS
`
`with a synchronous interface. Each byte is uniquely ad-
`dressed through a bank—select bit and 20 address bits. The
`bank select and address are entered first by RAS registering
`(row active command) 12 bits (A0-A10, BA) and then
`CAS registering 10 hits (AO—A8, BA). At CAS registration
`(READ or WRITE command), address bit Al 0 defines auto’
`precharge state (active HIGH). Bank selection is controlled
`by BA during both RAS and CAS registration.
`Tlieflvl 1;18LL2M8S1 is designed to operate in a synchrlo.
`nous, 33\ memory system. All input and output signa s,
`with the exception of clock enable (CKE) during PQWER—
`DOWN and SELF REFRESH modes, are synchronized to
`the positive-going edge of the system clock (CLK).
`The synchronous DRAM has several programmable fea-
`tures to allow maximum performance in eachuser's system.
`Additionally, bank switching between the two internal
`memory banks in conjunction with theprogrammable BURST
`mode provides very high~speed performance.
`The synchronous DRAM allows both AUTO REFRESH
`(during normal operation) and SELF REFRESH (for low-
`power, data-retention operation).
`
`Micron somiccrctctor. Inc
`
`reserves the ngm Io change 'i'fl(I|ll"li or sueulications without nmice
`(V‘g9“ Mirmn spmimmuucv in:
`
`SMART EXHIBIT 1009 - PAGE - 1
`
`

`
`ADVANCE
`
`M 48LC2M8S1(S)
`2 MEG x 8 SDRAM
`
`DATA—|N
`BUFFER
`
`DATAOUT
`BUFFER
`
`FUNCTIONAL BLOCK DIAGRAM
`
`I <
`
`1:
`
`
`
`CONTROLLOGIC
`
`DECODE
`
`COMMAND
`
`REFRESH
`CONTROLLER
`
`REFRESH
`OSCILLATOR
`and TIMER
`
`ROW-
`ADDRESS
`LATCH
`
`NO. 1 CLOCK
`GENERATOR
`
`ROW-
`ADDRESS
`BUFFERS
`
`ROWDECODER
`
`COLUMN-
`
`
`
`ADDRESSLATCH
`
`
`
`BURSTCOUNTER
`
`COLUMN-
`
`
`
`ADDRESSBUFFER
`
`NO. 2 CLOCK
`GENERATOR
`
`ROW-
`ADDRESS
`BUFFER5
`
`ROWDECODER
`
`BANK 0
`MEMORY
`ARRAY
`
`:--1COLUMN
`DECODER
`
`—- 512
`
`BANK 1
`MEMORY
`ARRAY
`
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`HEV 4/94
`
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`4'(‘|!?9fl‘ MLCFG1 Semconductm, Inc.
`
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`
`5 o z 0 c m U :
`
`u > E
`
`SMART EXHIBIT 1009 - PAGE - 2