SMART EXHIBIT 1008
`
`SMART EXHIBIT 1008
`
`

`
`JEDEC
`STANDARD
`
`DDR2 SDRAM SPECIFICATION
`
`JESD79-2F
`(Revision of JESD79-2E)
`
`November 2009
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`SMART EXHIBIT 1008 - PAGE - 1
`
`

`
`NOTICE
`
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`by the JEDEC legal Counsel.
`
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`
`The information included in JEDEC standards and publications represents a sound approach to
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`
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`
`Published by
`©JEDEC Solid State Technology Association 2009
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`SMART EXHIBIT 1008 - PAGE - 2
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`

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`
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`P LE A S E !
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`D O N ’T V IO LA T E
`T H E
`LA W !
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`T his docum ent is copyrighted by the E lectronic Industries A lliance and m ay not be
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`through entering into a license agreem ent. F or inform ation, contact:
`
`JE D E C S olid S tate T echnology A ssociation
`2500 W ilson B oulevard
`A rlington, V irginia 22201-3834
`or call (703) 907-7559
`
`
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`SMART EXHIBIT 1008 - PAGE - 3
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`SMART EXHIBIT 1008 - PAGE - 4
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`JEDEC Standard No. 79-2F
`
`Contents
`1 Scope ................................................................................................................................................. 1
`2 Package ballout & addressing ......................................................................................................... 2
`2.1 DDR2 SDRAM package ballout ...................................................................................................... 2
`2.2 Quad-stacked/quad-die DDR2 SDRAM internal rank associations .............................................. 11
`2.3
`Input/output functional description ................................................................................................ 13
`2.4 DDR2 SDRAM addressing ............................................................................................................ 14
`3 Functional description ................................................................................................................... 16
`3.1 Simplified state diagram ................................................................................................................ 16
`3.2 Basic functionality ......................................................................................................................... 16
`3.3 Power-up and initialization ............................................................................................................ 16
`3.3.1
`Power-up and initialization sequence ........................................................................................ 17
`3.4 Programming the mode and extended mode registers ................................................................. 18
`3.4.1 DDR2 SDRAM mode register (MR) ........................................................................................... 18
`3.4.2 DDR2 SDRAM extended mode registers (EMR(#)) ................................................................... 19
`3.4.3 Off-chip driver (OCD) impedance adjustment ............................................................................ 24
`3.4.4 ODT (on-die termination) ........................................................................................................... 27
`3.4.5 ODT related timings ................................................................................................................... 27
`3.5 Bank activate command ................................................................................................................ 32
`3.6 Read and write access modes ...................................................................................................... 32
`3.6.1
`Posted CAS ............................................................................................................................... 32
`3.6.2
`Burst mode operation ................................................................................................................ 34
`3.6.3
`Burst read command ................................................................................................................. 34
`3.6.4
`Burst write operation .................................................................................................................. 37
`3.6.5 Write data mask ......................................................................................................................... 40
`3.7 Precharge operation ..................................................................................................................... 41
`3.7.1
`Burst read operation followed by precharge .............................................................................. 42
`3.7.2
`Burst write followed by precharge .............................................................................................. 44
`3.8 Auto precharge operation ............................................................................................................. 45
`3.8.1
`Burst read with auto precharge .................................................................................................. 46
`3.8.2
`Burst write with auto precharge ................................................................................................. 48
`3.9 Refresh command ......................................................................................................................... 49
`3.10 Self refresh operation .................................................................................................................... 50
`3.11 Power-down .................................................................................................................................. 51
`3.12 Asynchronous CKE LOW event .................................................................................................... 55
`3.13 Input clock frequency change during precharge power down ....................................................... 56
`3.14 SSC (Spread Spectrum Clocking) ................................................................................................ 57
`3.14.1 Terms and definitions ................................................................................................................ 57
`3.14.2 SSC (Spread Spectrum Clocking) Criteria ................................................................................. 57
`3.14.3 Allowed SSC band .................................................................................................................... 57
`3.15 No operation command ................................................................................................................. 57
`3.16 Deselect command ....................................................................................................................... 57
`4 Truth tables ..................................................................................................................................... 58
`4.1 Command truth table .................................................................................................................... 58
`4.2 Clock enable truth table. ............................................................................................................... 59
`4.3 Data mask truth table. ................................................................................................................... 60
`5 Absolute maximum DC ratings ...................................................................................................... 61
`6 AC & DC operating conditions ...................................................................................................... 62
`
`Annex A (informative) Differences between JESD79-2F and JESD79-2E ..................................... 109
`
`-i-
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`SMART EXHIBIT 1008 - PAGE - 5
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`

`
`JEDEC Standard No. 79-2F
`
`Figures
`
`1 DDR2 SDRAM x4 ballout using MO-207 ............................................................................................ 2
`2 DDR2 SDRAM x8 ballout using MO-207 ............................................................................................ 3
`3 DDR2 SDRAM x16 ballout using MO-207 .......................................................................................... 4
`4 Stacked/dual-die DDR2 SDRAM x4 ballout using MO-242 ................................................................ 5
`5 Stacked/dual-die DDR2 SDRAM x8 ballout using MO-242 ................................................................ 6
`6 Stacked/dual-die DDR2 SDRAM x16 ballout using MO-242 .............................................................. 6
`7 Quad-stacked/quad-die DDR2 SDRAM x4 ballout using MO-242 ..................................................... 8
`8 Quad-stacked/quad-die DDR2 SDRAM x8 ballout using MO-242 ..................................................... 9
`9 Quad-stacked/quad-die DDR2 SDRAM x16 ballout using MO-242 ................................................. 10
`10 Quad-stacked/quad-die DDR2 SDRAM x4 rank association ........................................................... 11
`11 Quad-stacked/quad-die DDR2 SDRAM x8 rank association ........................................................... 11
`12 Quad-stacked/quad-die DDR2 SDRAM x16 rank association ......................................................... 12
`13 DDR2 SDRAM simplified state diagram ........................................................................................... 16
`14 Initialization sequence after power-up .............................................................................................. 18
`15 DDR2 SDRAM mode register set (MRS) ......................................................................................... 19
`16 EMR(1) programming ....................................................................................................................... 21
`17 EMR(2) programming ....................................................................................................................... 23
`18 EMR(3) programming ....................................................................................................................... 24
`19 OCD impedance adjustment ............................................................................................................ 24
`20 OCD adjust mode ............................................................................................................................. 26
`21 OCD drive mode ............................................................................................................................... 26
`22 Functional representation of ODT .................................................................................................... 27
`23 ODT update delay timing - tMOD ..................................................................................................... 28
`24 ODT update delay timing - tMOD, as measured from outside ......................................................... 28
`25 ODT timing for active/standby mode ................................................................................................ 29
`26 ODT timing for power-down mode ................................................................................................... 29
`27 ODT timing mode switch at entering power-down mode .................................................................. 30
`28 ODT timing mode switch at exiting power-down mode .................................................................... 31
`29 Bank activate command cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2 ............................. 32
`30 Example 1: Read followed by a write to the same bank,
`where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4 .......................... 33
`31 Example 2: Read followed by a write to the same bank,
`where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4 .......................... 33
`32 Data output (read) timing .................................................................................................................. 35
`33 Burst read operation: RL = 5 (AL = 2, CL = 3, BL = 4) ..................................................................... 35
`34 Burst read operation: RL = 3 (AL = 0 and CL = 3, BL = 8) ............................................................... 35
`35 Burst read followed by burst write: RL = 5, WL = (RL-1) = 4, BL = 4 ............................................... 36
`36 Seamless burst read operation: RL = 5, AL = 2, and CL = 3, BL = 4 ............................................... 36
`37 Read burst interrupt timing example: (CL=3, AL=0, RL=3, BL=8) .................................................... 37
`38 Data input (write) timing ................................................................................................................... 38
`39 Burst write operation: RL = 5 (AL=2, CL=3), WL = 4, BL = 4 ........................................................... 38
`40 Burst write operation: RL = 3 (AL=0, CL=3), WL = 2, BL = 4 ........................................................... 38
`41 Burst write followed by burst read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4 ...................... 39
`42 Seamless burst write operation: RL = 5, WL = 4, BL = 4 ................................................................. 39
`43 Write burst interrupt timing example: (CL=3, AL=0, RL=3, WL=2, BL=8) ........................................ 40
`44 Write data mask ............................................................................................................................... 41
`45 Example 1: Burst read operation followed by precharge:
`RL = 4, AL = 1, CL = 3, BL = 4, tRTP <= 2 clocks ............................................................... 42
`46 Example 2: Burst read operation followed by precharge:
`RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks ............................................................... 43
`47 Example 3: Burst read operation followed by precharge:
`RL = 5, AL = 2, CL = 3, BL = 4, tRTP <= 2 clocks ............................................................... 43
`
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`SMART EXHIBIT 1008 - PAGE - 6
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`

`
`JEDEC Standard No. 79-2F
`
`Figures
`48 Example 4: Burst read operation followed by precharge:
`RL = 6, AL = 2, CL = 4, BL = 4, tRTP <= 2 clocks ............................................................... 44
`49 Example 5: Burst read operation followed by precharge:
`RL = 4, AL = 0, CL = 4, BL = 8, tRTP > 2 clocks ................................................................. 44
`50 Example 1: Burst write followed by precharge: WL = (RL-1) =3 ...................................................... 45
`51 Example 2: Burst write followed by precharge: WL = (RL-1) = 4 ..................................................... 45
`52 Example 1: Burst read operation with auto precharge:
`RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks ............................................................... 46
`53 Example 2: Burst read operation with auto precharge:
`RL = 4, AL = 1, CL = 3, BL = 4, tRTP > 2 clocks ................................................................. 47
`54 Example 3: Burst read with auto precharge
`followed by an activation to the same bank (tRC Limit):
`RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks) ................................ 47
`55 Example 4: Burst read with auto precharge
`followed by an activation to the same bank (tRP Limit):
`RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks) ................................ 48
`56 Burst write with auto-precharge (tRC Limit): WL = 2, WR = 2, BL = 4, tRP = 3 ............................... 48
`57 Burst write with auto-precharge (WR + tRP): WL = 4, WR = 2, BL = 4, tRP = 3 .............................. 49
`58 Refresh command ............................................................................................................................ 50
`59 Self refresh operation ....................................................................................................................... 51
`60 Basic power down entry and exit timing diagram ............................................................................. 52
`61 Example 1 of CKE intensive environment ........................................................................................ 52
`62 Example 2 of CKE intensive environment ........................................................................................ 52
`63 Read to power-down entry ............................................................................................................... 53
`64 Read with autoprecharge to power-down entry ................................................................................ 53
`65 Write to power-down entry ............................................................................................................... 54
`66 Write with autoprecharge to power-down entry ................................................................................ 54
`67 Refresh command to power-down entry .......................................................................................... 55
`68 Active command to power-down entry ............................................................................................. 55
`69 Precharge/precharge-all command to power-down entry ................................................................ 55
`70 MRS/EMRS command to power-down entry .................................................................................... 55
`71 Asynchronous CKE LOW event ....................................................................................................... 56
`72 Clock frequency change in precharge power-down mode ............................................................... 56
`73 AC input test signal waveform .......................................................................................................... 64
`74 Differential signal levels .................................................................................................................... 65
`75 AC overshoot and undershoot definition for address and control pins ............................................. 66
`76 AC overshoot and undershoot definition for clock, data, strobe, and mask pins .............................. 66
`77 DDR2 default pulldown characteristics for full strength driver .......................................................... 69
`78 DDR2 default pullup characteristics for full strength output driver ................................................... 70
`79 DDR2 default pulldown characteristics for reduced strength drive ................................................... 71
`80 DDR2 default pullup characteristics for reduced strength driver ...................................................... 72
`81 AC timing reference load .................................................................................................................. 83
`82 Slew rate test load ............................................................................................................................ 83
`83 Data Input (Write) Timing ................................................................................................................. 84
`84 Data output (read) timing .................................................................................................................. 84
`85 Illustration of nominal slew rate for tDS (differential DQS, DQS) ..................................................... 87
`86 Illustration of nominal slew rate for tDS (single-ended DQS) ........................................................... 88
`87 Illustration of tangent line for tDS (differential DQS, DQS) ............................................................... 89
`88 Illustration of tangent line for tDS (single-ended DQS) ................................................................... 90
`89 Illustration of nominal slew rate for tDH (differential DQS, DQS) ..................................................... 91
`90 Illustration of nominal slew rate for tDH (single-ended DQS) .......................................................... 92
`91 Illustration tangent line for tDH (differential DQS, DQS) .................................................................. 93
`
`-iii-
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`SMART EXHIBIT 1008 - PAGE - 7
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`

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`JEDEC Standard No. 79-2F
`
`Figures
`
`92 Illustration tangent line for tDH (single-ended DQS) ....................................................................... 94
`93 Illustration of nominal slew rate for tIS ............................................................................................. 97
`94 Illustration of tangent line for tIS ....................................................................................................... 98
`95 Illustration of nominal slew rate for tIH ............................................................................................. 99
`96 Illustration tangent line for tIH ......................................................................................................... 100
`97 Method for calculating transitions and endpoints ........................................................................... 102
`98 Differential input waveform timing – tDS and tDH .......................................................................... 102
`99 Differential input waveform timing – tIS and tIH ............................................................................. 103
`
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`SMART EXHIBIT 1008 - PAGE - 8
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`

`
`JEDEC Standard No. 79-2F
`
`Tables
`1 Ball descriptions ............................................................................................................................... 13
`2
`128 Mb addressing ........................................................................................................................... 14
`3
`256 Mb addressing .......................................................................................................................... 14
`4
`512 Mb addressing .......................................................................................................................... 14
`5
`1 Gb addressing ............................................................................................................................... 15
`6
`2 Gb addressing ............................................................................................................................... 15
`7
`4 Gb addressing ............................................................................................................................... 15
`8 OCD drive mode program ................................................................................................................ 25
`9 OCD adjust mode program .............................................................................................................. 25
`10 Burst length and sequence .............................................................................................................. 34
`11 Bank selection for precharge by address bits .................................................................................. 41
`12 Precharge & auto precharge clarification ......................................................................................... 49
`13 Command truth table ....................................................................................................................... 58
`14 Clock enable (CKE) truth table for synchronous transitions ............................................................ 59
`15 DM truth table .................................................................................................................................. 60
`16 Absolute maximum DC ratings ........................................................................................................ 61
`17 Recommended DC operating conditions (SSTL_1.8) ...................................................................... 62
`18 Operating temperature condition ..................................................................................................... 62
`19 ODT DC electrical characteristics .................................................................................................... 63
`20 Input DC logic level .......................................................................................................................... 64
`21 Input AC logic level .......................................................................................................................... 64
`22 AC input test conditions ................................................................................................................... 64
`23 Differential input AC logic level ........................................................................................................ 65
`24 Differential AC output parameters .................................................................................................... 65
`25 AC overshoot/undershoot specification for address and control pins:
`A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT ............................................................. 65
`26 AC overshoot/undershoot specification for clock, data, strobe, and mask pins:
`DQ, (U/L/R)DQS, (U/L/R)DQS, DM, CK, CK ......................................................................... 66
`27 V-I characteristics for input-only pins with clamps ........................................................................... 67
`28 Output AC test conditions ................................................................................................................ 67
`29 Output DC current drive ................................................................................................................... 67
`30 OCD default characteristics ............................................................................................................. 68
`31 Full strength default pulldown driver characteristics ........................................................................ 69
`32 Full strength default pullup driver characteristics ............................................................................. 70
`33 Reduced strength default pulldown driver characteristics ................................................................ 71
`34 Reduced strength default pullup driver characteristics .................................................................... 72
`35 Full strength calibrated pulldown driver characteristics ................................................................... 73
`36 Full strength calibrated pullup driver characteristics ........................................................................ 73
`37 IDD specification parameters and test conditions
`(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 6) .............. 74
`38 IDD testing parameters .................................................................................................................... 76
`39 Input/output capacitance .................................................................................................................. 77
`40 Refresh parameters by device density ............................................................................................. 78
`41 DDR2 SDRAM standard speed bins and tCK/tCK(avg), tRCD, tRP, tRAS and tRC
`for corresponding bin ............................................................................................................. 78
`42 Timing parameters by speed grade (DDR2-400 and DDR2-533)..................................................... 79
`43 Timing parameters by speed grade (DDR2-667 and DDR2-800)..................................................... 81
`44 DDR2-400/533 tDS/tDH derating with differential data strobe ......................................................... 85
`45 DDR2-667/800 tDS/tDH derating with differential data strobe ......................................................... 85
`46 DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe ................................................. 86
`47 Derating values for DDR2-400, DDR2-533. .................................................................................... 95
`48 Derating values for DDR2-667, DDR2-800 ...................................................................................... 96
`
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`SMART EXHIBIT 1008 - PAGE - 10
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`JEDEC Standard No. 79-2F
`Page 1
`
`1 Scope
`This document defines the DDR2 SDRAM specification, including features, functionalities, AC
`and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification
`is to define the minimum set of requirements for JEDEC-compliant 256 Mb through 4 Gb for x4,
`x8, and x16 DDR2 SDRAM devices. This specification was created based on the DDR
`specification (JESD79). Each aspect of the changes for DDR2 SDRAM operation were
`considered and approved by committee ballot(s). The accumulation of these ballots were then
`incorporated to prepare this JESD79-2 specification.
`
`SMART EXHIBIT 1008 - PAGE - 11
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`

`
`JEDEC Standard No. 79-2F
`Page 2
`
`2 Package ballout & addressing
`2.1 DDR2 SDRAM package ballout
`
`Variation DM-z with support balls
`
`A
`
`B C D
`
`E
`F
`G
`H
`J
`K
`L
`M
`N
`P
`
`R T U V
`
`W
`
`(Top view: see balls through package)
`
`3
`
`4 5
`
`6
`
`7
`
`8
`
`NC
`
`9
`
`NC
`
`1
`
`NC
`
`2
`
`NC
`
`VSSQ
`DQS
`VDDQ
`DQ2
`VSSDL
`RAS
`CAS
`A2
`A6
`A11
`NC, A15
`
`DQS
`VSSQ
`DQ0
`VSSQ
`CK
`CK
`CS
`A0
`A4
`A8
`NC, A13
`
`VDDQ
`NC
`VDDQ
`NC
`VDD
`ODT
`
`VDD
`
`VSS
`
`VDD
`NC
`VDDQ
`NC
`VDDL
`
`NC, BA2
`
`VSS
`
`VDD
`
`NC
`VSSQ
`DQ1
`VSSQ
`VREF
`CKE
`BA0
`A10/AP
`A3
`A7
`A12
`
`VSS
`DM
`VDDQ
`DQ3
`VSS
`WE
`BA1
`A1
`A5
`A9
`NC, A14
`
`A
`B
`C
`D
`E
`F
`G
`H
`J
`K
`L
`
`Variation DJ-z without support balls
`
`NC
`
`NC
`
`NC
`
`NC
`
`Variation DM-z (x4/x8)
`with support balls
`1 2 3 4
`5 6 7
`8 9
`
`ABCDEFGHJKLMNPRTU WV
`
`Populated ball
`Ball not populated
`
`Variation DJ-z (x4/x8)
`without support balls
`1 2 3 4
`8 9
`5 6 7
`
`ABCDEFGHJKL
`
`Figure 1 — DDR2 SDRAM x4 ballout using MO-207
`
`SMART EXHIBIT 1008 - PAGE - 12
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`

`
`JEDEC Standard No. 79-2F
`Page 3
`
`Variation DM-z with support balls
`
`A
`
`B C D
`
`E
`F
`G
`H
`J
`K
`L
`M
`N
`P
`
`R T U V
`
`2 Package ballout & addressing (cont’d)
`2.1 DDR2 SDRAM package ballout (cont’d)
`
`(Top view: see balls through package)
`
`3
`
`4 5
`
`6
`
`7
`
`1
`
`NC
`
`2
`
`NC
`
`8
`
`NC
`
`9
`
`NC
`
`DQS
`VSSQ
`VSSQ
`DQS
`DQ0
`VDDQ
`VSSQ
`DQ2
`CK
`VSSDL
`CK
`RAS
`CS
`CAS
`A0
`A2
`A4
`A6
`A8
`A11
`NC, A15 NC, A13
`
`VDDQ
`DQ7
`VDDQ
`DQ5
`VDD
`ODT
`
`VDD
`
`VSS
`
`A
`B
`C
`D
`E
`F
`G
`H
`J
`K
`L
`
`VDD
`DQ6
`VDDQ
`DQ4
`VDDL
`
`NC, BA2
`
`VSS
`
`VDD
`
`NU/RDQS
`VSSQ
`DQ1
`VSSQ
`VREF
`CKE
`BA0
`A10/AP
`A3
`A7
`A12
`
`VSS
`DM/RDQS
`VDDQ
`DQ3
`VSS
`WE
`BA1
`A1
`A5
`A9
`NC, A14
`
`Variation DJ-z without support balls
`
`NC
`NC
`NOTE 1 B1, B9, D1, D9 = NC for x4 organization per variation DJ-z.
`NOTE 2 Pins B3 and A2 have identical capacitances as