`Case No. TBD
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SMART MODULAR TECHNOLOGIES INC.
`
`Petitioner
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`v.
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`JAMES B. GOODMAN
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`Patent Owner
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`Case No. TBD
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`Patent 6,243,315
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`DECLARATION OF DR. NADER BAGHERZADEH
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`UNDER 37 C.F.R. § 1.68
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`SMART EXHIBIT - 1002
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`
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`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
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`I, Nader Bagherzadeh, declare as follows:
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`1.
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`I am making this declaration at the request of SMART Modular
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`Technologies, Inc. in support of SMART’s Inter Partes review of U.S. Patent No.
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`6,243,315. This declaration includes Appendices A to B.
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`2.
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`I am being compensated for my services in this matter at the rate of
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`$450/hour plus expenses. My compensation is not contingent upon the outcome of
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`this proceeding.
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`3.
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`In preparing this declaration, I considered the following materials:
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`a.
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`the ‘315 patent, attached as Exhibit 1001;
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`b. the ‘315 patent file history;
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`c. Plaintiff’s Amended Infringement Chart For U.S. Patent No.
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`6,243,315 From Case No. 4:14-cv-01380 GHM (S.D. Tex.), attached
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`as Exhibit 1003;
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`d. U.S. Patent No. 5,600,605 to Schaefer (“Schaefer”), attached as
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`Exhibit 1004;
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`e. U.S. Patent No. 5,793,776 to Qureshi et al. (“Qureshi”), attached as
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`Exhibit 1005;
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`f. U.S. Patent No. 5,204,840 to Mazur (“Mazur”), attached as Exhibit
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`1006;
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`g. JEDEC DDR SDRAM Specification JESD79 R1, June 2000
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`SMART EXHIBIT - 1002 - PAGE 1
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`ATTORNEY DOCKET NO.: 21584-112006
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`(“JESD79”), attached as Exhibit 1007;
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`h. JEDEC DDR2 SDRAM Specification JESD79-2F, November 2009
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`(“JESD792F”), attached as Exhibit 1008;
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`i. Micron MT48LC2M8S1(S) Datasheet, April 1994 (“Micron Datasheet),
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`attached as Exhibit 1009;
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`j. Micron MT48LC2M8S1(S) Specification Sheet, June 1993 (“Micron
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`Specs”), attached as Exhibit 1010;
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`k. JEDEC DDR3 SDRAM Specification JESD79-3E, July 2010
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`(“JESD793E”), attached as Exhibit 1012;
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`l. U.S. Patent No. 4,005,395 to Fosler, Jr. et. al. (“Fosler”), attached as
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`Exhibit 1013;
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`m. Reengineering the Curriculum: Design and Analysis of a New Undergraduate
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`Electrical and Computer Engineering Degree at Carnegie Mellon University,
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`Director et al., IEEE 1995, attached as Exhibit 1014; and
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`n. Plaintiff’s Second Amended Infringement Chart For U.S. Patent No.
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`6,243,315 From Case No. 4:14-cv-01380 GHM (S.D. Tex.), attached
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`as Exhibit 1017.
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`I.
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`PROFESSIONAL BACKGROUND
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`4.
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`My Curriculum Vitae is attached hereto as Appendix A. I earned a
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`bachelor’s degree in electrical engineering in 1977 from the University of Texas at
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`SMART EXHIBIT - 1002 - PAGE 2
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`ATTORNEY DOCKET NO.: 21584-112006
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`Austin. In 1979 and 1987, respectively, I earned a master of science in electrical
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`engineering and a doctorate degree in computer engineering from the University of
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`Texas at Austin.
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`5.
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`I am currently a professor in the department of Electrical Engineering
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`and Computer Science at the University of California, Irvine – a position I have held
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`since 2003. Previously, from 1987 to 1992, I was an assistant professor in the
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`Department of Electrical & Computer Engineering at the University of California,
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`Irvine. Thereafter, from 1993 to 1997, I was an associate professor in the
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`Department of Electrical & Computer Engineering at the University of California,
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`Irvine. In 1998, I was promoted to Professor and Chair of the Department of
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`Electrical Engineering at the University of California, Irvine. I held that position until
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`2003, when I assumed my current role with the Department. I was elected as an
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`IEEE Fellow in 2014.
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`6.
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`I have been involved in design and development of digital systems for
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`more than 30 years. While at AT&T Bell Labs in the early 1980’s, I worked on an
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`interface card for T1 lines as part of a support R&D team for the design of the first
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`#5ESS digital switches. I was responsible for design of the hardware and software of
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`this board which included memory devices (EEPROM, DRAM, and SRAM).
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`7.
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`Since joining University of California, Irvine in 1987, I have been
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`teaching, researching, and consulting regarding almost all aspects of memory design
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`SMART EXHIBIT - 1002 - PAGE 3
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`for high performance computer systems, including but not limited to DRAMs and
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`SRAMs. In 2000, I became a cofounder of a high tech company called Morpho
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`Technologies, which was focused on the design and development of low power and
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`high performance digital signal processors for mobile applications. As part of my
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`duties as the chief technologist for the company, I evaluated patents, technical reports
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`and presentations related to memory chip designs, DSPs, and parallel processing
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`algorithms for mobile platforms.
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`8.
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`For the Morpho project, I designed, developed and tested the key
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`memory block responsible for exchanging data between the host processor and the
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`slave processor (array processor). This subcomponent was designed to meet the
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`power and performance requirements of the architecture for mobile embedded
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`applications. I also designed the main data storage of the microcontroller (Tiny RISC)
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`that was used for storing temporary data, as is the case for synchronous random
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`access memory (SRAM), which is a type of volatile memory. I was a primary
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`contributor for the prototype board design for the Morpho device, which was
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`integrated with DRAMs, FPGA, and other prototype board components.
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`9.
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`As part of my teaching and research experience, I was responsible for
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`developing circuits, electronic modules, and related architectures for memory systems.
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`For the multithreaded superscalar DSP that was developed at UCI, I designed the
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`memory block responsible for managing out-of-order execution of data registers
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`SMART EXHIBIT - 1002 - PAGE 4
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`ATTORNEY DOCKET NO.: 21584-112006
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`corresponding to different threads. I also designed the original temporary data
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`storage subcomponents for the VLIW processor, ViPER, and for the original Tiny
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`RISC processor. I have done extensive work on the design of efficient data
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`correction schemes for NAND flash memory circuits.
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`II.
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`RELEVANT LEGAL STANDARDS
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`10.
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`I have been asked to provide my opinion as to whether the prior art I
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`reviewed would render Claims 1, 5, 10, and 16 of the ‘315 patent anticipated or
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`obvious to a person of ordinary skill in the art at the time of the alleged invention.
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`11. My background and training is in engineering. The opinions I am
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`expressing in this declaration involve the application of my engineering knowledge
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`and experience to the evaluation of certain prior art with respect to the ‘315 patent.
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`Given that I have a lay person’s knowledge of patent law, I have requested the
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`attorneys from King & Spalding, who represent SMART, to provide me with
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`guidance as to the applicable patent law in this matter. The paragraphs below express
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`my understanding of how I must apply current principles related to patent validity to
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`my analysis.
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`12.
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`It is my understanding that in Inter Partes review, the Patent Office must
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`construe the claim by giving the claim its broadest reasonable interpretation consistent
`
`with the specification.
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`13.
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`It is my understanding that a claim is obvious under 35 U.S.C. § 103 if
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`SMART EXHIBIT - 1002 - PAGE 5
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`the differences between the invention and the prior art are such that the subject
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`matter as a whole would have been obvious to a person of ordinary skill in the art at
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`the time of the alleged invention. It is also my understanding that an obviousness
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`analysis takes into account the scope and content of the prior art, the differences
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`between the claimed subject matter and the prior art, and the level of ordinary skill in
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`the art at the time of the invention.
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`14.
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`It is my understanding that to assess the differences between prior art
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`and the claimed subject matter, 35 U.S.C. § 103 requires the claimed invention to be
`
`considered as a whole. This “as a whole” assessment requires showing that one of
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`ordinary skill in the art at the time of invention, confronted by the same problems as
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`the inventor and with no knowledge of the claimed invention, would have selected the
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`elements from the prior art and combined them in the claimed manner.
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`15.
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`It is my understanding that in determining the scope and content of the
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`prior art, a reference is considered appropriate prior art if it falls within the field of the
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`inventor’s endeavor. In addition, a reference is prior art if it is reasonably pertinent to
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`the particular problem with which the inventor was involved. A reference is
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`reasonably pertinent if it logically would have commended itself to an inventor’s
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`attention in considering his problem. If a reference relates to the same problem as the
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`claimed invention, that supports use of the reference as prior art in an obviousness
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`analysis.
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`SMART EXHIBIT - 1002 - PAGE 6
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`16.
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`It is also my understanding that there are several specifically recognized
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`
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`rationales for combining references or modifying a reference to show obviousness of
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`claimed subject matter. Some of these rationales include: combining prior art
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`elements according to known methods to yield predictable results; simple substitution
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`of one known element for another to obtain predictable results; a predictable use of
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`prior art elements according to their established functions; applying a known
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`technique to a known device (method or product) ready for improvement to yield
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`predictable results; choosing from a finite number of identified, predictable solutions,
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`with a reasonable expectation of success; and some teaching, suggestion, or
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`motivation in the prior art that would have led one of ordinary skill to modify the
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`prior art reference or to combine prior art reference teachings to arrive at the claimed
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`invention. It is also my understanding this list is not exhaustive.
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`III. PERSON OF ORDINARY SKILL IN THE ART
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`17.
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`It is my understanding that when interpreting the claims of the ‘315
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`patent, I must do so based on the perspective of one of ordinary skill in the art at the
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`relevant prior date. My understanding is that the earliest alleged priority date of the
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`‘315 patent is December 31, 1999.
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`18. The ‘315 patent relates to a volatile memory system with data retention
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`capabilities in low power situations. Specifically, as stated in the Abstract of ‘315
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`patent, it pertains to a volatile solid state memory devices that retain information
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`SMART EXHIBIT - 1002 - PAGE 7
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`when an electrical power source is applied to the memory devices within a
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`predetermined voltage range.
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`19.
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`Volatile memory systems typically include only volatile memory devices,
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`such as dynamic random-access memories (DRAM) that are subject to loss of data in
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`the absence of electrical power. Such volatile memory devices, however, typically
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`include a self-refresh mode that requires lower electrical power than during normal
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`operations.
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`20.
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`Further, volatile memory devices are typically configured to interface
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`with a memory controller of a host computer system for regular operation. Once
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`connected with the memory controller of the computer system the volatile memory
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`devices receive power for operation and instructions for various computing processes.
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`21.
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`In my opinion, a person of ordinary skill in the art for the ‘315 patent in
`
`December, 1999, would have a bachelor’s degree in electrical, electronics, computer
`
`engineering, or a related discipline; or the equivalent training or experience in
`
`electrical, electronics, computer engineering, or a related discipline. The person would
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`also have an additional two or more years of experience in computer hardware,
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`including the use of computer memory.
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`22.
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`A person having a bachelor’s degree in electrical, electronics, computer
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`engineering, or a related discipline would have experience with memories and
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`computer architecture. The additional two or more years of experience in experience
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`SMART EXHIBIT - 1002 - PAGE 8
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`in computer systems, circuits, electronics, or a related disciple would provide practical
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`ATTORNEY DOCKET NO.: 21584-112006
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`experience required to address issues such as low power backup for volatile memories.
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`23. The curriculum of a bachelor’s degree program in computer, electronics,
`
`or a related discipline typically includes courses pertaining to circuit design from
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`component parts, including building complex systems from basic building blocks, and
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`interconnecting digital elements and circuit elements. Such courses also include
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`design for electronic memory components. For example, the bachelor’s degree
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`program in electrical and computer engineering at Carnegie Mellon University
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`includes the following course requirements:
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` Building Complex Systems from Basic Building Blocks
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` Interconnecting digital elements
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` Interconnecting circuit elements . . .
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` Dealing with the system: memory, programmed, and hardwired control.
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`Ex. 1014, pp. 1255-56 & Table 2. With an additional 2 or more years of experience in
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`memory related circuits, a POSITA would have the prerequisite skill to take the
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`memory controller from Qureshi and connect it to the SDRAM of Schaefer, and
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`further to support Qureshi and Schaefer with the secondary power supply features of
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`Mazur.
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`24.
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`In my experience, this bachelor’s degree program is not unique to
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`Carnegie Mellon University. Many other universities offer similar courses and
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`SMART EXHIBIT - 1002 - PAGE 9
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`
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`programs of study at the bachelor’s level for electrical, electronics, and computer
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`engineering, or a related discipline,
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`25. A POSITA, with this level of experience, would be capable of reading
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`and understanding the open literature (including patents) related to DRAM system
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`design and would be able to modify an existing process based on the teachings found
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`in the literature. The POSITA would also be familiar with industry standards,
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`including the JEDEC standards.
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`IV. SUMMARY OF PRIOR ART
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`26. Volatile memories, such as dynamic random-access memory (DRAM)
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`and its synchronous variant subset, the SDRAM, have included self-refresh modes at
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`least since 1993, as illustrated in the datasheets from Micron Semiconductor Inc.’s
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`SDRAM chip MT48LC2M8S1 (Exhibits 1009 and 1010). For example, Exhibit 1010
`
`is a May, 1993, specification sheet for this DRAM chip and includes a block diagram
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`illustrating a “self-refresh oscillator and timer.” The self-refresh oscillator and timer
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`provides internally generated signals to the chip during the self-refresh mode. Exhibit
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`1009 is an April, 1994, datasheet that pertains to the same chip and discloses that
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`“[t]he synchronous DRAM allows. . . SELF REFRESH (for low-power, data-
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`retention operation).” Ex. 1009, p. 2--3 (emphasis in original).
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`27. During the self-refresh mode, the power consumption is reduced in
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`comparison to the normal operation of the SDRAM, as described above, with respect
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`SMART EXHIBIT - 1002 - PAGE 10
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`to the Micron datasheet (Ex. 1009). Id.
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`28.
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`As “refresh” is a low-power operation, a secondary power source may
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`provide the low-power required for operation. The secondary power source may be a
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`temporary power source. The use of a secondary power source for providing
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`temporary low-power during refresh modes for DRAM was well-known in the art
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`since at least May 8, 1975, as illustrated in U.S. Patent No. 4,005,395 to Fosler, Jr. et
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`al. (Ex. 1013). For example, Fosler discloses “[d]ynamic memory devices [that] are
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`commercially available as MOS random access memory (RAM) devices” configured
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`so that “[d]uring the refresh address mode, should the high power [be lost], low
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`power output . . . will be sufficient to generate a refresh signal.” Fosler 2:35-38 and
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`4:49-56. Fosler specifically discloses that “when operating from standby power there
`
`is very little drain on the battery or always-on power source.” Id., 5:31-35.
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`A.
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`Schaefer
`
`29.
`
`Schaefer (Ex. 1004) is assigned to Micron Technology Inc. and issued on
`
`February 4, 1997. Schaefer discloses an SDRAM chip that includes a low power self-
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`refresh mode to retain data, when there is a reduction in normal power supply.
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`Specifically, Schaefer explains that a low power self-refresh mode is in an SDRAM
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`chip (e.g., Micron’s MT48LC2M8S1 SDRAM chip), in which the amount of electrical
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`energy drawn from the computer system is reduced. Id. 3:58-61, 6:56-58, & 3:21-26.
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`Schaefer expressly incorporates the Functional Specification of Micron’s
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`MT48LC2M8S1 SDRAM chip into its specification. Id., 3:3-8. It is my opinion that
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`the “Functional Specification” in Schaefer refers to the datasheet and the specification
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`sheet for the MT48LC2M8S1 SDRAM chip, which is included as Exs. 1009 and 1010.
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`I also understand that “incorporation by reference” is a term of art that means that
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`the entire disclosure of the datasheet and specification sheet are part of the
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`specification of Schaefer.
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`30.
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`The Joint Electron Device Engineering Council (JEDEC) is an
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`independent semiconductor engineering standardization body that was founded in
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`1958. JEDEC issued and continues to issue industry-recognized standards for most
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`memory devices in the market today. For example, JEDEC standards are available
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`for SDRAM memory devices and their variations since at least June 2000. Exs.
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`DDR, DDR2 and DDR3. All DDR standards, including DDR2, DDR3, and DDR4
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`are JEDEC DRAM memory standards. For example, JEDEC’s JESD79-2F standard
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`document is titled “DDR2 SDRAM SPECIFICATION” (Ex. 1008 ), while JEDEC’s
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`JESD79-3E standard document is titled “DDR3 SDRAM SPECIFICATION” ( Ex.
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`1012). Also, Exs. 1003, 1; 1016, 3:¶10; & 1017:2.
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`31.
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`Fig. 1 of Schaefer is a functional block diagram of Micron’s
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`MT48LC2M8S1 SDRAM chip, which is similar to the block diagram established
`
`under the JEDEC SDRAM standards. Annotated Fig. 1 of Schaefer is below:
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`Schaefer, Fig. 1.
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`An annotated block diagram from JEDEC SDRAM is below:
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`Ex. 1007 (JEDEC SDRAM Std.), page 4. The similarities include
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` the existence of multiple “banks” of memory in both, Schaefer and the
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`JEDEC specification;
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` access control components – illustrated as the “control logic” in JEDEC
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`and the command controller in Schaefer;
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` address and control signals generated by the respective logic in JEDEC and
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`Schaefer; and
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` refresh components – common to both.
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`32.
`
`The functional diagram in Schaefer is representative of the Micron
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`SDRAM block diagram (Ex. 1009), which was incorporated by reference in Schaefer
`
`and reproduced below.
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`33.
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`The Micron datasheet also states that the MT48LC2M8S1 SDRAM chip
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`of Schaefer “meets all JEDEC functional specifications.” Id. at 2-3. Since the
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`datasheet of the MT48LC2M8S1 SDRAM chip is incorporated by reference into
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`Schaefer and the functional block diagrams are similar, a POSITA would understand
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`that the SDRAM of Schaefer is, therefore, a JEDEC-compliant DRAM.
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`B. Qureshi
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`34. Qureshi (Ex. 1005) is assigned to Samsung and issued on August 11,
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`1998. Qureshi teaches a memory controller for SDRAM chips, such as the Micron
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`SDRAM chip described in Schaefer. Qureshi’s memory controller is a test controller
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`that is configured to place a connected SDRAM chip into a low power self-refresh
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`mode to retain the existing data. Qureshi, Abstract.
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`C. Mazur
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`35. Mazur (1006) issued on April 20, 1993. Mazur teaches the use of a
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`battery as an alternative low power source (e.g., a rechargeable battery”) to drive a
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`DRAM device in a low power refresh mode. For example, Mazur discloses “methods
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`[to] back up the dynamic RAM memory of the associated computer system in the
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`event of a power loss or outage.” Mazur, 2:24-26. Mazur discloses corresponding
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`hardware that includes “a power loss detection circuit, an independent power supply,
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`a continuously rechargeable battery which is recharged by the independent power
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`supply, a standby refresh circuit, a switch-over circuit, address and data busses, and an
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`address control circuit, all of which are in addition to and augment the existing
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`conventional computer circuits.” Id., 2:6-14.
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`V.
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`CLAIM CONSTRUCTION
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`36.
`
`I have reviewed the claim terms and proposed claim constructions set
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`forth in the Petition, and copied in Paragraphs 36 - 42 below. I have used and applied
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`these constructions in my invalidity analysis set forth in Section VI below.
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`37.
`
`The broadest reasonable interpretation of the term “[a] memory system
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`for use in a computer system” in Claims 1 and 10 should at least be
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`a JEDEC-compliant system with memory devices connected to a memory
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`controller.
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`This interpretation is consistent with the specification and extrinsic evidence
`
`advanced by patent owner, because they disclose that the term is synonymous with a
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`JEDEC-complaint system that includes memory devices connected to a memory
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`controller. See, e.g., ‘315 patent, 5:41-48. Patent Owner’s statement, in concurrent
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`litigation, is that the “memory system” should be construed to include
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`DDR2, DDR3, and DDR4 [memory devices that] comply with the
`respective JEDEC Specifications [and that are subjected to] tests [by
`a control device for] the respective memory products.
`
`Ex. 1003, 2 & 4 (emphasis added) and Ex. 1017, 4, 8 & 12 (stating that each of DDR
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`2, 3 & 4 standards are “within the scope of the preamble” during testing). I have
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`applied this interpretation, based on patent owner’s construction, in my analysis of the
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`claims in the subsequent sections and the attached claim charts.
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`38.
`
`The broadest reasonable interpretation of the term a “plurality of volatile
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`SMART EXHIBIT - 1002 - PAGE 16
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`
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`solid state memory devices” in Claims 1 and 10 should at least be:
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`more than one bank of JEDEC-compliant memory.
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`This interpretation is consistent with the specification and extrinsic evidence
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`advanced by patent owner, because they disclose that the term is synonymous with a
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`JEDEC-complaint memory including more than one bank. See, e.g., 5:41-48 and 10:6-
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`9 of the ‘315 patent, which explains that bank selection is enabled using two write
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`enable signals, each corresponding to a bank:
`
` A logic HIGH on /WE dictates the READ from memory mode while a
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`logic LOW on /WE dictates the WRITE to memory mode.
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`10:6-9. See also Fig. 5I. Patent Owner’s statement, in concurrent litigation, is that the
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`“plurality of volatile solid state memory devices” should be construed to include
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`“banks of memory” for DDR2, 3, or 4 type devices, which comply with the
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`respective JEDEC Specifications. Ex. 1003, 2 & 4; Ex. 1017, 5, 8 & 12. I have
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`applied this interpretation, based on patent owner’s construction, in my analysis of the
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`claims in the subsequent sections and the attached claim charts.
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`39. The broadest reasonable interpretation of the term “address lines and
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`control lines” in Claims 1 and 10 should at least be:
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`JEDEC-compliant address and control balls or pins.
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`This interpretation is consistent with the specification and extrinsic evidence
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`advanced by patent owner, because they disclose that the term is synonymous with a
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`SMART EXHIBIT - 1002 - PAGE 17
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`JEDEC-complaint memory that includes address and control pins or balls. See, e.g.,
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`‘315 patent, 9:9-14, which states that the “solid state memory devices [are] in two way
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`communications [using] a standard memory connector . . . such as a 72 PIN SIMM,
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`144 PIN SODIMM, or 168 PIN DIMM connector, all three in accordance with the
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`JEDEC industry standards.” Id., 9:9-14. The ‘315 patent also explains that “[the]
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`address buses [are] in direct communication with memory devices. . . via the address
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`pins of the memory devices” and that “[e]ach DRAM in the configuration has. . .
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`three control signals, /CAS, /RAS and /WE, and eleven address lines labeled A0-
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`A10.” Id., 9:18-20 & 10:65-11:1.
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`Patent Owner’s statement, in
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`concurrent litigation, is that the
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`“plurality of volatile solid state
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`memory devices” should be
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`construed to include the JEDEC standards, for e.g., section 2.3 of DDR2. Ex. 1003,
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`3 & 1017, 14. An excerpt from section 2.3 of DDR2 (reproduced here) illustrates
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`that the JEDEC specification includes control balls or pins (e.g., BA, RAS, CAS,
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`WE) and address balls or pins (e.g., A0-A15) to receive corresponding JEDEC-
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`complaint BA, RAS, CAS, WE, and address signals. Ex. 1008, Section 2.3. I have
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`applied this interpretation, based on patent owner’s construction, in my analysis of the
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`claims in the subsequent sections and the attached claim charts.
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`SMART EXHIBIT - 1002 - PAGE 18
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`40. The broadest reasonable interpretation of the term “a control device for
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`
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`selectively electrically isolating [the] memory devices” (Claim 1, and its variation in
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`Claim 10) should at least be:
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`a memory controller for providing a JEDEC-compliant signal to
`trigger a “don’t care” or inhibit action for the corresponding memory
`devices.
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`This interpretation is consistent with the specification and extrinsic evidence
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`advanced by patent owner, because they disclose that the term is synonymous with a
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`JEDEC-complaint memory system including a controller for providing a JEDEC-
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`compliant signal that triggers a “don’t care” action. See, e.g., ‘315 patent, 5:41-48 and
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`10:24-26, which explains that a “DNC further electrically isolate the DRAMs. . . by
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`inhibiting any responses. . .” The ‘315 patent also states that “[t]he [DNC chip
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`provides control signals, e.g., ] /RASO, /CASO and /WEO, which are inputs to the
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`respective DRAM chip. ” Id., 10:14-16. Also, Fig. 5I.
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`41. A POSITA would understand from this disclosure in the ‘315 patent
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`that the DNC is a controller chip that uses JEDEC-compliant input signals (e.g.,
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`RASO, CASO, and WEO) in such a manner as to “inhibit any responses” from the
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`memory devices. This understanding is supported by the reasoning, based on patent
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`owner’s interpretation, that the DNC chip provides the required signals for the
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`memory device and may, therefore, provide these signals in such a manner as to
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`render the memory device non-responsive to these signals.
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`SMART EXHIBIT - 1002 - PAGE 19
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`42.
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`Patent Owner’s statement, in concurrent litigation, is that “a control
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`device for selectively electrically isolating” should include the JEDEC standards, for
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`e.g., Sections 2.3, 3.10, 3.11, and 4.2 in DDR2. Ex. 1003, 4 & Ex. 1017, 15.
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`Specifically, Patent Owner alleged that the “‘don’t care’ [is] electrically isolating.”
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`Section 3.10 of the JEDEC DDR2 specification (Ex. 1008) describes this function as
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`follows:
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`When the DDR2 SDRAM has entered Self Refresh mode, all of the
`external signals except CKE, are “don’t care.”
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`This establishes to a POSITA that JEDEC-compliant memory devices are configured
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`to enter a “don’t care” state, in which its responses are inhibited by the application of
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`appropriate JEDEC-compliant signals from a controller to the memory devices. This
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`understanding is supported by the reasoning, based on patent owner’s interpretation,
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`that the external signals, when set to “don’t care,” would render the memory device
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`non-responsive, as the applied “don’t care” signals do not require a response. I have
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`applied this interpretation, based on patent owner’s construction, in my analysis of the
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`claims in the subsequent sections, and the attached claim charts.
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`43.
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`The broadest reasonable interpretation of the term a “a low power mode
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`for [the] memory system” in claims 1 and 10 should at least be:
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`a JEDEC-compliant low power mode or ‘power down mode.’
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`This interpretation is consistent with the specification and extrinsic evidence
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`SMART EXHIBIT - 1002 - PAGE 20
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`
`
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`advanced by patent owner’s interpretation, because they disclose that the term is
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`synonymous with a JEDEC-complaint memory including low power mode or ‘power
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`down mode.’ See, e.g., ‘315 patent, 5:41-48 and 5:21-25, which explains that a “low
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`power standby mode,” is a state in which “[the memory device] is in self refresh mode
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`and is unable to respond to memory requests including read and write requests.”
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`Further, the ‘315 patent also provides that the “low power standby mode” is
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`synonymous with a “power down mode.” Id., 5:29-31. Patent Owner’s statement, in
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`concurrent litigation, is that “a low power mode for [the] memory system” should be
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`construed to include the JEDEC standards, for e.g., section 3.11 in DDR2. Ex. 1003,
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`4 & Ex. 1017, 15. Specifically, Patent Owner referenced the “‘Power-Down [mode
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`of DDR 2, which is entered] when there is no read or write operations.” Id. Also, Ex.
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`1008, Section 3.11. I have applied this interpretation, based on patent owner’s
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`construction, in my analysis of the claims in the subsequent sections and the attached
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`claim charts.
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`VI.
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`INVALIDITY REJECTIONS
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`
`
`A.
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`Schaefer In View Of Qureshi Rejections
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`44. When the proposed claim constructions are adopted, each and every
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`limitation of Claims 1 and 5 are disclosed by Schaefer in view of Qureshi. A claim
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`construction that encompasses the JEDEC specification must also encompass the
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`disclosure of Schaefer. This is, at least, because of the structural and functional
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`SMART EXHIBIT - 1002 - PAGE 21
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`
`
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`similarity of the Schaefer memory device and that of the JEDEC specification
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`memory device, as discussed in Section IV(A).
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`
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`1.
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`Obviousness Of Claims 1 and 5
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`45. Claims 1 and 5 of the ‘315 patent are obvious over Schaefer in view of
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`Qureshi. Attached as Appendix B is a claim chart showing how and where each
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`limitation of Claims 1 and 5 is disclosed by Schaefer in view of Qureshi.
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`a. Motivation To Combine And Predictability Of The Art
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`46. A POSITA would be motivated to combine Schaefer with Qureshi,
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`because the functional electronic modules of Schaefer and Qureshi are configured to
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`work together. For example, Schaefer teaches an SDRAM memory (e.g., Micron
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`MT48LC2M8S1 chip) that includes a low power self-refresh mode used to retain data
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`in low power situations (Schaefer, 3:3-6); and Qureshi teaches a memory controller
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`that is configured to place any SDRAM memory into a low power self-refresh mode,
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`for the purposes of data retention during testing (Qureshi, 1:65-2:2).
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`47.
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`Schaefer and Qureshi also disclose that their respective teachings are
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`merely exemplary modules that a POSITA may apply, in a variety of ways, without
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`departing from the scope of their corresponding functions. For example, Schaefer
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`discloses that “those of ordinary skill in the art [would appreciate] that a wide variety
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`of alternate and/or equivalent implementations calculated to achieve the same
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`purposes may be substituted . . . without departing from the scope of the present
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`SMART EXHIBIT - 1002 - PAGE 22
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`invention.” Schaefer, 10:25-33. Qureshi explains that “in accordance with [its]
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`invention, memory such as SDRAMs are put into self refresh mode while JTAG
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`testing is performed.” Qureshi, 1:63-65.
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`48.
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`As Schaefer and Qureshi provide that their respective disclosures are
`
`understood by a POSITA, and may be modified, altered or adapted, while retaining
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`their corresponding expected functions, the prior art teaches that the field of the ‘315
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`patent is very predi