ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SMART MODULAR TECHNOLOGIES INC.
`
`Petitioner
`
`v.
`
`JAMES B. GOODMAN
`
`Patent Owner
`
`Case No. TBD
`
`Patent 6,243,315
`
`DECLARATION OF DR. NADER BAGHERZADEH
`
`UNDER 37 C.F.R. § 1.68
`
`SMART EXHIBIT - 1002
`
`
`Case No. TBD
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SMART MODULAR TECHNOLOGIES INC.
`
`Petitioner
`
`v.
`
`JAMES B. GOODMAN
`
`Patent Owner
`
`Case No. TBD
`
`Patent 6,243,315
`
`DECLARATION OF DR. NADER BAGHERZADEH
`
`UNDER 37 C.F.R. § 1.68
`
`SMART EXHIBIT - 1002
`
`
`
`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
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`I, Nader Bagherzadeh, declare as follows:
`
`1.
`
`I am making this declaration at the request of SMART Modular
`
`Technologies, Inc. in support of SMART’s Inter Partes review of U.S. Patent No.
`
`6,243,315. This declaration includes Appendices A to B.
`
`2.
`
`I am being compensated for my services in this matter at the rate of
`
`$450/hour plus expenses. My compensation is not contingent upon the outcome of
`
`this proceeding.
`
`3.
`
`In preparing this declaration, I considered the following materials:
`
`a.
`
`the ‘315 patent, attached as Exhibit 1001;
`
`b. the ‘315 patent file history;
`
`c. Plaintiff’s Amended Infringement Chart For U.S. Patent No.
`
`6,243,315 From Case No. 4:14-cv-01380 GHM (S.D. Tex.), attached
`
`as Exhibit 1003;
`
`d. U.S. Patent No. 5,600,605 to Schaefer (“Schaefer”), attached as
`
`Exhibit 1004;
`
`e. U.S. Patent No. 5,793,776 to Qureshi et al. (“Qureshi”), attached as
`
`Exhibit 1005;
`
`f. U.S. Patent No. 5,204,840 to Mazur (“Mazur”), attached as Exhibit
`
`1006;
`
`g. JEDEC DDR SDRAM Specification JESD79 R1, June 2000
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`SMART EXHIBIT - 1002 - PAGE 1
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`ATTORNEY DOCKET NO.: 21584-112006
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`(“JESD79”), attached as Exhibit 1007;
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`h. JEDEC DDR2 SDRAM Specification JESD79-2F, November 2009
`
`(“JESD792F”), attached as Exhibit 1008;
`
`i. Micron MT48LC2M8S1(S) Datasheet, April 1994 (“Micron Datasheet),
`
`attached as Exhibit 1009;
`
`j. Micron MT48LC2M8S1(S) Specification Sheet, June 1993 (“Micron
`
`Specs”), attached as Exhibit 1010;
`
`k. JEDEC DDR3 SDRAM Specification JESD79-3E, July 2010
`
`(“JESD793E”), attached as Exhibit 1012;
`
`l. U.S. Patent No. 4,005,395 to Fosler, Jr. et. al. (“Fosler”), attached as
`
`Exhibit 1013;
`
`m. Reengineering the Curriculum: Design and Analysis of a New Undergraduate
`
`Electrical and Computer Engineering Degree at Carnegie Mellon University,
`
`Director et al., IEEE 1995, attached as Exhibit 1014; and
`
`n. Plaintiff’s Second Amended Infringement Chart For U.S. Patent No.
`
`6,243,315 From Case No. 4:14-cv-01380 GHM (S.D. Tex.), attached
`
`as Exhibit 1017.
`
`I.
`
`PROFESSIONAL BACKGROUND
`
`4.
`
`My Curriculum Vitae is attached hereto as Appendix A. I earned a
`
`bachelor’s degree in electrical engineering in 1977 from the University of Texas at
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`SMART EXHIBIT - 1002 - PAGE 2
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`ATTORNEY DOCKET NO.: 21584-112006
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`Austin. In 1979 and 1987, respectively, I earned a master of science in electrical
`
`engineering and a doctorate degree in computer engineering from the University of
`
`Texas at Austin.
`
`5.
`
`I am currently a professor in the department of Electrical Engineering
`
`and Computer Science at the University of California, Irvine – a position I have held
`
`since 2003. Previously, from 1987 to 1992, I was an assistant professor in the
`
`Department of Electrical & Computer Engineering at the University of California,
`
`Irvine. Thereafter, from 1993 to 1997, I was an associate professor in the
`
`Department of Electrical & Computer Engineering at the University of California,
`
`Irvine. In 1998, I was promoted to Professor and Chair of the Department of
`
`Electrical Engineering at the University of California, Irvine. I held that position until
`
`2003, when I assumed my current role with the Department. I was elected as an
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`IEEE Fellow in 2014.
`
`6.
`
`I have been involved in design and development of digital systems for
`
`more than 30 years. While at AT&T Bell Labs in the early 1980’s, I worked on an
`
`interface card for T1 lines as part of a support R&D team for the design of the first
`
`#5ESS digital switches. I was responsible for design of the hardware and software of
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`this board which included memory devices (EEPROM, DRAM, and SRAM).
`
`7.
`
`Since joining University of California, Irvine in 1987, I have been
`
`teaching, researching, and consulting regarding almost all aspects of memory design
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`SMART EXHIBIT - 1002 - PAGE 3
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`ATTORNEY DOCKET NO.: 21584-112006
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`for high performance computer systems, including but not limited to DRAMs and
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`SRAMs. In 2000, I became a cofounder of a high tech company called Morpho
`
`Technologies, which was focused on the design and development of low power and
`
`high performance digital signal processors for mobile applications. As part of my
`
`duties as the chief technologist for the company, I evaluated patents, technical reports
`
`and presentations related to memory chip designs, DSPs, and parallel processing
`
`algorithms for mobile platforms.
`
`8.
`
`For the Morpho project, I designed, developed and tested the key
`
`memory block responsible for exchanging data between the host processor and the
`
`slave processor (array processor). This subcomponent was designed to meet the
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`power and performance requirements of the architecture for mobile embedded
`
`applications. I also designed the main data storage of the microcontroller (Tiny RISC)
`
`that was used for storing temporary data, as is the case for synchronous random
`
`access memory (SRAM), which is a type of volatile memory. I was a primary
`
`contributor for the prototype board design for the Morpho device, which was
`
`integrated with DRAMs, FPGA, and other prototype board components.
`
`9.
`
`As part of my teaching and research experience, I was responsible for
`
`developing circuits, electronic modules, and related architectures for memory systems.
`
`For the multithreaded superscalar DSP that was developed at UCI, I designed the
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`memory block responsible for managing out-of-order execution of data registers
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`SMART EXHIBIT - 1002 - PAGE 4
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`ATTORNEY DOCKET NO.: 21584-112006
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`corresponding to different threads. I also designed the original temporary data
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`storage subcomponents for the VLIW processor, ViPER, and for the original Tiny
`
`RISC processor. I have done extensive work on the design of efficient data
`
`correction schemes for NAND flash memory circuits.
`
`II.
`
`RELEVANT LEGAL STANDARDS
`
`10.
`
`I have been asked to provide my opinion as to whether the prior art I
`
`reviewed would render Claims 1, 5, 10, and 16 of the ‘315 patent anticipated or
`
`obvious to a person of ordinary skill in the art at the time of the alleged invention.
`
`11. My background and training is in engineering. The opinions I am
`
`expressing in this declaration involve the application of my engineering knowledge
`
`and experience to the evaluation of certain prior art with respect to the ‘315 patent.
`
`Given that I have a lay person’s knowledge of patent law, I have requested the
`
`attorneys from King & Spalding, who represent SMART, to provide me with
`
`guidance as to the applicable patent law in this matter. The paragraphs below express
`
`my understanding of how I must apply current principles related to patent validity to
`
`my analysis.
`
`12.
`
`It is my understanding that in Inter Partes review, the Patent Office must
`
`construe the claim by giving the claim its broadest reasonable interpretation consistent
`
`with the specification.
`
`13.
`
`It is my understanding that a claim is obvious under 35 U.S.C. § 103 if
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`SMART EXHIBIT - 1002 - PAGE 5
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`ATTORNEY DOCKET NO.: 21584-112006
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`the differences between the invention and the prior art are such that the subject
`
`matter as a whole would have been obvious to a person of ordinary skill in the art at
`
`the time of the alleged invention. It is also my understanding that an obviousness
`
`analysis takes into account the scope and content of the prior art, the differences
`
`between the claimed subject matter and the prior art, and the level of ordinary skill in
`
`the art at the time of the invention.
`
`14.
`
`It is my understanding that to assess the differences between prior art
`
`and the claimed subject matter, 35 U.S.C. § 103 requires the claimed invention to be
`
`considered as a whole. This “as a whole” assessment requires showing that one of
`
`ordinary skill in the art at the time of invention, confronted by the same problems as
`
`the inventor and with no knowledge of the claimed invention, would have selected the
`
`elements from the prior art and combined them in the claimed manner.
`
`15.
`
`It is my understanding that in determining the scope and content of the
`
`prior art, a reference is considered appropriate prior art if it falls within the field of the
`
`inventor’s endeavor. In addition, a reference is prior art if it is reasonably pertinent to
`
`the particular problem with which the inventor was involved. A reference is
`
`reasonably pertinent if it logically would have commended itself to an inventor’s
`
`attention in considering his problem. If a reference relates to the same problem as the
`
`claimed invention, that supports use of the reference as prior art in an obviousness
`
`analysis.
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`SMART EXHIBIT - 1002 - PAGE 6
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`ATTORNEY DOCKET NO.: 21584-112006
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`16.
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`It is also my understanding that there are several specifically recognized
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`
`
`rationales for combining references or modifying a reference to show obviousness of
`
`claimed subject matter. Some of these rationales include: combining prior art
`
`elements according to known methods to yield predictable results; simple substitution
`
`of one known element for another to obtain predictable results; a predictable use of
`
`prior art elements according to their established functions; applying a known
`
`technique to a known device (method or product) ready for improvement to yield
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`predictable results; choosing from a finite number of identified, predictable solutions,
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`with a reasonable expectation of success; and some teaching, suggestion, or
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`motivation in the prior art that would have led one of ordinary skill to modify the
`
`prior art reference or to combine prior art reference teachings to arrive at the claimed
`
`invention. It is also my understanding this list is not exhaustive.
`
`III. PERSON OF ORDINARY SKILL IN THE ART
`
`17.
`
`It is my understanding that when interpreting the claims of the ‘315
`
`patent, I must do so based on the perspective of one of ordinary skill in the art at the
`
`relevant prior date. My understanding is that the earliest alleged priority date of the
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`‘315 patent is December 31, 1999.
`
`18. The ‘315 patent relates to a volatile memory system with data retention
`
`capabilities in low power situations. Specifically, as stated in the Abstract of ‘315
`
`patent, it pertains to a volatile solid state memory devices that retain information
`
`
`
`
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`SMART EXHIBIT - 1002 - PAGE 7
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`when an electrical power source is applied to the memory devices within a
`
`predetermined voltage range.
`
`19.
`
`Volatile memory systems typically include only volatile memory devices,
`
`such as dynamic random-access memories (DRAM) that are subject to loss of data in
`
`the absence of electrical power. Such volatile memory devices, however, typically
`
`include a self-refresh mode that requires lower electrical power than during normal
`
`operations.
`
`20.
`
`Further, volatile memory devices are typically configured to interface
`
`with a memory controller of a host computer system for regular operation. Once
`
`connected with the memory controller of the computer system the volatile memory
`
`devices receive power for operation and instructions for various computing processes.
`
`21.
`
`In my opinion, a person of ordinary skill in the art for the ‘315 patent in
`
`December, 1999, would have a bachelor’s degree in electrical, electronics, computer
`
`engineering, or a related discipline; or the equivalent training or experience in
`
`electrical, electronics, computer engineering, or a related discipline. The person would
`
`also have an additional two or more years of experience in computer hardware,
`
`including the use of computer memory.
`
`22.
`
`A person having a bachelor’s degree in electrical, electronics, computer
`
`engineering, or a related discipline would have experience with memories and
`
`computer architecture. The additional two or more years of experience in experience
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`SMART EXHIBIT - 1002 - PAGE 8
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`
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`in computer systems, circuits, electronics, or a related disciple would provide practical
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`ATTORNEY DOCKET NO.: 21584-112006
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`experience required to address issues such as low power backup for volatile memories.
`
`23. The curriculum of a bachelor’s degree program in computer, electronics,
`
`or a related discipline typically includes courses pertaining to circuit design from
`
`component parts, including building complex systems from basic building blocks, and
`
`interconnecting digital elements and circuit elements. Such courses also include
`
`design for electronic memory components. For example, the bachelor’s degree
`
`program in electrical and computer engineering at Carnegie Mellon University
`
`includes the following course requirements:
`
` Building Complex Systems from Basic Building Blocks
`
` Interconnecting digital elements
`
` Interconnecting circuit elements . . .
`
` Dealing with the system: memory, programmed, and hardwired control.
`
`Ex. 1014, pp. 1255-56 & Table 2. With an additional 2 or more years of experience in
`
`memory related circuits, a POSITA would have the prerequisite skill to take the
`
`memory controller from Qureshi and connect it to the SDRAM of Schaefer, and
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`further to support Qureshi and Schaefer with the secondary power supply features of
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`Mazur.
`
`24.
`
`In my experience, this bachelor’s degree program is not unique to
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`Carnegie Mellon University. Many other universities offer similar courses and
`
`
`
`
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`SMART EXHIBIT - 1002 - PAGE 9
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`
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`programs of study at the bachelor’s level for electrical, electronics, and computer
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`ATTORNEY DOCKET NO.: 21584-112006
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`engineering, or a related discipline,
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`25. A POSITA, with this level of experience, would be capable of reading
`
`and understanding the open literature (including patents) related to DRAM system
`
`design and would be able to modify an existing process based on the teachings found
`
`in the literature. The POSITA would also be familiar with industry standards,
`
`including the JEDEC standards.
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`IV. SUMMARY OF PRIOR ART
`
`26. Volatile memories, such as dynamic random-access memory (DRAM)
`
`and its synchronous variant subset, the SDRAM, have included self-refresh modes at
`
`least since 1993, as illustrated in the datasheets from Micron Semiconductor Inc.’s
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`SDRAM chip MT48LC2M8S1 (Exhibits 1009 and 1010). For example, Exhibit 1010
`
`is a May, 1993, specification sheet for this DRAM chip and includes a block diagram
`
`illustrating a “self-refresh oscillator and timer.” The self-refresh oscillator and timer
`
`provides internally generated signals to the chip during the self-refresh mode. Exhibit
`
`1009 is an April, 1994, datasheet that pertains to the same chip and discloses that
`
`“[t]he synchronous DRAM allows. . . SELF REFRESH (for low-power, data-
`
`retention operation).” Ex. 1009, p. 2--3 (emphasis in original).
`
`27. During the self-refresh mode, the power consumption is reduced in
`
`comparison to the normal operation of the SDRAM, as described above, with respect
`
`
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`SMART EXHIBIT - 1002 - PAGE 10
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`ATTORNEY DOCKET NO.: 21584-112006
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`to the Micron datasheet (Ex. 1009). Id.
`
`28.
`
`As “refresh” is a low-power operation, a secondary power source may
`
`provide the low-power required for operation. The secondary power source may be a
`
`temporary power source. The use of a secondary power source for providing
`
`temporary low-power during refresh modes for DRAM was well-known in the art
`
`since at least May 8, 1975, as illustrated in U.S. Patent No. 4,005,395 to Fosler, Jr. et
`
`al. (Ex. 1013). For example, Fosler discloses “[d]ynamic memory devices [that] are
`
`commercially available as MOS random access memory (RAM) devices” configured
`
`so that “[d]uring the refresh address mode, should the high power [be lost], low
`
`power output . . . will be sufficient to generate a refresh signal.” Fosler 2:35-38 and
`
`4:49-56. Fosler specifically discloses that “when operating from standby power there
`
`is very little drain on the battery or always-on power source.” Id., 5:31-35.
`
`A.
`
`Schaefer
`
`29.
`
`Schaefer (Ex. 1004) is assigned to Micron Technology Inc. and issued on
`
`February 4, 1997. Schaefer discloses an SDRAM chip that includes a low power self-
`
`refresh mode to retain data, when there is a reduction in normal power supply.
`
`Specifically, Schaefer explains that a low power self-refresh mode is in an SDRAM
`
`chip (e.g., Micron’s MT48LC2M8S1 SDRAM chip), in which the amount of electrical
`
`energy drawn from the computer system is reduced. Id. 3:58-61, 6:56-58, & 3:21-26.
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`Schaefer expressly incorporates the Functional Specification of Micron’s
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`MT48LC2M8S1 SDRAM chip into its specification. Id., 3:3-8. It is my opinion that
`
`the “Functional Specification” in Schaefer refers to the datasheet and the specification
`
`sheet for the MT48LC2M8S1 SDRAM chip, which is included as Exs. 1009 and 1010.
`
`I also understand that “incorporation by reference” is a term of art that means that
`
`the entire disclosure of the datasheet and specification sheet are part of the
`
`specification of Schaefer.
`
`30.
`
`The Joint Electron Device Engineering Council (JEDEC) is an
`
`independent semiconductor engineering standardization body that was founded in
`
`1958. JEDEC issued and continues to issue industry-recognized standards for most
`
`memory devices in the market today. For example, JEDEC standards are available
`
`for SDRAM memory devices and their variations since at least June 2000. Exs.
`
`DDR, DDR2 and DDR3. All DDR standards, including DDR2, DDR3, and DDR4
`
`are JEDEC DRAM memory standards. For example, JEDEC’s JESD79-2F standard
`
`document is titled “DDR2 SDRAM SPECIFICATION” (Ex. 1008 ), while JEDEC’s
`
`JESD79-3E standard document is titled “DDR3 SDRAM SPECIFICATION” ( Ex.
`
`1012). Also, Exs. 1003, 1; 1016, 3:¶10; & 1017:2.
`
`31.
`
`Fig. 1 of Schaefer is a functional block diagram of Micron’s
`
`MT48LC2M8S1 SDRAM chip, which is similar to the block diagram established
`
`under the JEDEC SDRAM standards. Annotated Fig. 1 of Schaefer is below:
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`SMART EXHIBIT - 1002 - PAGE 12
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`Schaefer, Fig. 1.
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`An annotated block diagram from JEDEC SDRAM is below:
`
`Ex. 1007 (JEDEC SDRAM Std.), page 4. The similarities include
`
` the existence of multiple “banks” of memory in both, Schaefer and the
`
`
`
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`JEDEC specification;
`
` access control components – illustrated as the “control logic” in JEDEC
`
`and the command controller in Schaefer;
`
` address and control signals generated by the respective logic in JEDEC and
`
`Schaefer; and
`
` refresh components – common to both.
`
`32.
`
`The functional diagram in Schaefer is representative of the Micron
`
`SDRAM block diagram (Ex. 1009), which was incorporated by reference in Schaefer
`
`and reproduced below.
`
`33.
`
`The Micron datasheet also states that the MT48LC2M8S1 SDRAM chip
`
`of Schaefer “meets all JEDEC functional specifications.” Id. at 2-3. Since the
`
`datasheet of the MT48LC2M8S1 SDRAM chip is incorporated by reference into
`
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`Schaefer and the functional block diagrams are similar, a POSITA would understand
`
`that the SDRAM of Schaefer is, therefore, a JEDEC-compliant DRAM.
`
`B. Qureshi
`
`34. Qureshi (Ex. 1005) is assigned to Samsung and issued on August 11,
`
`1998. Qureshi teaches a memory controller for SDRAM chips, such as the Micron
`
`SDRAM chip described in Schaefer. Qureshi’s memory controller is a test controller
`
`that is configured to place a connected SDRAM chip into a low power self-refresh
`
`mode to retain the existing data. Qureshi, Abstract.
`
`C. Mazur
`
`35. Mazur (1006) issued on April 20, 1993. Mazur teaches the use of a
`
`battery as an alternative low power source (e.g., a rechargeable battery”) to drive a
`
`DRAM device in a low power refresh mode. For example, Mazur discloses “methods
`
`[to] back up the dynamic RAM memory of the associated computer system in the
`
`event of a power loss or outage.” Mazur, 2:24-26. Mazur discloses corresponding
`
`hardware that includes “a power loss detection circuit, an independent power supply,
`
`a continuously rechargeable battery which is recharged by the independent power
`
`supply, a standby refresh circuit, a switch-over circuit, address and data busses, and an
`
`address control circuit, all of which are in addition to and augment the existing
`
`conventional computer circuits.” Id., 2:6-14.
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`V.
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`CLAIM CONSTRUCTION
`
`36.
`
`I have reviewed the claim terms and proposed claim constructions set
`
`forth in the Petition, and copied in Paragraphs 36 - 42 below. I have used and applied
`
`these constructions in my invalidity analysis set forth in Section VI below.
`
`37.
`
`The broadest reasonable interpretation of the term “[a] memory system
`
`for use in a computer system” in Claims 1 and 10 should at least be
`
`a JEDEC-compliant system with memory devices connected to a memory
`
`controller.
`
`This interpretation is consistent with the specification and extrinsic evidence
`
`advanced by patent owner, because they disclose that the term is synonymous with a
`
`JEDEC-complaint system that includes memory devices connected to a memory
`
`controller. See, e.g., ‘315 patent, 5:41-48. Patent Owner’s statement, in concurrent
`
`litigation, is that the “memory system” should be construed to include
`
`DDR2, DDR3, and DDR4 [memory devices that] comply with the
`respective JEDEC Specifications [and that are subjected to] tests [by
`a control device for] the respective memory products.
`
`Ex. 1003, 2 & 4 (emphasis added) and Ex. 1017, 4, 8 & 12 (stating that each of DDR
`
`2, 3 & 4 standards are “within the scope of the preamble” during testing). I have
`
`applied this interpretation, based on patent owner’s construction, in my analysis of the
`
`claims in the subsequent sections and the attached claim charts.
`
`38.
`
`The broadest reasonable interpretation of the term a “plurality of volatile
`
`SMART EXHIBIT - 1002 - PAGE 16
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`
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`solid state memory devices” in Claims 1 and 10 should at least be:
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`more than one bank of JEDEC-compliant memory.
`
`This interpretation is consistent with the specification and extrinsic evidence
`
`advanced by patent owner, because they disclose that the term is synonymous with a
`
`JEDEC-complaint memory including more than one bank. See, e.g., 5:41-48 and 10:6-
`
`9 of the ‘315 patent, which explains that bank selection is enabled using two write
`
`enable signals, each corresponding to a bank:
`
` A logic HIGH on /WE dictates the READ from memory mode while a
`
`logic LOW on /WE dictates the WRITE to memory mode.
`
`10:6-9. See also Fig. 5I. Patent Owner’s statement, in concurrent litigation, is that the
`
`“plurality of volatile solid state memory devices” should be construed to include
`
`“banks of memory” for DDR2, 3, or 4 type devices, which comply with the
`
`respective JEDEC Specifications. Ex. 1003, 2 & 4; Ex. 1017, 5, 8 & 12. I have
`
`applied this interpretation, based on patent owner’s construction, in my analysis of the
`
`claims in the subsequent sections and the attached claim charts.
`
`39. The broadest reasonable interpretation of the term “address lines and
`
`control lines” in Claims 1 and 10 should at least be:
`
`JEDEC-compliant address and control balls or pins.
`
`This interpretation is consistent with the specification and extrinsic evidence
`
`advanced by patent owner, because they disclose that the term is synonymous with a
`
`
`
`
`
`SMART EXHIBIT - 1002 - PAGE 17
`
`
`
`
`JEDEC-complaint memory that includes address and control pins or balls. See, e.g.,
`
`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
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`‘315 patent, 9:9-14, which states that the “solid state memory devices [are] in two way
`
`communications [using] a standard memory connector . . . such as a 72 PIN SIMM,
`
`144 PIN SODIMM, or 168 PIN DIMM connector, all three in accordance with the
`
`JEDEC industry standards.” Id., 9:9-14. The ‘315 patent also explains that “[the]
`
`address buses [are] in direct communication with memory devices. . . via the address
`
`pins of the memory devices” and that “[e]ach DRAM in the configuration has. . .
`
`three control signals, /CAS, /RAS and /WE, and eleven address lines labeled A0-
`
`A10.” Id., 9:18-20 & 10:65-11:1.
`
`Patent Owner’s statement, in
`
`concurrent litigation, is that the
`
`“plurality of volatile solid state
`
`memory devices” should be
`
`construed to include the JEDEC standards, for e.g., section 2.3 of DDR2. Ex. 1003,
`
`3 & 1017, 14. An excerpt from section 2.3 of DDR2 (reproduced here) illustrates
`
`that the JEDEC specification includes control balls or pins (e.g., BA, RAS, CAS,
`
`WE) and address balls or pins (e.g., A0-A15) to receive corresponding JEDEC-
`
`complaint BA, RAS, CAS, WE, and address signals. Ex. 1008, Section 2.3. I have
`
`applied this interpretation, based on patent owner’s construction, in my analysis of the
`
`claims in the subsequent sections and the attached claim charts.
`
`
`
`
`
`SMART EXHIBIT - 1002 - PAGE 18
`
`
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`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
`
`40. The broadest reasonable interpretation of the term “a control device for
`
`
`
`selectively electrically isolating [the] memory devices” (Claim 1, and its variation in
`
`Claim 10) should at least be:
`
`a memory controller for providing a JEDEC-compliant signal to
`trigger a “don’t care” or inhibit action for the corresponding memory
`devices.
`
`This interpretation is consistent with the specification and extrinsic evidence
`
`advanced by patent owner, because they disclose that the term is synonymous with a
`
`JEDEC-complaint memory system including a controller for providing a JEDEC-
`
`compliant signal that triggers a “don’t care” action. See, e.g., ‘315 patent, 5:41-48 and
`
`10:24-26, which explains that a “DNC further electrically isolate the DRAMs. . . by
`
`inhibiting any responses. . .” The ‘315 patent also states that “[t]he [DNC chip
`
`provides control signals, e.g., ] /RASO, /CASO and /WEO, which are inputs to the
`
`respective DRAM chip. ” Id., 10:14-16. Also, Fig. 5I.
`
`41. A POSITA would understand from this disclosure in the ‘315 patent
`
`that the DNC is a controller chip that uses JEDEC-compliant input signals (e.g.,
`
`RASO, CASO, and WEO) in such a manner as to “inhibit any responses” from the
`
`memory devices. This understanding is supported by the reasoning, based on patent
`
`owner’s interpretation, that the DNC chip provides the required signals for the
`
`memory device and may, therefore, provide these signals in such a manner as to
`
`render the memory device non-responsive to these signals.
`
`
`
`
`
`SMART EXHIBIT - 1002 - PAGE 19
`
`
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`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
`
`42.
`
`Patent Owner’s statement, in concurrent litigation, is that “a control
`
`device for selectively electrically isolating” should include the JEDEC standards, for
`
`e.g., Sections 2.3, 3.10, 3.11, and 4.2 in DDR2. Ex. 1003, 4 & Ex. 1017, 15.
`
`Specifically, Patent Owner alleged that the “‘don’t care’ [is] electrically isolating.”
`
`Section 3.10 of the JEDEC DDR2 specification (Ex. 1008) describes this function as
`
`follows:
`
`When the DDR2 SDRAM has entered Self Refresh mode, all of the
`external signals except CKE, are “don’t care.”
`
`This establishes to a POSITA that JEDEC-compliant memory devices are configured
`
`to enter a “don’t care” state, in which its responses are inhibited by the application of
`
`appropriate JEDEC-compliant signals from a controller to the memory devices. This
`
`understanding is supported by the reasoning, based on patent owner’s interpretation,
`
`that the external signals, when set to “don’t care,” would render the memory device
`
`non-responsive, as the applied “don’t care” signals do not require a response. I have
`
`applied this interpretation, based on patent owner’s construction, in my analysis of the
`
`claims in the subsequent sections, and the attached claim charts.
`
`43.
`
`The broadest reasonable interpretation of the term a “a low power mode
`
`for [the] memory system” in claims 1 and 10 should at least be:
`
`a JEDEC-compliant low power mode or ‘power down mode.’
`
`This interpretation is consistent with the specification and extrinsic evidence
`
`SMART EXHIBIT - 1002 - PAGE 20
`
`
`
`
`advanced by patent owner’s interpretation, because they disclose that the term is
`
`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
`
`synonymous with a JEDEC-complaint memory including low power mode or ‘power
`
`down mode.’ See, e.g., ‘315 patent, 5:41-48 and 5:21-25, which explains that a “low
`
`power standby mode,” is a state in which “[the memory device] is in self refresh mode
`
`and is unable to respond to memory requests including read and write requests.”
`
`Further, the ‘315 patent also provides that the “low power standby mode” is
`
`synonymous with a “power down mode.” Id., 5:29-31. Patent Owner’s statement, in
`
`concurrent litigation, is that “a low power mode for [the] memory system” should be
`
`construed to include the JEDEC standards, for e.g., section 3.11 in DDR2. Ex. 1003,
`
`4 & Ex. 1017, 15. Specifically, Patent Owner referenced the “‘Power-Down [mode
`
`of DDR 2, which is entered] when there is no read or write operations.” Id. Also, Ex.
`
`1008, Section 3.11. I have applied this interpretation, based on patent owner’s
`
`construction, in my analysis of the claims in the subsequent sections and the attached
`
`claim charts.
`
`VI.
`
`INVALIDITY REJECTIONS
`
`
`
`A.
`
`Schaefer In View Of Qureshi Rejections
`
`44. When the proposed claim constructions are adopted, each and every
`
`limitation of Claims 1 and 5 are disclosed by Schaefer in view of Qureshi. A claim
`
`construction that encompasses the JEDEC specification must also encompass the
`
`disclosure of Schaefer. This is, at least, because of the structural and functional
`
`
`
`
`
`SMART EXHIBIT - 1002 - PAGE 21
`
`
`
`
`similarity of the Schaefer memory device and that of the JEDEC specification
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`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
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`memory device, as discussed in Section IV(A).
`
`
`
`
`
`1.
`
`Obviousness Of Claims 1 and 5
`
`45. Claims 1 and 5 of the ‘315 patent are obvious over Schaefer in view of
`
`Qureshi. Attached as Appendix B is a claim chart showing how and where each
`
`limitation of Claims 1 and 5 is disclosed by Schaefer in view of Qureshi.
`
`a. Motivation To Combine And Predictability Of The Art
`
`46. A POSITA would be motivated to combine Schaefer with Qureshi,
`
`because the functional electronic modules of Schaefer and Qureshi are configured to
`
`work together. For example, Schaefer teaches an SDRAM memory (e.g., Micron
`
`MT48LC2M8S1 chip) that includes a low power self-refresh mode used to retain data
`
`in low power situations (Schaefer, 3:3-6); and Qureshi teaches a memory controller
`
`that is configured to place any SDRAM memory into a low power self-refresh mode,
`
`for the purposes of data retention during testing (Qureshi, 1:65-2:2).
`
`47.
`
`Schaefer and Qureshi also disclose that their respective teachings are
`
`merely exemplary modules that a POSITA may apply, in a variety of ways, without
`
`departing from the scope of their corresponding functions. For example, Schaefer
`
`discloses that “those of ordinary skill in the art [would appreciate] that a wide variety
`
`of alternate and/or equivalent implementations calculated to achieve the same
`
`purposes may be substituted . . . without departing from the scope of the present
`
`
`
`
`
`SMART EXHIBIT - 1002 - PAGE 22
`
`
`
`ATTORNEY DOCKET NO.: 21584-112006
`Case No. TBD
`
`invention.” Schaefer, 10:25-33. Qureshi explains that “in accordance with [its]
`
`invention, memory such as SDRAMs are put into self refresh mode while JTAG
`
`testing is performed.” Qureshi, 1:63-65.
`
`48.
`
`As Schaefer and Qureshi provide that their respective disclosures are
`
`understood by a POSITA, and may be modified, altered or adapted, while retaining
`
`their corresponding expected functions, the prior art teaches that the field of the ‘315
`
`patent is very predi
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