UNITED STATES PATENT & TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SMART MODULAR TECHNOLOGIES INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner.
`
`Case IPR2105-01675
`Patent No. 6,243,315 B1
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, AND
`GARTH D. BAER, Administrative Patent Judges
`
`PATENT OWNER SUBMITS SUPPLEMENTAL EVIDENCE
`
`David Fink (Lead Counsel)
`Registration No. 25,972
`Fink & Johnson
`7519 Apache Plume
`Houston, TX 77071
`Tel.: 713-729-4991
`texascowboy6@gmail.com
`
`-1-
`
`

`

`The Petitioner has submitted objections on March 11, 2016 to Exhibits to the Patent
`
`Owner’s Response filed March 3, 2016.
`
`The Petitioner filed the objections more than 5 days after the Patent Owner’s Response,
`
`thereby failing to comply with 37 C.F.R. § 42.64(b)(1). For this and other reasons, the
`
`objections should be ignored.
`
`Nevertheless, Patent Owner respectfully submits Supplemental Evidence shown in
`
`Exhibit 1 to replace the attachments to the Patent Owner’s Response.
`
`It is respectfully pointed out that the Supplemental Evidence is identical to the
`
`attachments to the Response; however, there is added information in the lower right hand corner
`
`identifying the pages as part of the Patent Owner’s evidence, along with page numbering.
`
`March 16, 2016
`
`Respectfully submitted,
`
`/David Fink/
`
`David Fink (Lead Counsel)
`Registration No. 25,972
`Fink & Johnson
`7519 Apache Plume
`Houston, TX 77071
`Tel.: 713-729-4991
`texascowboy6@gmail.com
`
`-2-
`
`

`

`EXHIBIT 1
`EXHIBIT 1
`
`-3-
`-3-
`
`

`

`Memory Configurations: JESD21-C I JEDEC
`
`Page I ofS
`
`Memory Configurations: JESD21-C
`
`JESD21-C, JEDEC Configurations for Solid State Memories, is a compilation of some 3000 pages of all
`memory device standards tor solid state memory including DIMM, DRAM, SDRAM, MCP, PROM, and others
`from September 1989 to present. The document is divided into sections for ease of use. Each section can be
`searched by following one of the links listed on the menu "JESD21-C Standards" on the right of this page.
`
`The JEDEC JC-42 l/committees/jc-42\ Committee on RAM Memory and tts Subcommittees, JC-45
`(fcommltteesljc:45l Committee on Memory Modules and its Subcommittees and the JC-63 llcommltteesljc-63\
`Committee on Multi Chip Packages develop the standards in JESD21-C and are responsible for updating the
`publication.
`
`An annual updating service !lstandards-documentslorder-hard-copiesl for JESD21 is available by subscription.
`Subscribers receive periodic electronic updates for replacement or insertion into the hard copy JESD21-C.
`
`A complete hard COPY of JESD21-C (fstandards-documentslorder-hard-copiesl is available for purchase. The
`hard copy comes in two 3" wide 3-ring binders so that future updates can be added with ease.
`
`JESD21-C l/sites/defaultlfiles/21C TOCR24.pdfl: Table of Contents
`• Section 1 : Scope
`Section 2: llsitesldefaultlfiles/2 OOR20.pdfl Terms and Deftnitions
`• Section 3 llsites/defaultlflles/3 01 01.pdfl: General
`• Section 6 l/sites/defaultlfiles/6 OOR17.pd0: Applicable Other Documents
`Annexes llsites/defaultlfiles/21 c AnnexAR24.pdf}: Differences between revisions
`
`Search Documents Related to Memory Configurations: JESD21-C
`
`• Memory Confiauratlons: JESD21-C (/standards-documents/results/field belong to:%22Publication%
`2095%221
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`Recent Documents
`
`Title
`
`Document# Date
`
`SPD4.1.2.M-1
`
`https://www.jedec.org/category/technology-focus-area/memory-configurations-jesd21-c
`
`3/2/2016
`
`IPR2015-01675 GOODMAN EX A 2001
`
`

`

`JEDEC Standarad No. 21-C
`Page 3.12.3-1
`
`3.12.3 Silicon Pad Sequences
`
`3.12.3.1 LPDRAM (SDR/DDR) Silicon Pad Sequence Guidelines
`(x16, x32, single/doubl-ide, asymmetricaU symmetrical design)
`
`Figure 3.12.3.1-1 Example A -Asymetric DRAM Pad Sequence (x32) ........................................... 3
`Figure 3.12.3.1-2 Example B-Asymetric DRAM Pad Sequence (x16) .......................................... 4
`Figure 3.12.3.1-3 Example C -Symetric DRAM Pad Sequence (x16) ............................................. 5
`Figure 3.12.3.1-4 Example D - Symetrlc DRAM Pad Sequence (x32) ............................................. 6
`Figure 3.12.3.1-6 Example E -Single-Side DRAM Pad Sequence (x32) ......................................... 7
`Figure 3.12.3.1-6 Example F -Symetric DRAM Pad Sequence (x16) ............................................. 8
`Figure 3.12.3.1-7 Example G -Super-bond layout patten with Status Read Register locations .9
`
`3.12.3.2 x16 PS RAM Silicon Pad Sequence Order
`
`Figure 3.12.3.2-1 x16 PSRAM Silicon Pad Order Reference(Top View ........................................ 10
`Figure 3.12.3.2-2 X16 PSRAM Silieon Pad Order (Option A and 9) ............................................. 11
`
`3.12.3.3 x18 NANO Interfaced Memories Silicon Pad Sequenee
`
`Figure 3.12.3.3-1 x18 NANO Interfaced Memories Silicon Pad Sequanca (Top View ................. 12
`
`Release 15r18r16A
`
`IPR2015-01675 GOODMAN EX A 2002
`
`

`

`JEDEC Standared No. 21-C
`Page 3.12.3- 2
`
`3.12.3.1 LPDRAM (SDR/DDR) Silicon Pad Sequence Guidelines
`(x16, x32, single/double-side, asymmetricaU symmetrical design)
`I One pair VDDQNSSQ per 4DQs -place between DQ"s (two DQs on each side ofVDDQIVSSQ)
`
`2. DQS and DM must be within the data groups
`28 DQS and OM pairs located at end of data bytes toward center of die
`2C. DQ's should be in sequential order DQ [MAX:O]
`20 Sequential order of DQ"s based on standard MCP and Pkg-on-Pkg electrical
`interfacealignmentand LPDRAM Status Register fixed lower word implementation
`
`3. VDD/VSS core supply in center and at both edges of pad sequence, center may have multiple pairs.
`
`4. VDDQNSSQ alternate across DQ groups for better routing
`
`5. Clock needs to be at the die center for speed and symmetrical distribution.
`SA. One or two elk/elk# pairs are optional; if two. both pairs must be connected on silicon or package
`substrate.
`
`6. Adjacent groups must be address and control. also for speed, the 5 non-address control lines (CKE,
`WE, CAS, RAS, CS) should be on the same side of the clock because of their inter-relations in the
`main chip state machine.
`6A.The Specific order of ctrl signals doesn't matter but should be CKE, WE, CAS, RAS, CS for stan(cid:173)
`dard purposes
`
`7. Non-Standard signals (non-speed critical) should be located on outside ends of pad sequence on the
`less populated pad side (examples: TQ- Temp sense, DPD, etc.)
`
`8. Keeping symmetry for x32 and xl6 provides the added benefit of enabling a single design for the two
`widths
`
`9. Doesn't need to conform to discrete LPDRAM bailout (non-stacked)
`
`JO.Address signals should be compatible to discrete LPSDR/DDR bailout {A4: 15] and [AO:A3] groups
`NOTE: NC pad locations may vary.
`Seven examples are provided in Figures 3.12.3.1-1 through 7, for reference
`x32 Asymmetrical (example A)
`x16 Asymmetrical (example B)
`x 16 Symmetrical (example C)
`x32 Symmetrical (example D)
`x32 Single Side (example E)
`x 16 Single Side (example F)
`Super-bond layout pattern with Status Read Register locations (example G)
`
`Rel-15r16A
`
`IPR2015-01675 GOODMAN EX A 2003
`
`

`

`CERTIFICATE OF SERVICE IN COMPLIANCE WITH 37 C.F.R. § 42.6(E)(4)
`
`The undersigned certifies that a complete copy of this PATENT OWNER SUBMITS
`
`SUPPLEMENTAL EVIDENCE was served via email on Counsel for Petitioner in this proceeding
`
`on March 16, 2016:
`
`Michael F. Heafey
`King & Spalding
`601 South California Avenue, Suite 100
`Palo Alto, CA 94304
`mheafey@kslaw.com
`
`Date: March 16, 2016
`
`/David Fink/
`David Fink (Lead Counsel)
`Registration No. 25,972
`Fink & Johnson
`7519 Apache Plume
`Houston, TX 77071
`Tel.: 713-729-4991
`texascowboy6@gmail.com
`
`-4-
`
`