Helsinki University of Technology, Electronic Circuit Design Laboratory
`
`Report 39, Espoo 2004
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`Low-Noise Amplifiers for Integrated Multi-Mode Direct-
`Conversion Receivers
`
`
`
`
`Jussi Ryynänen
`
`
`
`Dissertation for the degree of Doctor of Science in Technology to be presented with due
`permission of the Department of Electrical and Communications Engineering for public
`examination and depate in Auditorium S4 at Helsinki University of Technology (Espoo,
`Finland) on the 18th of June, at 12 o’clock noon.
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`Helsinki University of Technology
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`Department of Electrical and Communications Engineering
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`Electronic Circuit Design Laboratory
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`Teknillinen korkeakoulu
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`Sähkö- ja tietoliikennetekniikan osasto
`
`Piiritekniikan laboratorio
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`
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`TCL EXHIBIT 1052
`Page 1 of 150
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`

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`
`Distribution:
`
`Helsinki University of Technology
`
`Department of Electrical and Communications Engineering
`
`Electronic Circuit Design Laboratory
`
`P.O.Box 3000
`
`FIN-02015 HUT
`
`Finland
`
`Tel. +358 9 4512271
`
`Fax: +358 9 4512269
`
`
`Copyright  2004 Jussi Ryynänen
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`ISBN 951-22-7109-5
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`ISSN 1455-8440
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`
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`
`
`Espoo 2004
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`
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`TCL EXHIBIT 1052
`Page 2 of 150
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`

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`Abstract
`
`The evolution of wireless telecommunication systems during the last decade has been rapid.
`During this time the design driver has shifted towards fast data applications instead of speech.
`In addition, the different systems may have a limited coverage, for example, limited to urban
`areas only. Thus, it has become important for a mobile terminal to be able to use different
`wireless systems, depending on the application chosen and the location of the terminal.
`
`The choice of receiver architecture affects the performance, size, and cost of the receiver. The
`superheterodyne receiver has hitherto been the dominant radio architecture, because of its good
`sensitivity and selectivity. However, superheterodyne receivers require expensive filters, which,
`with the existing technologies, cannot be integrated on the same chip as the receiver. Therefore,
`architectures using a minimum number of external components, such as direct conversion, have
`become popular. In addition, compared to the superheterodyne architecture, the direct-
`conversion architecture has benefits when multi-mode receivers, which are described in this
`thesis, are being designed.
`
`In this thesis, the limitations placed on the analog receiver by different system specifications are
`introduced. The estimations for the LNA specifications are derived from these specifications. In
`addition, the limitations imposed by different types of receiver architectures are described. The
`inductively-degenerated LNA is the basis for all the experimental circuits. The different
`components for this configuration are analyzed and compared to other commonly-used
`configurations in order to justify the use of an inductively-degenerated LNA. Furthermore, the
`design issues concerning the LNA-mixer interface in direct-conversion receivers are analyzed.
`Without knowing these limitations, it becomes difficult to understand the choices made in the
`experimental circuits.
`
`One of the key parts of this thesis describes the design and implementation of a single-chip
`multi-mode LNA, which is one of the key blocks in multi-mode receivers. The multi-mode
`structures in this thesis were developed for a direct-conversion receiver where only one system
`is activated at a time. The LNA interfaces to a pre-select filter and mixers and the different
`LNA components are analyzed in detail. Furthermore, the design issues related to possible
`interference from additional systems on single-chip receivers are analyzed and demonstrated.
`
`A typical receiver includes variable gain, which can be implemented both in the analog
`baseband and/or in the RF. If the variable gain is implemented in the RF parts, it is typically
`placed in the LNA or in a separate gain control stage. Several methods that can be used to
`implement a variable gain in the LNA are introduced and compared to each other. Furthermore,
`several of these methods are included in the experimental circuits.
`
`The last part of this thesis concentrates on four experimental circuits, which are described in
`this thesis. The first two chips describe an RF front-end and a direct-conversion receiver for
`WCDMA applications. The whole receiver demonstrates that it is possible to implement A/D
`converters on the same chip as sensitive RF blocks without significantly degrading receiver
`performance. The other two chips describe an RF front-end for WCDMA and GSM900
`applications and a direct-conversion receiver for GSM900, DCS1800, PCS1900 and WCDMA
`systems. These ICs demonstrate the usability of the circuit structure developed and presented in
`this thesis. The chip area in the last multi-mode receiver is not significantly increased compared
`to corresponding single-system receivers.
`
`Keywords: analog integrated circuit, BiCMOS, direct-conversion, low-noise amplifiers,
`mobile communication, multi-mode, radio receivers.
`
`i
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`TCL EXHIBIT 1052
`Page 3 of 150
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`

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`Preface
`
`The research for this thesis has been carried out in Electronic Circuit Design Laboratory of
`Helsinki University of Technology between 1998 and 2003. The work presented in this thesis is
`part of a research project funded by Nokia Networks, Nokia Mobile Phones, and Finnish
`National Technology Agency (TEKES). During years 2001-2003, I had the privilege of
`participating the Graduate School in Electronics, Telecommunications, and Automation
`(GETA), which partially funded my studies. I also thank the following foundations for financial
`support: Nokia Foundation, the Finnish Society of Electronics Engineers (EIS), Emil Aaltonen
`Foundation, the Foundation of Technology (TES), Jenny and Antti Wihuri Foundation, and the
`Foundation for Financial Aid at Helsinki University of Technology.
`
`I would like to thank my supervisor Prof. Kari Halonen for the opportunity to work relatively
`freely on an interesting research topic and his encouragement and guidance during the research.
`I also warmly thank Prof. John Long and Dr. Petteri Alinikula for reviewing my thesis and for
`their valuable comments and suggestions.
`
`I want to express my gratitude to all my present and former colleagues at the laboratory for
`creating a relaxed and pleasant atmosphere. I wish to thank Dr. Aarno Pärssinen for his valuable
`advices and instructions and for teaching me a lot of things about the design of RF circuits and
`direct-conversion receivers. I am also grateful to Dr. Jarkko Jussila for advices and comments in
`the field of integrated radio receivers and analog baseband circuits. In addition, I would like to
`thank Mikko Hirvonen, Jouni Kaukovuori, and Kari Stadius for their help and comments during
`the project.
`
`The members of the research team “SuMu”, Dr. Jarkko Jussila, Dr. Kalle Kivekäs, Dr. Aarno
`Pärssinen, and Dr. Lauri Sumanen, deserve special thanks for creating an excellent working
`atmosphere. Without their help and contributions this thesis had never been finished. Especially
`the high motivation and friendly atmosphere among this team helped this thesis. In addition, the
`junior researchers in direct conversion receiver projects and power amplifier projects, Mikko
`Hotti, Jere Järvinen, Pasi Juurakko, Jouni Kaukovuori, Arto Malinen, and Ville Saari, is also
`gratefully acknowledged.
`
`Finally, my warmest thanks go to my parents Hillevi and Kari and my brother Heikki for their
`support and encouragement during my studies. A huge thanks goes to my dear wife, Kirsi, who
`has shared the good as well as the difficult times during this doctoral work.
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`Jussi Ryynänen
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`Espoo, June 2004
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`ii
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`TCL EXHIBIT 1052
`Page 4 of 150
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`

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`Contents
`
`
`Abstract................................................................................................................................. i
`Preface .................................................................................................................................. ii
`Contents................................................................................................................................ iii
`Symbols and abbreviations ................................................................................................... v
`Symbols........................................................................................................................... v
`Abbreviations.................................................................................................................. vii
`1 Introduction..................................................................................................................... 1
`1.1 Motivation for the thesis.......................................................................................... 1
`1.2 Research contribution and publications................................................................... 1
`1.3 Organization of the thesis........................................................................................ 4
`2 Requirements for low-noise amplifiers in wireless communications............................... 5
`2.1 Superheterodyne receiver ........................................................................................ 5
`2.2 Direct-conversion receiver ...................................................................................... 6
`2.3 Other architectures .................................................................................................. 9
`2.4 Wireless telecommunication systems ...................................................................... 10
`2.5 Design parameters for low-noise amplifiers............................................................ 11
`2.5.1 Sensitivity and noise figure .......................................................................... 11
`2.5.2 Linearity....................................................................................................... 16
`2.6 Receivers with multi-mode capabilities................................................................... 24
`2.7 References............................................................................................................... 27
`3 Single-system low-noise amplifier design ....................................................................... 29
`3.1 Single-stage LNA configurations ............................................................................ 29
`3.1.1 Input matching ............................................................................................. 30
`3.1.2 Voltage gain................................................................................................. 31
`3.1.3 Noise figure.................................................................................................. 33
`3.1.4 NF of the inductively-degenerated common-emitter LNA........................... 35
`3.1.5 IIP3 .............................................................................................................. 37
`3.1.6 Summary of the input stage comparison ...................................................... 40
`3.2 Cascode transistor ................................................................................................... 40
`3.3 Load of the LNA ..................................................................................................... 42
`3.3.1 Resistive load............................................................................................... 42
`3.3.2 Resonator load ............................................................................................. 43
`3.4 LNA biasing ............................................................................................................ 45
`3.5 Single-ended and balanced LNAs ........................................................................... 47
`3.6 Interface to mixer .................................................................................................... 48
`3.7 References............................................................................................................... 50
`4 Design of multi-mode low-noise amplifiers for DCRs.................................................... 53
`4.1 Multi-mode input stage design ................................................................................ 53
`4.2 Load in multi-mode LNAs ...................................................................................... 58
`4.3 LNA and mixer interface......................................................................................... 62
`4.4 Interference between different systems ................................................................... 63
`4.5 Recent publications describing multi-mode LNAs.................................................. 66
`4.6 References............................................................................................................... 66
`5 Variable gain in inductively-degenerated LNAs ............................................................. 68
`5.1 Analog and digital gain control ............................................................................... 68
`5.2 Gain control in inductively-degenerated LNA ........................................................ 69
`
`iii
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`TCL EXHIBIT 1052
`Page 5 of 150
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`

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`5.2.1 Variable gain using input stage and load adjustment ...................................69
`5.2.2 Variable gain implemented using analog or digital current steering ............72
`5.2.3 Variable gain using resistor chain ................................................................75
`5.2.4 Variable gain using separate signal paths.....................................................75
`5.2.5 Comparison of gain control methods of inductively-degenerated LNA .......78
`5.3 Transients in DCRs caused by programmable gain in RF front-end........................79
`5.4 References ...............................................................................................................85
`6 Experimental circuits.......................................................................................................87
`6.1 RF front-end for direct-conversion WCDMA receiver............................................88
`6.1.1 LNA design ..................................................................................................88
`6.1.2 Mixer design ................................................................................................89
`6.1.3 Measurements ..............................................................................................91
`6.2 22-mA, 3.0-dB NF direct-conversion receiver for 3G WCDMA ............................95
`6.2.1 LNA .............................................................................................................96
`6.2.2 Downconversion mixer ................................................................................97
`6.2.3 Analog baseband circuit and A/D converters ...............................................98
`6.2.4 Experimental results.....................................................................................100
`6.3 Dual-band RF front-end for WCDMA and GSM applications................................105
`6.3.1 RF front-end for direct-conversion receivers ...............................................106
`6.3.2 LNA .............................................................................................................107
`6.3.3 Single-ended-to-differential converter .........................................................108
`6.3.4 Mixer............................................................................................................109
`6.3.5 Layout ..........................................................................................................110
`6.3.6 Experimental results.....................................................................................111
`6.4 Multi-mode receiver for GSM900, DCS1800, PCS1900, and WCDMA................117
`6.4.1 LNA .............................................................................................................118
`6.4.2 Downconversion mixer ................................................................................120
`6.4.3 Analog baseband circuit ...............................................................................122
`6.4.4 Experimental results.....................................................................................124
`6.5 Conclusions to experimental circuits.......................................................................130
`6.6 References ...............................................................................................................131
`7 Conclusions .....................................................................................................................133
`Appendix 1: Table of recently published LNAs....................................................................134
`
`
`iv
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`TCL EXHIBIT 1052
`Page 6 of 150
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`

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`Symbols and abbreviations
`
`Symbols
`
`A
`
`
`
`A1,A2…
`AV
`
`B
`
`
`
`C
`
`Cje
`Cgs
`
`Cπ
`en
`Eb
`Bn
`f
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`
`
`
`
`
`
`
`
`
`
`
`Area of bipolar transistor
`
`Amplitude, amplifier
`
`Voltage gain
`
`Channel bandwidth, Amplitude
`
`Capacitor, capacitance
`
`Base-emitter capacitor of bipolar transistor
`
`Gate-source capacitor of MOS transistor
`
`Base-emitter capacitor of bipolar transistor
`
`Noise voltage
`
`Bit energy
`
`System noise bandwidth
`
`
`
`
`
`
`
`Frequency
`
`Signal frequencies
`
`Clock frequency
`
`Corner frequency of flicker noise
`
`f1, f2,
`fCLK
`fflicker
`fHPF
`fLO
`fRF
`fSYS
`fT
`fTX
`G
`
`gm
`Gm
`i
`
`I
`
`IB
`IC
`Idd
`
`k
`
`
`
`
`
`
`
`
`
`
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`
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`
`
`
`
`
`
`
`Cutoff frequency of highpass filter
`
`Local oscillator frequency
`
`Radio frequency
`
`Frequency of the additional system
`
`Unity-gain frequency
`
`Transmitter frequency
`
`Gain
`
`Transconductance
`
`Transconductance
`
`AC current
`
`In-phase
`
`Base current of a bipolar transistor
`
`Collector current of a bipolar transistor
`
`Current consumption
`Boltzmann’s constant ≈ 1.3807⋅10-23J/K
`
`v
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`TCL EXHIBIT 1052
`Page 7 of 150
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`

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`K
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`kcmod
`L
`
`M
`
`mc
`n
`
`Nin
`Nout
`Pcmod
`
`Pd
`Pin
`Pimd2
`Pimd3
`PLO
`Pout
`P1, P2
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`
`
`
`
`
`
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`
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`
`
`
`
`
`
`Constant
`
`Empirical factor
`
`Inductor, loss, effective channel length of a MOSFET
`
`MOSFET
`
`Frequency conversion term
`
`Bipolar transistor ideality factor
`
`Noise power at input
`
`Noise power at output
`
`Cross modulation power in the user channel
`
`Power dissipation
`
`Input power
`
`Power of second-order intermodulation product at output
`
`Power of third-order intermodulation product at output
`
`Power of local oscillator
`
`Output power
`
`q
`
`Q
`
`R
`
`ro
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`rπ
`RS
`Sin
`Sout
`Ssensitivity
`Sth
`
`S11
`
`
`
`T
`
`Tbit
`Tchip
`V
`
`
`
`
`
`
`
`
`
`VBE, V1, Vπ
`
`Vgs
`vout
`
`
`
`
`
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`
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`
`
`
`
`
`
`
`
`
`
`Signal powers
`Electron charge ≈ 1.602⋅10-19C
`Quadrature-phase, quality factor, bipolar transistor
`
`Resistor, resistance
`
`Output resistance
`
`Base-emitter resistance of bipolar transistor
`
`Source resistance
`
`Signal power at input
`
`Signal power at output
`
`Sensitivity level
`
`Thermal noise floor
`
`Scattering parameter of two-port (reflection)
`
`Absolute temperature
`
`Bit duration
`
`Chip duration
`
`DC voltage, signal amplitude
`
`Base-emitter voltage of a BJT
`
`Gate-source voltage of a MOSFET
`
`Output signal
`
`vi
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`TCL EXHIBIT 1052
`Page 8 of 150
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`

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`vs
`VT
`W
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`
`
`
`
`
`
`
`
`
`
`ZIN
`ZL
`ZS
`
`α1, α2…
`β
`
`δ
`∆P2
`∆P3
`γ
`τF
`ω
`ωr
`
`
`
`
`
`
`
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`
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`
`
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`Source voltage
`
`Thermal voltage
`
`Effective channel width of a MOSFET
`
`Input impedance
`
`Load impedance
`
`Source impedance
`
`Nonlinearity coefficients
`
`
`
`
`
`Bipolar transistor current gain
`
`MOS transistor noise constant
`
`Power difference between fundamental and second-order signals
`
`Power difference between fundamental and third-order signals
`
`MOS transistor noise constant
`
`Forward transit time of a BJT
`
`Angular frequency
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`Angular frequency at resonance
`
`Abbreviations
`
`AC
`
`ADC
`
`
`
`
`
`
`
`
`
`Alternating current
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`Analog-to-digital converter
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`Automatic gain control
`
`AGC
`
`AM
`
`AMPS
`
`BER
`
`
`
`
`
`
`
`
`
`BiCMOS
`
`BJT
`
`BPF
`
`BS
`
`
`
`
`
`
`
`CDMA
`
`CMFB
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`CMOS
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`CG
`
`CLK
`
`CW
`
`
`
`
`
`
`
`
`
`
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`
`
`
`
`
`
`
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`
`
`
`
`
`
`
`
`
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`Amplitude modulation
`
`Advanced mobile phone system
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`Bit-error rate
`
`Bipolar complementary metal oxide semiconductor
`
`Bipolar junction transistor
`
`Bandpass filter
`
`Base station
`
`Code division multiple access
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`Common-mode feedback
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`Complementary metal oxide semiconductor
`
`Coding gain
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`Clock
`
`Continuous wave
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`vii
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`DAC
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`DC
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`DCR
`
`
`
`
`
`
`
`DCS1800
`
`DNL
`
`DS
`
`DSB
`
`DSP
`
`ENOB
`
`ESD
`
`F
`
`FDD
`
`FER
`
`FFT
`
`FH
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`GMSK
`
`GPS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Digital-to-analog converter
`
`Direct current
`
`Direct-conversion receiver
`
`Digital cellular system
`
`Differential nonlinearity
`
`Direct Sequence
`
`Double sideband
`
`Digital signal processor
`
`Effective number of bits
`
`Electrostatic discharge
`
`Noise factor
`
`Frequency division duplex
`
`Frame error rate
`
`Fast Fourier transform
`
`Frequency hopping
`
`Gaussian minimum shift keying
`
`Global positioning system
`
`Global system for mobile communications
`
`GSM, GSM900
`
`HPF
`
`IC
`
`ICP
`
`IF
`
`IIP2
`
`IIP3
`
`INL
`
`ITU
`
`LC
`
`LNA
`
`LO
`
`LSB
`
`MS
`
`MOS
`
`NF
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`NMOS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Highpass filter
`
`Integrated circuit
`
`Input compression point
`
`Intermediate frequency
`
`Second-order input intercept point
`
`Third-order input intercept point
`
`Integral nonlinearity
`
`International Telecommunications Union
`
`Inductor-capacitor
`
`Low-noise amplifier
`
`Local oscillator
`
`Least significant bit
`
`Mobile station
`
`Metal oxide semiconductor
`
`Noise figure
`
`N-channel metal oxide semiconductor
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`viii
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`OFDM
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`OIP3
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`PCB
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`
`
`
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`PCS1900
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`PMOS
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`PSD
`
`QPSK
`
`RC
`
`RC-PP
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`RF
`
`RMS
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`RX
`
`SAW
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`SF
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`SFDR
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`SG
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`
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`
`
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`Orthogonal frequency division multiplex
`
`Third-order output intercept point
`
`Printed circuit board
`
`Digital cellular system
`
`P-channel metal oxide semiconductor
`
`Power spectral density
`
`Quadrature phase shift keying
`
`Resistor-capacitor
`
`Resistor-capacitor polyphase filter
`
`Radio frequency
`
`Root-mean-square
`
`Receiver
`
`Surface acoustic wave
`
`Spreading factor
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`Spurious free dynamic range
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`Spreading gain
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`Super high frequency
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`
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`
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`
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`
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`
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`SHF
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`SiGe
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`SNDR
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`SNR
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`SS
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`SSB
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`TDD
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`TDMA
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`TX
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`UHF
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`UTRA
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`VCO
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`WCDMA
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`WLAN
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`2G
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`3G
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`
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`Silicon-germanium
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`Signal-to-noise and distortion ratio
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`Signal-to-noise ratio
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`Spread spectrum
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`Single sideband
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`Time division duplex
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`Time division multiple access
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`Transmitter
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`Ultra high frequency
`
`UMTS terrestrial radio access
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`Voltage controlled oscillator
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`Wide-band code division multiple access
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`Wireless local area network
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`Second generation
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`Third generation
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`ix
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`1
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`Introduction
`
`1.1 Motivation for the thesis
`
`The evolution of current wireless communication systems has been very rapid. The goal has
`been small-size and low-cost terminals that can be programmed for different applications.
`Hence, the trend has been towards digital transceivers. The implementation of a “full” digital
`transceiver is still unrealistic and, therefore, many analog circuits that shape and transform the
`data are required. In addition, the implementation of future systems sets new challenges for
`circuit and system level design. The implementation of high data rates in wireless systems may
`require for example, wide channel bandwidths, continuous-time reception, and, because of the
`available frequency bands, usually high receive and transmit frequencies (> 2GHz). In addition,
`new systems should be implemented using low supply voltages without significantly degrading
`the performance compared to the current systems. For example, the operation time of a terminal
`with fast data rates should be the same as in current terminals. Therefore, the design of
`integrated analog circuits becomes very challenging and new circuit- and system-level solutions
`will be needed.
`
`The first terminals using 3G wide-band code division multiple access (WCDMA) systems are
`already available to consumers. These terminals can provide high-speed data connections, thus
`partly making possible fast and real-time Internet connections. At first, these systems will cover
`urban areas and, in order to maintain a connection to these terminals, the terminal should be
`able to use other existing systems in rural areas. In addition, it may be more optimal to use the
`other systems for different types of applications. For example, GSM-based systems could be
`used for speech connections when high-speed data is not required. The integration of these
`multi-system, multi-band terminals is challenging because, in order to minimize the size of
`these transceivers, the different systems should share most of their building blocks.
`
`One of the most challenging building blocks in multi-mode receivers is the low-noise amplifier
`(LNA). In order to achieve a sufficient performance, frequency-selective components are
`usually required in the LNA. Therefore, the operation bandwidth of the LNA is not sufficient
`for multi-band and multi-system operation without the addition of adjustable components.
`Furthermore, when the LNA is integrated on the same chip as the other building blocks, the
`interference from these blocks can deteriorate the performance of the LNA.
`
`1.2 Research contribution and publications
`
`This thesis concentrates on the design and implementation of LNAs for multi-mode direct-
`conversion receivers (DCRs). The author describes and proposes solutions for the design and
`implementation of this type of LNA. The approach in this thesis has been to start the design
`from the system requirements. The requirements for the LNA are derived from the
`specifications, together with the designers of the other blocks. The circuit structures for multi-
`mode receivers are developed from the LNA specifications. The goal has not been to develop or
`model different devices on the IC. The IC manufacturer provided the detailed models for the
`passives, transistors, and bonding pads including ESD, used in the experimental circuits.
`
`A huge number of LNAs have been reported in the literature. It is not the purpose of this thesis
`to review the development of these LNAs comprehensively. The focus is on the recently-
`
`1
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`published designs. The author has designed and implemented all the LNAs presented in this
`thesis. The first two experimental circuits are designed for a WCDMA receiver, and the other
`two are targeted for multi-mode applications. The main emphasis in this thesis is on finding
`circuit solutions to make multi-mode operation possible by sharing devices already in the LNA,
`thus excluding straightforward parallel structures. In addition, the focus is on how to implement
`a variable gain in single-system and multi-mode LNAs.
`
`The research team which designed, implemented, and measured the receivers published in this
`thesis consisted of five members, including the author. The other researchers were Dr. Jarkko
`Jussila, Dr. Kalle Kivekäs, Dr. Aarno Pärssinen, and Dr. Lauri Sumanen. In each paper, the first
`author had the main responsibility for the manuscript.
`
`Papers P1 and P2 describe a chip-set for a direct-conversion receiver designed for the WCDMA
`system. Dr. Pärssinen and Dr. Jussila made the system design for the receiver. The author is
`responsible for the design, implementation, and partitioning of the RF front-end, together with
`Dr. Pärssinen. Dr. Jussila and Dr. Sumanen are responsible for the analog baseband and A/D
`converter chips, respectively.
`
`Paper P3 is a conference article based on P1 and P2 and presents the RF front-end of the chip-
`set in P1. The contribution of the author is the same as in P1 and P2.
`
`Paper P4 is a single-chip version of the receiver presented in P1. Only minor modifications
`were made to the RF front-end of the receiver. The author’s contribution is the same as in P1.
`
`Papers P5 and P6 present a single-chip receiver designed for WCDMA systems. The author
`contributed to the RF front-end partitioning, LNA design, and implementation. He also
`participated in the receiver measurements. The A/D converter, which was implemented on the
`same chip as a sensitive RF front-end, had only a minor effect on the performance of the
`receiver. Dr. Jussila and Dr. Pärssinen participated in the receiver partitioning. In addition, Dr.
`Pärssinen contributed to the RF front-end design; Dr. Kivekäs contributed to the RF front-end
`partitioning and mixer design and implementation. Dr. Jussila and Dr. Sumanen are responsible
`for the analog baseband and A/D converter circuits, respectively.
`
`Papers P7 and P8 present an RF front-end, which is targeted for WCDMA and GSM
`applications. The RF front-end can use all devices except the LNA input stage in both modes.
`The author is responsible for the RF front-end partitioning, the LNA, and single-ended-to-
`differential converter design and implementation. Dr. Kivekäs and Dr. Pärssinen contributed to
`the RF front-end partitioning and Dr. Kivekäs was responsible for the mixer design.
`
`Paper P9 is a journal article which deals with the single-chip quad-mode direct-conversion
`receiver. The component sharing of this receiver is optimised and it uses only four on-chip
`inductors. In addition, the gain control transients from the LNA gain control are significantly
`improved compared to those in previous publications by the same author. The author is
`responsible for the receiver partitioning, together with Dr. Kivekäs and Dr. Jussila. In addition,
`the author is responsible for the LNA design and LNA-mixer interface design. The receiver was
`implemented in co-operation with Dr. Jussila, Dr. Kivekäs, Dr. Pärssinen, and Dr. Sumanen.
`
`P1
`
`P2
`
`A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. Halonen, “A Wide-Band Direct
`Conversion Receiver for WCDMA Applications,” ISSCC Digest of Technical Papers,
`pp. 220-221, Feb. 1999.
`
`A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. Halonen, “A 2-GHz Wide-Band
`Direct Conversion Receiver for WCDMA Applications,” IEEE J. Solid-State Circuits,
`vol. 34, pp. 1893-1903, Dec. 1999.
`
`2
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`P3
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`P4
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`P5
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`P6
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`P7
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`P8
`
`P9
`
`J. Ryynänen, A. Pärssinen, J. Jussila, K. Halonen, “An RF Front-End for the Direct
`Conversion WCDMA Receiver,” IEEE RFIC Digest of Papers, June 1999, pp. 21-24.
`
`A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, K. Kivekäs, K. Halonen, “A Wide-
`Band Direct Conversion Receiver With On-Chip A/D Converters,” in Symposium on
`VLSI Circuits Digest of Technical Papers, pp. 32-33, June 2000.
`
`J. Jussila, J. Ryynänen, K. Kivekäs, L. Sumanen, A. Pärssinen, K. Halonen, “A 22-mA
`3.7dB NF Direct Conversion Receiver for 3G WCDMA,” ISSCC Digest of Technical
`Papers, pp. 284-285, Feb. 2001.
`
`J. Jussila, J. Ryynänen, K. Kivekäs, L. Sumanen, A. Pärssinen, K. Halonen, “A 22-mA
`3.0-dB NF Direct Conversion Receiver for 3G WCDMA,” IEEE J. Solid-State
`Circuits, vol. 36, pp. 2025-2029, Dec. 2001.
`
`J. Ryynänen, K. Kivekäs, J. Jussila, A. Pärssinen, “A Dual-Band RF Front-End for
`WCDMA and GSM Applications,” in Proceedings of Custom Integrated Circuits
`Conference, pp. 175-178, May 2000.
`
`J. Ryynänen, K. Kivekäs, J. Jussila, A. Pärssinen, K. Halonen, “A Dual-Band RF
`Front-End for WCDMA and GSM Applications,” IEEE J. Solid-State Circuits, vol. 36,
`pp. 1198-1204, Aug. 2001.
`
`J. Ryynänen, K. Kivekäs, J. Jussila, A. Pärssinen, K. Halonen, “A Single-Chip
`Multimode Receiver for GSM900, DCS1800, PCS1900, and WCDMA,” IEEE J.
`Solid-State Circuits, vol. 38, pp. 594-602, April 2003.
`
`Other publications related to the topic:
`
`J. Ryynänen,