Fully integrated radio paging receiver
`
`I.A.W. Vance, B.Eng., M.Sc
`
`Indexing terms: Radiocommunication, Integrated circuits
`
`Abstract: A review is made of radio paging receiver requirements and a new receiver architecture is described
`which uses a direct conversion (zero-IF) principle. This circuit is shown to have advantages over the conven-
`tional superheterodyne with high-frequency IF and in particular is shown to be suitable for monolithic
`realisation. A single chip which performs as a complete high-sensitivity VHF receiver is presented, and the
`resulting miniature pager is shown.
`
`1
`
`Introduction
`
`Radio paging is an expanding sector of the telecommuni-
`cations market, and in particular a large increase in the use of
`wide-area paging systems is taking place at the present time.
`Receivers for wide-area applications place severe demands on
`the circuits and technology used owing to the necessity of
`achieving high levels of performance within constraints of
`size and power consumption. Table 1 gives a set of parameters
`as typically specified. Some of these have direct relationships
`to the physical size of the receiver, for example sensitivity
`via antenna size, spurious responses via constraints on realis-
`able lQ' of tuned circuits and, more obviously, power con-
`sumption via battery size.
`
`Table 1: Typical specifications for wide-area
`receivers
`
`radiopaging
`
`Frequency bands, MHz
`Channel spacing, kHz
`Modulation format, kHz, NRZ FSK
`Data rate, bit/s
`Sensitivity,/nV/m
`Next channel rejection, dB
`Next channel blocking level, dB
`± 20 MHz blocking level, dB
`Spurious response rejection, dB
`Battery life, week
`Temperature range, deg C
`
`87, 150, 450, 900
`25
`±4.5
`500
`10*
`65
`60
`100
`70
`13
`—5 to + 50
`
`*8 position test on body — see Reference 15
`
`However, there is a trend in the industry towards smaller
`pagers, despite an increase in functions being offered and a
`requirement to mass produce the ever increasing quantities.
`Furthermore, paging receivers exist in a rather unprotected
`environment, where they are liable to be dropped, thrown
`and generally roughly treated.
`This paper describes the implementation of a radio paging
`receiver which attempts simultaneously to ease the solution
`of all the above mentioned problems by the use of the inte-
`grated circuit medium.
`
`2
`
`Receiver fundamentals
`
`The requirements for small size, high reliability and low
`assembly cost in the radio paging receiver lead directly to the
`idea of a one-chip integrated-circuit realisation if this is poss-
`ible. The digital decoding circuitry which follows the receiver
`portion is already highly integrated in modern pagers, and so a
`complementary radio chip is a very attractive proposition.
`Conventional pagers have for many years relied on the
`single- or double-conversion superheterodyne receiver with a
`variety of intermediate frequencies being used, depending on
`the input signal band. Full integration of this type of receiver
`has not been attractive for a number of reasons. The most
`
`Paper 1729F, received 10th September 1981
`The author is with Standard Telecommunication Laboratories Limited,
`London Road, Harlow CM 17 9NA, England
`
`important of these is that such a chip fails to replace most of
`the components and becomes little more than the transistors
`of the discrete circuit made on one IC [1].
`Existing circuits (e.g. Reference 2) integrate the inter-
`mediate frequency and demodulator functions of a conven-
`tional superheterodyne receiver, but further integration of this
`to include the front end is not attractive owing to the small
`impact on size and power consumption achieved relative to a
`discrete component version.
`It has been proposed previously [3—5] that the direct
`conversion (zero-IF) type of receiver is optimum for mono-
`lithic construction, and this proves to be especially true for
`the modulation format usually adopted for digital paging
`systems, i.e. nonreturn to zero direct frequency-shift keying
`(FSK).
`The zero-IF receiver has the advantage that it has no
`1st-order spurious responses (i.e. image), and thus the problem
`of obtaining VHF selectivity in a small physical volume is
`greatly eased. Image and IF related responses other than first
`order are also eliminated, for example IF difference, IF
`breakthrough and images of harmonics. Furthermore, most
`of the receiver's gain is obtained at the lowest possible fre-
`quency, resulting in minimal power consumption and greater
`tolerance over printed circuit board layout as far as stability
`is concerned. The major benefit, however, is that the circuit
`blocks which need to be realised for this type of receiver are
`more compatible with integrated-circuit techniques.
`It is interesting to note that the first reported solid-state
`paging receiver, while completely discrete in construction
`[6], also used a quasidirect conversion technique. The IF used
`was low frequency, 5 kHz, such that the image was within the
`channel bandwidth but no sideband folding occurred.
`A similar system has also been proposed [7] with an
`in-channel IF and the use of frequency feedback to avoid
`spectrum fold-over.
`However, both these methods incur a noise figure penalty,
`up to 3 dB, unless an image rejection mixer is used if the noise
`figure is determined by the premixer gain. (They also clearly
`have assymetrical out-of-band characteristics.)
`In pagers, constraints of antenna size and current con-
`sumption do not usually allow such a relaxation of inherent
`sensitivity.
`Within the class of true zero-IF systems, the phase-locked
`loop demodulator operating at RF should be considered [8].
`This is conceptually simple but, owing to closed-loop stability
`requirements, it is not possible to obtain the required next-
`channel rejection, and miniature RF filters with adequate
`selectivity to separate a 25 kHz channel at 150 MHz are only
`just becoming state of the art via surface-acoustic-wave devices
`[9].
`The system described below follows many of the principles
`of previous work but represents a new [10] class of direct
`conversion receivers, i.e. a true zero IF using in-phase and
`quadrature channels but with limiting amplifiers in each arm,
`and a digital demodulator.
`
`0143-7070/82/010002 + 05 $01.50/0
`
`IEEPROC, Vol. 129, Pt. F, No. 1, FEBRUARY 1982
`
`TCL EXHIBIT 1045
`Page 1 of 5
`
`

`
`3
`
`Zero-IF pocket paging equipment receiver
`
`3.1 Principle of operation
`Fig. 1 shows a block diagram of the principle of the new
`paging receiver. The incoming RF signals are mixed in two
`mixers with a local oscillator nominally on the centre fre-
`quency of the signal to be received and split into quadrature
`paths as shown. At the output of the mixers, two lowpass
`filters form the channel selectivity. These filters have a pass-
`bandwidth of one half the bandwidth of the RF signal spec-
`trum, since information from both the high side and low side
`of the local oscillator is folded over into this frequency band.
`Thus, in the typical case of FSK with a deviation of ± 4.5 kHz,
`the filters have a corner frequency of between 6 and 8 kHz to
`allow for oscillator drift etc. The low-frequency outputs from
`the mixers, after selection by these filters, are fully limited in
`two high-gain limiting amplifiers and then treated as digital
`signals and processed by a digital demodulator which consists
`in its most simple form of a D-type flip-flop, as shown.
`
`1 Q'channel
`
`Fig. 1 Principle of FSK receiver, block diagram
`
`The operation of this circuit may be easily seen by the
`following consideration. In the steady-state conditions with
`the input signal in, say, the 'mark' condition, i.e. nominally
`4.5 kHz below the local oscillator, the outputs froni the two
`mixers will consist of two sine waves at 4.5 kHz in quadrature.
`After the limiting amplifiers, the data at the 'clock' and 'D'
`inputs of the flip-flop are thus 4.5 kHz square waves in quadra-
`ture, as illustrated in Fig. 2a. If the D-type is positive-edge
`clocked and the relative quadrature condition is as shown in
`
`cussed in order to highlight the improved areas and to show
`that the nonoptimal areas have a negligible impact on the
`application in hand.
`
`4.1 Sensitivity
`For wide-area pagers, high sensitivity is a major requirement.
`One of the objectives of the present work was to effect a
`dramatic decrease in size and weight of the complete pocket
`equipment, so as to increase its acceptability to the user. This
`implies a lower fundamental limit on the power received by
`the antenna, however engineered, thus placing greater demands
`on the actual receiver's performance.
`Five factors contribute
`to
`the sensitivity obtainable:
`namely the RF noise figure, the predetection noise bandwidth,
`the demodulation process, the postdetection filtering and the
`error tolerance of the digital decoder circuitry. These last two
`items will be assumed to be optimised independently of the
`receiver, and similarly the RF noise figure obtainable is not
`particular to this method. Hence we shall consider the noise
`bandwidth and the demodulator characteristics.
`
`4.2 Predetection bandwidth
`The predetection noise bandwidth will be determined by that
`of the lowpass filters, provided that the front-end gain is
`sufficient
`to overcome the wideband noise of the limiting
`amplifiers. This condition is easily met in a minimum power
`consumption design, as the amplifier bandwidth will be as
`small as is practicable within IC tolerance considerations.
`It is also a necessary condition to ensure maximum sensitivity.
`The effective noise bandwidth is thus twice the physical
`bandwidth of the filters, since noise is mixed from both above
`and below the local oscillator frequency. The split into two
`channels can be ignored, given the proviso as above that all
`the noise originates from the front end.
`
`' D' input
`'clock'input
`
`-A.5kHz
`
`4.5kHz
`
`Fig. 2 Waveforms at digital demodulator
`a Input below/„, Q = 1
`b Input above f0, Q = <p
`
`lQ output will be a constant logical
`
`the Figure, then the
`1 condition.
`Tf the input signal is now considered in the 'space' con-
`dition, i.e. 4.5 kHz above the local oscillator, the same con-
`ditions as above apply except that the relative phase of the
`data at the flip-flop inputs has shifted by 180°, i.e. 90° lag
`instead of 90° lead (Fig. 2b). This is due to mixing in the RF
`mixers from the high side instead of the low side as previously.
`The '(7 output is now clearly a continuous logical 0.
`Thus the ouput of the flip-flop changes state according
`to whether the frequency of the input signal is above or
`below the local oscillator. This is as required for an FSK
`demodulator.
`
`4
`
`Detailed performance of the system
`
`The method just described of receiving and demodulating
`signals will be expected to have performance differences
`from the conventional superheterodyne. These will be dis-
`
`IEEPROC, Vol. 129, Pt. F, No. 1, FEBRUARY 1982
`
`Fig. 3
`
`Spectrum of slow FSK signal with filtering
`optimum filter
`conventional filter
`However, for an FSK signal with a large modulation index,
`the power spectrum is entirely concentrated in two peaks
`at plus and minus the deviation frequency. The predetection
`filter would thus optimally have a shape as shown in Fig. 3
`matched to the signal spectrum and a receiver so configured
`would achieve the same increase in low signal-level sensitivity
`over a simple flat filter as would a fully optimised threshold
`extension frequency feedback system. This is important in
`paging systems, as the sensitivity specifications result in a
`measurement somewhere near the bottom of the FM threshold.
`The exact point depends on the coding, error tolerance and
`the performance of the data synchronisation circuits (see, for
`example, Reference 11). However, with the POCSAG code
`[12] used in 25 kHz channel spacing format at 512 bit/s, the
`point at which there is a 0.5 probability of receiving a paging
`call with an optimum decoder occurs when the signal/noise
`ratio in the IF is about — 1 dB. In the exemplary case used
`above, some 9dB of improvement is theoretically available at
`this point over a flat IF filter.
`With the zero-IF system, a good approximation to this ideal
`filter can be made by introducing a highpass corner into the
`
`TCL EXHIBIT 1045
`Page 2 of 5
`
`

`
`interest is that of Fig. 4, where two flip-flops are clocked off
`opposite channels in a symmetrical arrangement. The outputs
`are added resistively. This has the advantage that a noise error
`occurring in one channel will cause only a half-height output
`error. (Note that even front-end originated noise appears
`independently in the two channels.)
`A further characteristic of the system is that offsets and
`changes of deviation do manifest themselves in the form of
`edge jitter on the output pulses. This is considered more fully
`in the next Section.
`The result is that this demodulator has an output waveform
`and noise spectrum quite unlike a high-frequency discrimi-
`nator and needs different filtering and decision-making cir-
`cuitry for optimum sensitivity. It is difficult to prove that
`analysis is accurate for the very low signal/noise case needed
`here, but practical measurements of bit error rates corrected
`for IF bandwidth (Section 4.2) made with two systems using
`a common noise dominant RF stage gave sensitivities within
`1 dB. Absolute sensitivity at 512 bit/s, ±4.5 kHz deviation,
`with ±2.5 kHz receiver and transmitter offset allowance, is
`— 132dBm for 0.5 probability of POCSAG paging success
`with an optimum decoder circuit.
`
`4.4 Da ta-ra te limita tions and jitter
`The zero-IF system shown is suboptimal in that it uses limiting
`amplifiers. The effect of this may be seen by viewing the
`whole circuit as follows.
`The operation of one limiter if such that the state of the
`output of the amplifier changes for each 180° of phase change
`of the RF input signal. The other limiter behaves similarly but
`interleaved in quadrature. This is illustrated in Fig. 5, which
`
`-Q
`
`Fig. 5 Phasor diagram for in-phase and quadrature sampling
`is a phasor diagram; T represents the in-phase channel and '(?'
`the quadrature channel. Each time the input signal vector
`moves from one quadrant to the next, an edge results in one
`channel; continuous movement then causes the sequences as
`illustrated in Fig. 2 previously. When the input signal passes
`through the local oscillator frequency, the phasor stops and
`then starts to rotate in the opposite direction. Since the signal
`frequency and the time of occurrence of this transition will be
`in general asynchronously related, the position of the phasor
`at the zero-frequency crossing point will be randomly distri-
`buted around the phase diagram. Now, if the zero frequency
`point occurs, for example, at position 'a' in Fig. 5 for a phasor
`that was initially rotating counterclockwise, then an edge will
`occur almost immediately after the true zero crossing as the
`phasor repasses the + Q axis. If, however, point 'b' had been
`reached, then a delay will occur before the + Q axis is
`recrossed.
`
`IEEPROC, Vol. 129, Pt. F, No. 1, FEBRUARY 1982
`
`two channels; this, when reflected around the oscillator
`frequency, gives the desired response. In practice, with receiver
`and transmitter frequency offsets taken into account, a more
`modest but still useful improvement in sensitivity can be
`obtained over a conventional superhet design, and a DC block
`is necessary at this point in any case.
`Of particular interest here is the effect of deliberate trans-
`mitter offsets employed in a simultaneous multitransmitter
`system [13, 14]. As an example, with ±1.5 kHz receiver
`oscillator allowance and no offset, a flat filter bandwidth of
`±6 kHz is needed, or a two-peak filter bandwidth for this
`system of ± 3 kHz.
`When transmitter offset is used, not only does it degrade
`sensitivity at the postdetection slicing stage (see below), but
`clearly it also requires an increased noise bandwidth. While
`both flat and two-peak filters become wider, the latter does
`so at twice the rate of the former. Hence, with ± 1 kHz maxi-
`mum offset, the bandwidth ratio becomes ± 7 kHz to ± 5 kHz.
`The analysis by Hatton et al [14] assumes a receiver with
`noise characteristics of the type described in this paper.
`These results are summarised in Table 2.
`
`Table 2: Predetection bandwidth advantage
`of zero-l F system
`
`Receiver
`allowance
`ppm
`
`Transmitter
`allowance
`kHz
`
`Bandwidth
`advantage
`dB
`
`963
`
`1.5
`
`000
`
`± 1
`
`05
`
`10
`10
`
`conditions: ± 4.5 kHz deviation, 512 bit/s
`data, 150 MHz
`
`4.3 Demodulator characteristics
`The demodulator is fundamentally digital in nature, and so
`its output has only two states. Thus the output voltage is
`independent of the frequency deviation and also of any
`offset from the on-tune condition. The primary use of the.
`circuit is with the POCSAG [12] code, which is direct non-
`return-to-zero FSK. With such a DC coupled code, a fixed
`slicing level has to be adopted if no coding restrictions are to
`be imposed; this implies a reduced noise margin for data in
`one direction with a conventional demodulator when off
`tune. In the present case, no such reduction occurs for this
`reason.
`However, set against this is the fact that, if an error occurs,
`it is a full-height voltage step which will not be 'corrected'
`until the next correctly phased clock edge on the D-type.
`With the circuit as shown, this error pulse length would be on
`average half a cycle of the deviation frequency.
`This pulse length can be reduced by utilising a more com-
`plex circuit than that of Fig. 1, in which information is
`extracted from both the positive- and negative-going edges
`in both channels. Many circuits are possible, but of particular
`
`> I
`
`"J
`«r
`
`1,
`
`D Q
`Ck
`
`D C
`
`k Q
`
`I channel
`
`Q channel
`
`Fig. 4
`
`Improved digital demodulator circuit
`
`TCL EXHIBIT 1045
`Page 3 of 5
`
`

`
`Information is only updated when an edge occurs in one
`limiting amplifier output, and thus a variable edge jitter will
`result on the demodulated output pulses.
`For an instantaneous phase-continuous transition, this
`delay r will lie within the range
`
`0 < r<
`
`is the frequency deviation in the direction relevant
`where Aft
`to the edge being considered, and T will be uniformly distrib-
`uted within this range. Positive- and negative-going edges will
`only have equal peak jitter for the on-tune condition.
`In the case of FSK signals with shaped transitions, the
`maximum delay is the time at which 90 of phase shift has
`been accumulated. This may easily be found by integrating the
`rate of phase change to give the time, providing, of course,
`that the risetime shaping is well defined.
`Example
`For a signal with ± 4.5 kHz deviation in the on-tune condition
`with instantaneous transitions the jitter produced is from 0 to
`56/is. For a bit rate of 500 bit/s (i.e. a bit of 2ms), this
`represents an edge jitter of 2.8%.
`
`A second limitation may be due to the particular realisation
`of the demodulator process. The simple, one D-type, circuit
`considered in Section 2 only clocks on positive edges of one
`channel and hence has a maximum pulse edge delay of four
`times that calculated above for instantaneous transitions.
`(For shaped transitions, a smaller ratio will apply since the
`first 90° takes longer to accumulate than the subsequent
`phase quadrants.) Between the simplest circuit and the funda-
`mental limit of the phase sampling in the limiting amplifiers, a
`trade-off between complexity and operating speed may be
`made.
`As related to the typical paging example, it may be seen
`that the pulse distortion due to this cause can readily be kept
`below 10% and thus have a negligible effect on performance.
`However, this nonideality implies that there is a lower
`usable limit to the modulation index which may be used with
`the system. The value of the limit will be determined by the
`performance and design of the postdetection stages.
`
`4.5 Selec tivity and spurious responses
`It will readily be apparent from the discussion of Section 4.3
`that a correctly modulated signal on the adjacent channel will
`not be demodulated since it fails to cross the local-oscillator
`frequency. That is, the next channel rejection of this receiver
`is infinite, even with no channel filters. The lowpass filters are
`needed only to give the necessary blocking performance and to
`establish the noise bandwidth.
`This behaviour is particularly useful in paging systems
`
`Fig. 6 VHF radio receiver chip
`
`IEEPROC, Vol. 129, Pt. F, No. 1, FEBRUARY 1982
`
`where adjacent channel responses constitute false calls,
`whereas blocking results in lost calls, the former representing a
`greater nuisance to the user.
`Image rejection is similarly infinite, and input filtering is
`necessary only to ensure adequately low spurious responses
`to oscillator harmonics, and for protection against front-end
`blocking. It is possible to control both of these effects other
`than with an input filter; the blocking by designing for large-
`signal handling and the spurious by control at the oscillator.
`
`4.6 Spurious radia tion
`In the system described, the local oscillator is tuned to the
`input channel; thus not only is there no possibility of isolating
`it from the input by filtering, but also the antenna is peaked
`at this frequency. Suppression can be effected by three con-
`tributing factors:
`(a) low-level oscillator injection
`(b) high degree of balance in mixers
`(c) reverse isolation of RF stages.
`
`In practice, careful attention to detail has enabled this prob-
`lem to be solved with margin in hand.
`The integrated-circuit form provides further advantages in
`this respect. The miniaturised parts and connections mean that
`unintentional
`'antennas' are greatly reduced in radiating
`efficiency, affecting both transmission and reception from and
`to the circuitry.
`It should also be noted that, should there be any remaining
`local-oscillator radiation, it will be on the allocated channel
`only.
`
`5
`
`Monolithic realisation
`
`The receiver using the above architecture has been integrated
`on a single silicon chip some 2 mm by 2.5 mm which contains
`all the functions including local oscillator, RF stage, main
`gain blocks, demodulator, and data slicing circuit. This is
`then a true one-chip receiver having the antenna connected to
`one pin and fully filtered sliced data presented at another.
`Fig. 6 shows the chip, which has been designed to conservative
`rules
`to enable multisourcing
`in high-frequency bipolar
`processes.
`The primary advantage of the direct conversion receiver is
`that the off-chip component count is minimised and consists
`mainly of low-frequency decoupling capacitors and the two
`lowpass filters. About 20 components are needed to make a
`complete receiver.
`The use of integrated-circuit design techniques allows
`performance improvements to be obtained over simple discrete
`designs. For example, it allows the provision of such details
`as constant current operation over varying supply voltage to be
`included and stabilisation of current, voltage and temperature
`performance in the oscillator sections. Low power consump-
`tion is achieved by obtaining most of the circuit gain in the LF
`amplifiers, but even at the bandwidths used careful design is
`necessary to ensure stability. Note, for example, the 'ring-
`main' earth around the periphery of the chip. The circuit
`operates down to 1.8 V supply and draws some 2.5 mA when
`fully operational. In stand-by (battery save) mode, this current
`drain is reduced to 120/iA.
`
`6
`
`Conclusions
`
`A novel radio receiver architecture has been described which is
`suitable for large modulation-index frequency-shift keyed
`signals. It is also readily adaptable to an integrated-circuit
`design, even more so than previously published zero IF
`configurations.
`The combination of this new system with advanced inte-
`
`TCL EXHIBIT 1045
`Page 4 of 5
`
`

`
`STC who have contributed a wide range of skills on this
`programme and made it possible.
`
`8
`
`References
`
`1 TANABE, K., KANNO, M., SUZUKI, J., OKAMOTO, M.,
`MURAKAMI, D., OKUBO, T., and IDESAWA, M.: 'Development of
`VHF/FM radio front-end IC\ IEEE Trans., 1980, CE-26, pp. 677-
`692
`2 Plessey Semiconductors, data sheet for SL6690, 1980
`3 VANCE, I.A.W.: 'An integrated circuit v.h.f. radio receiver', Radio
`& Electron. Eng., 1980, 50, pp. 158-164
`4 VANCE, I.A.W., and NEALE, M.W.: 'Large scale integrated circuits
`for v.h.f. receivers'. IEE Digest 1980/41 conference on the impact
`of new l.s.i. techniques on communication systems, pp. 28-34
`5 GOATCHER, J.K., NEALE, M.W., and VANCE, I.A.W.: 'Noise
`considerations in an integrated circuit v.h.f. radio receiver'.
`Proceedings of conference on radio receivers and associated systems,
`1981, IERE no. 50., pp. 49-59
`6 KERWEIN, A.E., and STEIFF, L.H.: 'Design of a 150 Megacycle
`pocket receiver for the Bellboy personal signalling system,' Bell
`Syst. Tech. J., 1963, 42, pp. 527-565
`7 KASPERKOVITZ, D.: 'An integrated f.m. receiver', in KAISER,
`W.A., and PROEBSTER, W.E. (eds.): 'Electronics to microelec-
`tronics' (North Holland Publishing Co., 1980.), pp. 623-625
`(preprints of EUROCON '80)
`frequency-selective AM/FM
`8 GREBENE, A.B.: 'An integrated
`demodulator', IEEE Trans., 1971, 17, pp. 71-80
`9 MOORE, P.A., MURRAY, R.J., WHITE, P.D., and GARTER, J.:
`Surface acoustic wave filters for use in mobile radio'. Proceedings
`of conference on radio receivers and associated systems, 1981,
`IERE no. 50, pp. 19-28
`10 British Patent Specification no. 1 517 121
`11 MABEY, P.J.: 'Digital signalling for radio paging', IEEE Trans.,
`1981,VT-30, pp. 85-94
`12 TRIDGELL, R.H.: 'The application of coding techniques to radio-
`paging'. Proceedings of 1980 international Zurich seminar on digital
`communication, pp. C9.1-9.5
`13 MIZUKAMI, T., MASAKI, M., NAGATA, K., and HKOSAKA, K.:
`'NEC digital paging system'. NEC Research and Development
`no. 50. 1978, pp. 1-10
`14 HATTON, T., HIRADE, K., and ADACHI, F.: 'Theoretical studies
`of a simulcast digital radio paging system using a carrier frequency
`offset strategy', IEEE Trans., 1980, VT-29, pp. 87-95
`15 MITCHELL, D., and VAN WYNEN, K.G.: 'A 150 Me personal radio
`signalling system', Bell Syst. Tech. J., 1961,40, pp. 1239-1257
`
`Fig. 7 Miniature pocket pager
`
`grated design techniques has allowed the realisation of a true
`one-chip paging receiver capable of meeting stringent wide-area
`specifications, and operating throughout the VHF bands.
`In particular, the new equipment has exceptional spurious
`response rejection and high sensitivity.
`The resulting receiver (Fig. 7) is substantially smaller (only
`55cm 3) than would have been possible using conventional
`techniques and has a complete lack of screens, multiboard or
`hybrid-type construction. The production process has been
`deskilled by removing the radio-frequency critical compo-
`nents, and it is predicted that better reliability will be seen in
`service owing to the more compact form and the lower compo-
`nent count.
`It is clear that many other applications exist for this circuit
`and that significant advantages can be obtained in systems
`design given the availability of a truly mass-producible receiver.
`It seems reasonable to look forward to similar receivers for
`other modulation formats and specifications.
`
`7
`
`Acknowledgments
`
`I should like to thank my many team colleagues at STL and
`
`IEE PROC, Vol. 129, Pt. F, No. 1, FEBRUARY 1982
`
`TCL EXHIBIT 1045
`Page 5 of 5