United States Patent [191
`Meek et al.
`'
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,672,640
`Jun. 9, 1987
`
`[73] Assignee:
`
`[54] RADIO RECEIVER
`[75] Inventors: Thomas R. Meek, Harlow; Howard
`B. Butterfield, Bishops Stortford,
`both of England
`Standard Telephones & Cables Public
`Limited Company, London, England
`[21] Appl. No.: 706,396
`[22] Filed:
`Feb. 27, 1985
`[30]
`Foreign Application Priority Data
`Mar. 1, 1984 [GB] United Kingdom ............... .. 8405388
`
`[51] 1111. cu ......................... .................. .. H03D 1/22
`[52] vs. C]. .................................... .. 375/120; 375/39;
`375/81; 375/97; 329/124; 455/265
`[58] Field Of Search ................... .. 375/120, 88, 97, 80,
`375/81, 77, 39; 340/825.44; 455/228, 263, 265,
`259; 329/124, 50, 104
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,193,034 3/1980 Vance ................................. .. 375/88
`FOREIGN PATENT DOCUMENTS
`l5l7l2l 7/l978 United Kingdom .
`1563187 3/1980 United Kingdom .
`2099245 l/l982 United Kingdom .
`2109201 5/1933 United Kingdom .
`
`Primary Examiner-Robert L. Grif?n
`Assistant Examiner-M. Huseman
`Attorney, Agent, or Firm-Kerkam, Stowell, Kondracki
`& Clarke
`ABSTRACT
`[57]
`A radio pager for receiving FSK signals has optimally
`narrow gaussian bandpass ?lters (F1, F2) and a phase
`lock loop (11, 12, 13, 14) for preventing local oscillator
`drift controlled in dependence of the derivation fre
`quency ($4.5 KHz) which is accurately controlled at
`the transmitter and which is derived from the decoder
`logic circuit (20).
`A signi?cant increase in sensitivity is achieved over
`existing pagers.
`
`
`
`3,456,l96 7/1969 Schneider 4,193,033 3/1980 Voorman ............ ..
`
`7 Claims, 1 Drawing Figure
`
`HYBRID
`TRANSFORMER
`
`M
`
`AMPLIFIER
`
`TCL EXHIBIT 1040
`Page 1 of 5
`
`

`
`U. S. Patent
`
`Jun. 9,1987
`
`4,672,640
`
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`TCL EXHIBIT 1040
`Page 2 of 5
`
`

`
`1
`
`RADIO RECEIVER
`
`4,672,640
`2
`termined deviation frequency. The receiver includes
`?rst and second signal paths to which received radio
`signals are applied in quadrature, a local oscillator cir
`cuit for generating a local oscillating signal, means in
`each of the signal paths for mixing the local oscillator
`signal with the respective quadrature signal to produce
`a baseband signal, an optimally narrow guassian band
`pass ?lter for setting the passband and ?ltering noise in
`each of the signal paths connected to the output of the
`respective mixing means, means for generating a refer
`ence signal having a frequency corresponding to the
`predetermined deviation frequency, and a phase lock
`loop for controlling the local oscillator frequency. The
`phase lock loop is responsive to at least one of the base
`band signals and to the reference signal, and is operable
`to control the local oscillator frequency so as to main
`tain the baseband signal in phase lock with the reference
`signal.
`Thus a phase locked loop is used which locks on to
`the $4.5 KI-Iz deviation and this is accurately con
`trolled by the POCSAG transmitter. It is derived in the
`receiver from the decoder logic circuit, but the data is
`not extracted from the phase locked loop directly: this
`just sets the oscillator on frequency.
`
`BACKGROUND OF THE INVENTION
`This invention relates to a radio receiver and particu
`larly although not exclusively to a radio pager using a
`code format to the POCSAG standard, which is a Brit
`ish Post Of?ce Standard for digital data transmission.
`Our British Pat. No. 1517121 describes a radio pager
`c. 0
`for FSK signals and similar to the STC Model 5C pager.
`This pager is a tone-only receiver operating in the VHF
`high band (138-174 MHz). It uses a binary digital code
`format to the POCSAG standard, which provides the
`receiver with four addresses, each distinguished by a
`different alert tone pattern.
`In order to make it possible to produce the complete
`radio receiver on a single chip, a direct conversion
`technique is employed in which the radio frequency
`signal is mixed with a local oscillator on the nominal
`channel frequency, resulting in a “Zero I.F.”. Because
`the radio signal is frequency modulated there is in fact a
`beat frequency produced in the mixer, equal to the
`frequency deviation of the carrier. Conventional LF.
`strips are replaced by audio frequency ampli?ers with
`this technique, and adjacent channel selectivity is pro
`vided by low pass ?lters.
`To make it possible to recover frequency modulation,
`the radio frequency signal is fed to two paths with a 90
`degree phase difference between them. Each path has
`its own mixer, fed from the same local oscillator and its
`own low pass ?lter and limiting ampli?er. The phase
`relationship of the two baseband signals will vary ac
`cording to whether the radio carrier frequency is above
`or below the local oscillator frequency. The two base
`band signals are combined to recover the modulating
`signal in a D-type clocked ?ip-?op to the D-input of
`which is applied the output of one of the limiting ampli
`?er stages whilst the output of the other limiting ampli
`?er stage is applied to the clock input of the ?ip-?op.
`In the POCSAG radio-paging network, the binary
`data is modulated onto the r.f. carrier using F.S.K.
`modulation, as discussed above. The data rate is 512
`Bits/sec and a frequency deviation of 14.5 KHz is
`used. This high modulation index produces large con
`centrations of energy separated $4.5 KHz away from
`the r.f. carrier. The baseband (low pass) ?lters that are
`used in the homodyne (zero I.F.) radio-paging receiver
`only need to be bandpass ?lters centered on 4.5 KHZ
`and having a noise equivalent bandwidth of around 1
`KHz to produce optimum receiver detection perfor
`mance. However this argument assumes that the receiv
`er’s local oscillator is exactly on frequency or with a
`very small frequency offset (about 100 Hz). This cannot
`be achieved with a small, cheap crystal oscillator di
`rectly.
`A compromise solution adopted on the present
`Model 5C pager manufactured by Standard Telephones
`and Cables plc is to use a much larger noise equivalent
`bandwidth (6.5 KHz) to allow for crystal oscillator
`temperature drift and crystal aging. The ?lters then
`become band pass ?lters with a 6.5 KHz upper cut-off
`frequency, the lower cut-off being around 1 KHz, with
`associated loss of receiver sensitivity.
`
`BRIEF DESCRIPTOIN OF THE DRAWINGS
`In order that the invention can be clearly understood
`reference will now be made to the accompanying draw
`ing which is a circuit diagram of the radio receiver of a
`radio pager according to an embodiment of the present
`invention and simpli?ed to explain the main features of
`the invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`Referring to the drawing the input from the aerial A
`is fed to an r.f. ampli?er 1. The output from ampli?er 1
`feeds a hybrid transformer 2 which with associated
`components (not shown) provides the two signals in
`quadrature at the mixers 3 and 4.
`Mixers 3 and 4 have a local oscillator 5 providing
`inputs at 6 and 7 via a triplet stage 8. The outputs 9 and
`10 from the mixers are fed to respective 4.5 KHz gauss
`ian bandpass ?lters F1 and F2 each having a l KHz
`band width.
`The oscillator 5 is controlled by a crystal 11 which is
`voltage controlled. It can be tuned over a range of i3
`KHZ. An error voltage signal on line 12 is derived sum
`ming ampli?er 13 which receives a ?rst signal (100 Hz
`ramp waveform) from the decoder circuit 20 of the
`radio pager. This overcomes the very narrow locking
`range of 100 Hz, which now becomes 3 KHz. This ?rst
`signal is disabled when the phase lock loop circuit is in
`lock by a_ lock detector 14A which monitors the ana
`logue mixer 14 to see if it is between the supply rail and
`the zero rail, at which point lock can be assumed, and
`this controls a switch 13A which disables the sawtooth
`waveform so long as the circuit is in lock. A second
`signal is derived from a 4.5 KHz signal derived from the
`decoder logic circuitry 20 and mixed by mixer 14 with
`the signal from one of the mixers (6) to produce a con
`trol signal (0 Hz when in lock) which is ?ltered by a
`phase lock loop low-pass ?lter 15. The loop bandwidth
`is 100 Hz. Mixer 14 acts as a phase shift discriminator.
`The 4.5 KHz signal from the logic circuitry is inverted
`when the data output is high. Bit transitions on the
`output of mixer 3 may cause phase jitter on the phase
`
`40
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`SUMMARY OF THE INVENTION
`According to the present invention there is provided
`a homodyne radio receiver for receiving digital signals
`frequency modulated on an R.F. carrier having a prede
`
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`TCL EXHIBIT 1040
`Page 3 of 5
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`

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`4,672,640
`3
`shift discriminator output but this is reduced to an ac
`ceptably low level by the loop ?lter cut off.
`The outputs from the ?lters F1 and F2 feed the low
`gain high frequency limiter ampliers 16 and 17 whose
`signals are combined in the D-type ?ip-?op 18 to ex
`tract the data which is then fed to the decoder logic
`circuitry, indicated generally by reference numeral 20,
`via ampli?er 19. Conveniently the circuitry within the
`block marked LC. is in the form of an integrated circuit,
`as too would be the logic circuitry 20.
`The logic circuitry compares the received codewords
`with each of four addresses stored in a fusible link diode
`matrix 21. The circuity includes a master clock oscilla
`tor running at 32.768 KHZ.
`In addition the 4.5 KHz reference waveform to mixer
`14 is derived by frequency division and mixing of the
`32.768 KHz oscillator. This applies also to the 100 Hz
`ramp waveform which is applied to summing ampli?er
`13 and which is preferably derived by dividing the bit
`rate signal (256 Hz) by 2.5. The signal thus derived by
`division is then turned into a sawtooth waveform that
`sweeps the voltage controlled oscillator 5 and sets it in
`lock. This overcomes narrow locking range problems
`(set by loop ?lter cut-off).
`In the idle state of the pager, the logic circuit 20
`generates a battery saving sampling signal on line 22
`which switches on the current supply 23 for powering
`most of the current consuming circuitry in the receiver
`(as represented diagramatically by the broken lines) for
`about one tenth of a second in every second. During this
`time the received data is examined to see if a valid trans
`mission at 512 bits/sec is present. When valid data is
`detected the supply 23 is switched on continuously
`while the decoder circuit 20 looks for a synchronising
`codeword. Once found the battery saving signal on 22
`switches on the power only during synchronising code
`words and the two codewords constituting the frame in
`which the pager’s address falls. This mode continues
`until valid data ceases, when the pager reverts to the
`idle state. Should a synchronising codeword not be
`detected while valid data is still present, the battery
`saving will switch on again continuously until either a
`synchronising word is found or valid data ceases.
`During the frame in which the pager’s address oc
`curs, all received codewords are compared with all four
`possible stored addresses. If a match is found with all
`except zero, one or two bits different, then the code
`word is accepted as a valid call, and is registered in the
`appropriate one of four memory latches. If the pager is
`switched to the memory mode, then nothing further
`happens until the switch is returned to the ON position;
`but if it is already in the ON state, then the acoustic
`output of the call is started.
`The output signal to the person being paged is either
`stored or if switched on, bleeps according to the rele
`vant pattern depending on the message.
`A modi?cation to the receiver shown in the drawing
`will now be described. In the drawing the signal is taken
`off and mixed with 4.5 KHZ in mixer 14 to produce a
`phase-lock control signal. In the case where fast locking
`time is required a larger loop bandwidth is necessary.
`The loop bandwidth must be approx. 6 dB/octave roll
`off to ensure stable operation, so in the case of large
`bandwidth, considerable phase jitter may come through
`the ?lter due to the 180° phase changes at both transis
`tions in the data stream at point 6.
`To eliminate this the modi?cation proposes an extra
`mixer 30 added between output lines 9 and 10, (i.e.
`
`4
`between I and Q channels). This mixer now acts as the
`P.S.D. (phase‘shift-discriminator). Normally the output
`of this could drive the loop ?lter but this would result in
`the local oscillator sitting at 4.5 KHz above or below
`the proper carrier frequency. Mixer 14 is therefore
`retained and the output of the added mixer 30 drives
`mixer 14 via line 300, the previous connection to the Q
`channel being broken.
`This arrangement reduces phase jitter because the
`demodulator now acts like a Costas loop and the lock
`ing is performed on the “Sunde” signals. All other ele
`ments of the circuit remain the same. It should be noted
`that in the block I.C. representing the integrable com
`ponent both mixers 14 and 30 could be on or off the
`chip, as desired.
`The use of the phase locked loop and gaussian band
`pass ?lters in accordance with the invention advanta
`geously provides an improvement in receiver sensitivity
`of some 8dB over presently available pagers.
`We claim:
`1. A homodyne radio receiver for receiving digital
`signals frequency modulated on an RF. carrier having
`a predetermined deviation frequency, said receiver
`comprising:
`?rst and second signal paths to which received radio
`signals are applied in quadrature;
`a local oscillator circuit for generating a local oscilla
`tor signal;
`means in each of said signal paths for mixing the local
`oscillator signal with the respective quadrature
`signal to produce a baseband signal;
`an optimally narrow guassian bandpass ?lter for set
`ting the passband and ?ltering noise in each of said
`signal paths connected to the output of the respec
`tive mixing means;
`means for generating a reference signal having a fre~
`quency corresponding to the predetermined devia
`tion frequency; and
`a phase lock loop for controlling the local oscillator
`frequency, said phase lock loop being responsive to
`at least one of the baseband signals and to said
`reference signal and operable to control the local
`oscillator frequency so as to maintain the baseband
`signal in phase lock with the reference signal.
`2. A receiver as claimed in claim 1, which further
`comprises:
`means connected to the outputs of said optimally
`narrow gaussian bandpass ?lters for extracting data
`corresponding to received digital signals;
`decoding circuitry for decoding the extracted data,
`the decoding circuitry including a master clock
`oscillator operating at a clock frequency; and
`the reference signal being derived from the clock
`frequency.
`3. A receiver as claimed in claim 1, which further
`comprises:
`said phase lock loop including a discriminator to
`which said at least one of the baseband signals and
`said reference signal are applied, the discriminator
`output providing a control signal;
`means for generating a ramp waveform for increasing
`the locking range of said phase lock loop; and
`a summing ampli?er for summing the control signal
`and the ramp waveform to generate an error signal
`for controlling the local oscillator frequency.
`4. A receiver as claimed in a claim 3, wherein the
`ramp waveform input to the summing ampli?er is dis»
`abled when the phase lock loop is in lock.
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`5
`5. A receiver as claimed in claim 2, which further
`comprises:
`said phase lock loop including a discriminator to
`
`which said at least one of the baseband signals and
`
`said reference signal are applied, the discriminator
`
`output providing a control signal;
`
`4,672,640
`6
`a summing ampli?er for summing the control signal
`and the ramp waveform to generate an error signal
`for controlling the local oscillator frequency.
`6. A receiver as claimed in claim 5, wherein:
`said discriminator is a phase-shift discriminator; and
`wherein
`said reference signal input to the phase-shift discrimi
`nator is inverted when the extracted data has a
`predetermined logic state.
`7. A receiver as claimed in claim 5, wherein the ramp
`waveform input to the summing ampli?er is disabled
`when the phase lock loop is in lock.
`1K
`llK
`* lk
`it
`
`means for generating a ramp waveform for increasing
`
`the locking range of said phase lock loop; and
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`TCL EXHIBIT 1040
`Page 5 of 5