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`
`Application Of Zero-If Radio Architecture to Multistandard Compatible Radio Systems.
`
`Alfonso Femhndez-DurBn
`Tomks Sanjukn
`Mariano Perez
`Gregorio Nuiiez
`Alcatel Standard Elkctrica Madrid, Spain
`
`To overcome the above mentioned limitations, the
`obvious way is to develop an architecture which is
`more suitable for integration, in which the number of
`oscillators is reduced, and the IF functions (With
`associated passive filters) are suppressed, shifting the
`most important multistandard operations
`to
`the
`Baseband (preferably processed in low cost digital
`CMOS circuits) is the Zero-IF.
`
`2. Objectives
`
`The main objectives of GIRAFE project can be
`summarized in the following items.
`
`Develop a library of integrable and reusable
`radio frequency building blocks applicable to
`UMTS, based on multistandard evolution from
`second
`generation
`systems
`(DECT,
`GSM/DCS 1800, INMARS AT M).
`
`Develop an integrated radio frequency front-end
`based on combinations of the above building
`blocks, for the multistandard operation based on
`second
`generation
`systems
`(DECT,
`GSWDCS 1800, INMARSAT M).
`
`Develop novel techniques for low cost, high
`volume packaging for RF integrated front end
`applications.
`
`Develop an electroless chip bumping process to
`minimize RF parasitics.
`
`Develop a TAB/flip chip assembly process.
`
`3. Technical approach
`
`3.1. Project development methodology.
`
`The GIRAFE project Development Methodology is
`depicted in the next diagram:
`
`Abstract
`
`This paper covers the results of the radio architecture
`studies towards common multistandard compatible
`radio front-ends carried out within the RACE Project
`2123 GIRAFE (Gigahertz Radio Front Ends) which
`is a research project
`in
`the area of mobile
`telecommunications focused on the application of
`advanced microelectronics integration and packaging
`techniques for RF components to be used in terminals
`of future mobile communications systems. These
`terminals will be based on combinations of available
`second generation
`systems
`in Europe
`(GSM,
`DCS1800, DECT and INMARSAT). The objective is
`to create a set of RF building blocks (RX and TX
`mixers, 90" phase shifters, VCO and prescaler) and
`develop multistandard RF
`front-ends
`in high
`frequency bipolar process, complemented by the
`investigation and adaptation of novel packaging
`techniques which have a major
`impact
`in
`manufacturing
`low
`cost,
`high
`volume RF
`components.
`
`1. Introduction
`
`One of the most critical points to overcome in
`multistandard terminals for mobile and personal
`communication systems is to find the maximum
`number of commonalties to allow the highest possible
`degree of integration, under the constraints of low
`voltage and low power consumption. The starting
`point for multistandard terminals is to set-up a
`common radio architecture capable to afford the
`various standards (typically 2, but more could be
`possible). In fact, the most typical architecture of a
`the so called "Radio with
`radio subsystem
`is
`intermediate frequency". Cost and consumption is
`directly related with the number of stages and also the
`need of passive components (Mainly filters). Today
`almost all digital mobile communication terminals are
`based on that architecture (DECT, GSM, DAMPS,
`CDMA ...). In that case the level of integration is
`limited by
`the presence of passive intermediate
`functions (Image and channel filters...), oscillators
`and a certain amount of HF and IF stages (Use of
`bipolar technology with reduced densities). This
`makes that architecture not
`to be optimal for
`multistandard compatibility
`
`Radio Receivers and Associated Systems, 26-28 September 1995, Conference Publication No 41 5 0 IEE 1995
`
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`82
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`between these stages usually contain analog and
`passive filters (e. g. Surface Acoustic filters) that
`have relative big size and high cost. Cost and
`consumption are therefore directly related with the
`number of stages and also the need of passive
`components (Mainly filters). Nawdays most of the
`digital mobile communication terminals are based on
`that architecture (DECT, GSM, DAMPS, CDMA ...).
`
`-7
`
`U
`
`Figure 1. Project development methodology
`of GIRAFE project.
`
`As it can be seen in said diagram, the project
`is based on two lines of contributions namely:
`
`Figure 2. Classic heterodyne receiver
`
`- System and specification inputs.
`- Technological inputs
`- Bipolar Development.
`- Packaging.
`
`As it is reflected in the work break down of the
`project, there is an initial system specification coming
`from the reference systems (DECT, GSM/DCS 1800,
`INMARSAT M). The specifications are used to
`discuss the compatibility opportunities derived from
`the Front End architectures taken in conjunction with
`the process capabilities. The latter reisults is a set of
`common specifications of a RF Front End covering
`architectural, system and preliminary design issues.
`This
`information
`together with
`the packaging
`intermediate results and the SPICE plarameters, feed
`the bipolar RF design. The design results are sent to
`the foundry to complete the first silicon run. The
`outcome of the run composed of the RF front end
`building blocks together with the packaging passes to
`a first test phase in which the specifications are
`verified. The results of the first test phase are use in
`the redesign phase to proceed with the second and
`last silicon iteration of the project.
`
`3.2. Radio architecture.
`
`Two different radio architectures are considered in
`this project, namely zero IF and Image rejection, this
`paper is focused mainly on the first aine, so hereafter
`the references will be based on the comparison to
`said architecture (Zero IF).
`
`3.2.1 Radio with intermediate frequlency
`
`subsystem
`raldio
`typical
`a
`shows
`Figure 2
`traditional structure is called
`architecture. That
`"Radio with intermediate frequency". In this well
`known architecture the information :signal is shifted
`from the RF carrier to the baseband by means of
`several mixing or down conversions. The boundaries
`
`In that case the level of integration is limited by the
`use of said passive components and intermediate
`functions (Image and channel filters...), oscillators
`and a certain amount of HF and IF stages (Use of
`bipolar technology with reduced densities).
`
`3.2.2 Reference Zero-IF architecture
`
`To overcome the above mentioned limitations, the
`obvious way is to develop an architecture which is
`more suitable for integration, in which we suppress
`the IF functions (With associated passive filters) and
`reduce the number of oscillators.
`Such an architecture is presented in Figure 3, where
`the simplification is obvious in comparison with the
`block diagram of figure 2.
`With zero IF we state :
`- Limited number of RF stages and no
`
`IF stages
`
`IF stages)
`
`- oscillators can be reduced to one
`- power consumption optimized (No
`
`- Limited number of passive (And
`expensive) components
`The major part of analog functions are working in
`low frequency range, where
`it is must easier to do
`integration. For examp!e with IF a channel filter uses
`SAW technology: with zero IF the equivalent filter
`can be implemented in a CMOS chip (# 3mm2 with a
`0,8 pm process).
`But zero IF shows 2 major drawbacks which must be
`compensated :
`
`- Offset
`- Leakage of local oscillator
`
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`83
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`The second drawback is solved by high quality
`techniques, as well as good reverse
`shielding
`isolation in mixers and LNA.
`
`The first one requires compensation techniques which
`relatively complex, but whose level of integration is
`possible with CMOS.
`
`Figure 3.Zero-IF Architecture in the scope of
`GIRAFE
`
`3.3. RF front-end architecture for a dual mode
`terminal
`
`Recently the idea of migration or evolution from the
`second generation systems towards UMTS contrary
`to the revolution (i.e. brand new system) has gained
`importance, therefore the design of components
`capable to operate under multistandard conditions
`appears to be a key issue to reduce the gap between
`the UMTS and the second generation systems in
`terms of implementation.
`
`Taking the GIRAFE approach to radio architecture
`described in the above sections, in which three major
`subsystems are identified, namely: primary front-end,
`radio front-end itself and low frequency or baseband
`processing,
`the maximum set of commonalties
`between
`the different specifications have been
`defined.
`
`In the primary front-end, the low noise amplifier
`(LNA), power amplifier (PA) and a set of duplexers
`or switches appear to be strongly dependent on the
`specific system. To achieve a LNA capable to operate
`in the worst case of noise requirements, but with
`sufficient bandwidth
`to cover several systems
`becomes more expensive than simply duplicate the
`circuitry. On the other hand something similar
`happens to the PA, different systems require strongly
`solutions, e. g. depending on
`different
`the
`modulation, the PA must be class AB, class C, etc.,
`and again the circuit duplication appears to be the
`cost effective solution.
`
`The front-end concept in GIRAFE covers the radio
`processing elements that can be made multistandard
`i. e. mixers, phase shifters, VCO and PLL (the tatter
`
`two with some restrictions), under the scope of
`optimal cost, size and power consumption.
`
`The Figure 3 shows also
`the approach
`multistandard terminals under the GIRAFE scope.
`
`to
`
`considerations
`General
`specifications.
`
`on
`
`the
`
`system
`
`GIRAFE is based on an original architecture with
`zero IF. Use of that architecture is yet very limited,
`and no circuits using that technique (for a cellular
`application) exist working with a low power supply
`(3V).
`
`Due to the specific requirements of the front end
`functions, the building blocks namely Rx mixed, Tx
`mixer, Phase Shifter, VCO, and prescaler must be
`specifically designed. The Phase shifter can be
`common for Rx and Tx, but for the mixers, the
`following main differences appear:
`
`RX (Down-conversion)
`
`Dynamic range: Very high (in the order of 80 to 90
`dB). The mixer has to accept a very wide range of
`signals, which, to make things even worse, are
`previously amplified by an LNA.
`Noise Figure: must be as low as possible in order not
`to contribute to the overall noise of the down-
`converter.
`Frequency conversion: Input high frequency, output
`low frequency. This implies that the frequency
`response
`is very good, and there
`is normally
`conversion gain.
`Power consumption: Relatively low.
`
`TX (Up-conversion)
`
`Dynamic range: Low. Normally the input amplitude
`is controlled inside the system.
`Noise Figure: Medium, Not a very critical factor in
`up-conversion.
`Frequency conversion: Input low frequency, output
`high frequency. This situation is very difficult to
`handle by integrated mixers, and normalIy there is
`conversion loss.
`Power consumption: Relatively high. In order to
`minimise the conversion gain loss, a high current
`level must be maintained in the circuit.
`
`Therefore the Rx and Tx mixers designs must be
`to optimize for specific requirements,
`different
`consequently no effort should be done to find a
`common scheme for Rx and Tx, the designs should
`be optimize for the function.
`
`3.4. Technological developments
`
`The major trend of the electronics assembly industry
`is towards bare-chip assembly on high performance
`circuit boards. TAB and flip-chip, particularly flip-
`chip, give higher interconnection density, higher
`assembly yields, smaller assembly size and better
`electrical performance
`than conventional wire-
`
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`

`
`bonding. If TAB or flip-chip are combined with
`direct chip assembly on the circuit board, rather than
`by way of a plastic or ceramic packagle, packing
`density is greatly increased and electricall parasitics
`are decreased, thereby increasing operatiing speeds
`and electrical performance. For RF applications,
`wire-bonds, due to their variability in length and in
`spatial position, have inherently unpredictable values
`of R, L (self + mutual) and C (self + mutual). If TAB
`or flip-chip is used for chip assembly, this variability
`is completely eliminated and, if flip-chip on board is
`used,
`the electrical parasitics of
`the chip U 0
`connection drop to almost zero. There is 1,hus strong
`motivation for using bumped chips, and flip-chip in
`particular.
`
`It is a goal of GIRAFE project to develop low cost
`packaging and connection
`techniques
`for RF
`application as mentioned above.
`
`4. Design activities.
`
`The aim for the design from the specification of each
`basic-cells in the GIRAFE Project is the following:
`
`- Regarding the different existing system, a first
`research give a list of cells which are common to all
`of these systems, and can be consider as essential to
`built an architecture. The list is the following :
`* TX-Mixer
`* RX-Mixer
`* Phase-Shifter
`* vco
`* Prescaler.
`
`these basic-cells, an overall
`- For each of
`specification as been done, to obtain the most
`common figures on each item for each systems. This
`gives target Specification for each cells.
`
`- Each cell is designed following these specification.
`For example, a new circuitry has been found to built
`the RX-mixer, because the classical solutiion can't be
`used (Power supply is very low).
`- To reach the specification described above, we must
`now consider the system(s) where these cells will be
`used. Then we introduce the Min and Max Level, the
`gains, the switching mode for power-moide, the IP3
`or IM3 level, ...
`
`Some glue circuitry has to be added to the basic-cell
`to obtain a cell with a "Multi-Standard'' possibility of
`use.
`
`level, we can built some simplified
`this
`At
`components for testing the design. This has been
`done for the VCO. and the Prescaler.
`
`The GIRAFE project will stop at this level, for the
`cell point of view as shown in Figure 4.
`
`84
`
`GIRAFE PROJECT
`
`Girafe in the development cycle
`
`Figure 4. GIRAFE in the development cycle.
`
`But to make an chip, related to an architecture, for
`building a terminal, we now need to put these cells in
`a single silicon, and to interconnect them.
`
`Some new glue circuitry has to be added for the
`interface of each cell with the others, and for the
`interface level with the extemal world (LNA, Power
`Amplifier AGC strategy, power supply mode,
`switching and activation mode, ....)
`
`This part is necessary to obtain a circuit that can be
`tested, regarding some hard specification that can be
`measure only at this level (for example: Noise
`,harmonic rejection for the all system, phase and
`frequency errors, etc...).
`
`The building blocks that are considered in the project
`are: TX mixer, RX mixer, Phase shifter, VCO and
`PLL. But integrated multistandard front-ends are also
`under development, for this reason some additional
`circuitry has to developed for bias and RF adaptation
`both under
`the
`low voltage and
`low power
`consumption.
`
`5. Summary
`
`The availabiIity of building blocks for low cost Radio
`Front Ends capable to operate in the 2 Ghz band with
`power supply in the range of 3 volts and low power
`consumption
`is a mandatory step for a mobile
`communication system be integrated in the consumer
`market. In the context of evolution towards the third
`generation mobile systems the outcome of GIRAFE
`project will facilitate the transition from the second
`generation systems to UMTS by contributing to the
`implementation of multistandard terminals. Covering
`the implementation of specific building blocks (Up
`and Down converter Mixers, phase shifter, VCO,
`Prescaler) as well as complete front-ends for such
`multistandard terminals based on combinations of
`three second generation systems namely DECT,
`GSM/DCS and INMARSAT M, said emphasis on the
`compatibility and multistandard operation, opens a
`smooth evolution or migration towards UMTS.
`
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`

`
`Acknowledgments
`
`To the European Commission DGXIII B for the
`financial support including this project in the
`Mobile Project Line of the RACE I1 programme.
`To the GIRAFE consortium as a whole for their
`professional and high quality contributions.
`
`Alcatel Standard Electrica
`Spain
`Alcatel Mobile Communications France
`France
`Alcatel Bell Telephone Manufacturing
`Belgium
`Nera Satcom Division
`Norway
`Swindon Silicon Systems Limited
`UK
`National Microelectronics Research Centre
`Ireland
`Universidad Polittcnica de Madrid
`Spain
`
`Bibliography
`
`[ 11 ETSI SMG5 TDoc 153194
`[2] ETSI SMGS TDoc 358/94
`[3] ETSI SMGS TDoc 269/94
`[4] ETSI SMG5 TDoc 337/94
`[5] ITU Doc 8-1/Temp/S-E
`[6] Mobile Telecommunications: Technological,
`Industrial and Usage Trends (RMR study for DG 111,
`European Commission)
`[7] Scenario Mobile Communications 2010, Eutelis
`(final report for DGXIII, European Commission)
`[8] Personal Communications Transceiver
`Architectures for monolithic Integration.
`E. Boneck and al., PIMRC94.
`
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