United States Patent [191
`Mohindra
`
`llllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`5,584,068
`Dec. 10, 1996
`
`US005584068A
`[11] Patent Number:
`[45] Date of Patent:
`
`[54] DIRECT CONVERSION RECEIVER
`
`[75] Inventor: Rishi Mohindra, Eindhoven,
`Netherlands
`
`[73] Assignee: U.S. Philips Corporation, New York,
`NY.
`
`[21] Appl. No.: 520,330
`[22] Filed:
`Aug. 28, 1995
`
`Related U.S. Application Data
`
`[63] Continuation of Ser. No. 148,105, Nov. 3, 1993, abandoned.
`[30]
`Foreign Application Priority Data
`
`Nov. 26, 1992 [EP]
`
`European Pat. OH. ............ .. 92203653
`
`[51] Int. Cl.6 ..................................................... .. H04B 1/26
`[52] U.S. Cl. . ................ .. 455/324; 455/1822; 455/1922;
`375/344
`[58] Field of Search ............................ .. 455/1821, 182.2,
`455/1831, 183.2, 192.1, 192.2, 257, 259,
`260, 265, 324, 256; 375/97, 80, 83, 84,
`81
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`8/1982 Waters .................................... .. 375/81
`4,344,178
`6/1987 Marshall et a1. ..
`375/88
`4,672,636
`4,871,975 10/1989 Nawata et al.
`329/124
`4,989,220
`l/199l Serrone ................................... .. 375/83
`
`l/1993 Ishizu ...................................... .. 375/86
`5,179,578
`5,365,185 11/1994 Bar-David .
`5,438,692
`8/1995 Mohindra .............................. .. 455/324
`
`FOREIGN PATENT DOCUMENTS
`
`0298484 2/1992 European Pat. Olf. .
`2180419 3/1987 United Kingdom .
`Primary Examiner—Andrew Faile
`Assistant Examiner-Lee Nguyen
`Attorney, Agent, or Firm—Michael E. Marion
`[57]
`ABSTRACT
`
`A direct conversion receiver for FSK modulated digital
`signals has two quadrature signal paths (1, Q) and an a.f.c.
`loop for controlling a local frequency generator. A control
`signal for the a.f.c. loop is produced by an offset frequency
`detector, and is in the form of a unipolar series of pulses
`having an average value which is proportional to the offset
`of the local frequency with respect to the carrier frequency
`of the signal being received. The olfset frequency detector
`derives such control signal based on the difference between
`phase-shifted cross-products of the signals in the l and Q
`paths. This achieves fast a.f.c. loop response, improving the
`perfonnance of the receiver, and permits a simpler loop ?lter
`for achieving the requisite signal averaging. The receiver
`also includes an out-of-range detector for detecting when the
`local frequency is outside a predetermined window with
`respect to the carrier frequency of the received signal, in
`which case the a.f.c. control signal is derived from the
`average level of data in the received signal rather than from
`the o?set frequency detector.
`
`8 Claims, 4 Drawing Sheets
`
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`Ex. 2008
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`Page 1 of 12
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`

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`US. Patent
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`Dec. 10, 1996
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`Sheet 1 of 4
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`5,584,068
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`Page 2 of 12
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`U.S. Patent
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`Dec. 10, 1996
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`Sheet 2 of 4
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`US. Patent
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`Dec. 10, 1996
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`Sheet 3 0f 4
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`U.S. Patent
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`Dec. 10, 1996
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`Sheet 4 of 4
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`1
`DIRECT CONVERSION RECEIVER
`
`This is a continuation of application Ser. No. 08/148,105
`?led Nov. 3, 1993 abandoned.
`
`BACKGROUND OF THE INVENTION
`
`1. Related Application
`This application is related to Applicant’s copending appli
`cation Ser. No. 133,546, ?led Oct. 2, 1993, PHN 14,285,
`assigned to the same assignee.
`2. Field of the Invention
`The present invention relates to a direct conversion
`receiver comprising a local frequency generating arrange
`ment which is coupled to a pair of quadrature related mixers
`for mixing down an rf input signal to quadrature related
`signals, and a.f.c. means for providing a control signal for
`the local frequency generating arrangement, the a.f.c.
`means, which are coupled to quadrature paths, comprising a
`frequency oifset detector for deriving a frequency control
`signal having an average value which is proportional to the
`frequency offset of the local frequency generating arrange
`ment with respect to the rf input signal. The frequency offset
`detector comprises a series arrangement of a phase shifting
`arrangement and a multiplication arrangement in a quadra
`ture path. Such direct conversion, receivers can be digital
`paging receivers or transceivers using an FSK (Frequency
`Shift Keying) modulation scheme, but also transceivers for
`cordless telephony or the like.
`3. Description of the Related Art
`A direct conversion receiver of this kind is known from
`the European Patent EP 298 484 B 1. In the known direct
`conversion receiver, which is an optical receiver, arl a.f.c.
`(automatic frequency control) signal for a local oscillator
`with inherent correct polarity is derived from so-called I
`and Q-channel receiver paths. For this purpose, a baseband
`I-channel signal is fed to a frequency offset detector,
`together with a quadrature related Q-channel signal. The
`frequency o?set detector is a series arrangement of a phase
`shifting arrangement and a multiplication arrangement,
`whereby the Lchannel signal is fed to an input of the
`multiplication arrangement, and the Q-channel signal is fed
`to another input of the multiplication arrangement via the
`phase shifting arrangement. The output signal of the detector
`is used as a control signal which is fed to the local oscillator
`via a low pass ?lter. In the known receiver the control signal
`is a bipolar signal, which is subject to a relatively strong low
`frequency ripple component.
`
`20
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`25
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`30
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`40
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`45
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`SUMMARY OF THE INVENTION
`
`It is an object of the present invention to provide a direct
`conversion receiver having an improved performance, and
`imposing less demand upon signal averaging in the low pass
`loop ?lter.
`To this end a direct conversion receiver according to the
`present invention is charactetised in that the frequency
`detector comprises a further series arrangement of a phase
`shifting arrangement and a multiplication arrangement in
`another quadrature path, and a subtracting the arrangement
`for subtracting output signals of the two multiplication
`arrangements, whereby inputs of the multiplication arrange
`ments are cross-coupled to the quadrature paths, and other
`inputs of the multiplication arrangements are coupled to the
`quadrature paths via the phase shifting arrangements. In the
`receiver according to the present invention the control signal
`
`55
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`65
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`2
`comprises a considerable higher tipple frequency compo
`nent as compared with the known receiver, and so a suc
`ceeding low pass ?lter for ?ltering the control signal can
`have a much higher cut-off frequency. Consequently the
`a.f.c. loop has a faster response, which is advantageous for
`quick frequency lock and also for scanning frequency chan
`nels. For an appropriate response the ?lter cut-off frequency
`should not become too low with respect to the ripple
`frequency of the control signal i.e. a trade—off has to be made
`between a fast loop response and a clean a.f.c. signal. When
`using a direct conversion receiver according to the present
`invention e.g. as an FSK data paging receiver for high
`frequencies such as in the 900 MHZ band, use of expensive
`temperature compensating schemes for compensating fre
`quency drift of a crystal oscillator in such a receiver as is
`necessary in conventional paging receivers, is also avoided.
`Although the phase shifting arrangement and the multi
`plication arrangement can be implemented by using analog
`circuits, in a simple embodiment the phase shifting arrange
`ment is a shift register and the multiplication arrangement is
`an exclusive-OR. In such an embodiment, the phase shifting
`arrangement has a phase shift proportional to frequency, i.e.
`is a time delay arrangement.
`An alternative embodiment of a direct conversion receiver
`according to the present invention comprises a microcon
`troller functionally implementing the series arrangements
`and the subtracting arrangement, and digital-to-analog con
`version means and/or digital output means for providing the
`control signal. Such an embodiment is particularly advan
`tageous if the direct conversion receiver comprises a micro
`controller with digital I/O-channels and/or a digital-to-ana
`log converter for other purposes, and such resources can be
`shared for implementing the present invention. The shared
`resources can be multiplexed, then.
`In a further embodiment of a direct conversion receiver
`according to the present invention, the control signal is fed
`to the local oscillator via an analog or digital integrator or
`via an analog or digital low pass ?lter. Thus, the a.f.c. loop
`dynamics can be easily controlled. Using an integrator
`achieves a zero steady state response. The digital embodi
`ment is particularly advantageous if microcontroller
`resources can be shared, as mentioned above.
`For a.f.c. range extension, the direct conversion receiver
`according to the present invention comprises a data demodu
`lation arrangement in parallel with the offset frequency
`detector for providing data from the quadrature related
`baseband signals, a data ?lter for providing ?ltered data, and
`an out-of-range decision arrangement coupled to the data
`?lter via an averaging ?lter. The decision arrangement
`controls a switching arrangement for switching an output
`signal of the offset frequency detector as the control signal,
`or the ?ltered data as the control signal. Such a range
`extension, e.g. in an FSK receiver, is necessary if the
`frequency of the local oscillator drifts close to or beyond the
`frequency deviation of the received r.f. FSK data signal. The
`out-of-range decision arrangement, which can be a window
`comparison arrangement, detects such an out-of-range con
`dition, and the ?ltered data is taken as an a.f.c. control signal
`instead of an output signal of the offset frequency detector.
`Such an out-of-range detection is particularly effective if the
`number of ones and zeroes in the FSK signal is approxi
`mately equal, on the average. The out-of—range detection can
`also be a software based decision arrangement implemented
`with a microcontroller, which checks data validity or other
`signal parameters like signal frequency for taking an out
`of-range decision. In case of checking signal frequencies,
`checking a frequency of the product signal of the I and Q
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`Page 6 of 12
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`channels, i.e. checking a double frequency, achieved more
`accurate measurement than checking the frequency of an I or
`Q channel alone. Checking data validity can be based on a
`valid CRC (Cyclic Redundancy Code), a BER (Bit Error
`Rate), or the like.
`An embodiment of a direct conversion device according
`to the present invention comprises bandpass ?lters in the
`respective quadrature paths, wherein for a.f.c. out-of-range
`extension the bandpass ?lters are stopband ?lters stopping a
`band substantially from DC, or wherein for out-of-range
`extension the direct conversion receiver comprises highpass
`?lters coupled to the quadrature paths, whereby the com
`bined bandpass and highpass ?lters form stopband ?lters,
`and wherein the phase shifting arrangements have a non
`linear shifting characteristic approaching a predetermined
`phase shift with increasing frequency. The stopband or
`frequency gap is chosen such that for a zero offset frequency,
`the received signal frequency just falls outside the gap,
`whereas for an offset beyond the frequency deviation of the
`input rf signal one of the FSK data “0” and “1” frequencies
`falls inside the gap. It is thus achieved that the gap sup
`presses a signal that would otherwise pull the a.f.c. into the
`wrong direction.
`An embodiment of a direct conversion device according
`to the present invention comprises ?lters in the respective
`quadrature paths, wherein for a.f.c. out-of-range extension
`the phase shifting arrangements have a non-linear phase
`shifting characteristic changing from a ?rst predetermined
`phase shift to a second predetermined phase shift with
`increasing baseband frequency around a predetermined
`baseband frequency (which could also be Af, Af being a
`frequency deviation). Thus always a correct polarity a.f.c.
`signal is achieved. For a frequency offset beyond twice the
`frequency deviation both a correct polarity and non-reduced
`a.f.c. loop gain is achieved, whereas for a lower o?'set some
`a.f.c. loop gain reduction occurs.
`
`4
`FIG. 10 shows a phase shifting characteristic in another
`embodiment of the present invention, and
`FIG. 11 shows another embodiment of a phase shifting
`arrangement.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`FIG. 1 schematically shows a direct conversion receiver
`1 according to the present invention. The direct conversion
`receiver 1, which can be a paging transceiver, comprises an
`antenna 2 for receiving an rf (radio frequency) input signal
`rf, which can be an rf FSK (Frequency Shift Keying) signal
`carrying FSK modulated digital signals. The rf input signal
`rf is fed to a low noise rf ampli?er 3, which is coupled to
`quadrature paths 4 and 5, so-called I- and Q-channels, for
`mixing down the rf input signal rf to quadrature related
`baseband signals I and Q. The quadrature path 4 comprises
`a phase shifting device 6 causing a +45 degrees phase shift
`of the ampli?ed rf signal. The phase shifting device 6 is
`coupled to a mixer 7 for mixing down the rf signal rf to the
`baseband signal I, an output of the mixer 7 being ?ltered and
`limited by means of a respective ?lter 8 and a limiter 9.
`Similarly, the quadrature path 5 comprises a phase shifting
`device 10 causing a ~45 degrees phase shift of the ampli?ed
`rf signal, a mixer 11, a ?lter 12, and a limiter 13 for
`achieving the baseband signal Q. The ?lters 8 and 12 are
`provided for limiting the noise bandwidth and for channel
`selectivity. By AC-coupling of the ?lters 8 and 12 to the
`mixers 7 and 11, DC~offset effects are avoided. The limiters
`9 and 13 are provided for removing amplitude signal varia
`tions. The mixers 7 and 11 are further coupled to a local
`frequency generating arrangement, eg a crystal oscillator
`14 having a crystal 15 as a frequency determining element,
`via a frequency multiplication arrangement 16. The local
`frequency generating arrangement 14 can also be a more
`elaborate arrangement, e.g. a frequency synthesizer having
`a crystal oscillator for providing a reference frequency. Such
`frequency synthesizers can operate on the basis of a PLL
`(Phase Locked Loop). In a direct conversion receiver the
`mixing frequency, ie an output frequency fL of the multi
`plication arrangement 16, further denoted as oscillator fre
`quency, is chosen such that baseband zero-intermediate
`frequency signals I and Q are obtained, for a ?ctitious canier
`fc. Instead of two phase shifting devices, with +45 degrees
`and —45 degrees phase shifting, respectively, a single 90
`degrees phase shifting device can be applied, for phase
`shifting the oscillator signal for one of the mixer signals. For
`example for FSK modulated rf signals with a frequency
`deviation of +4 kHz and —4 kHz around a 900 MHz carrier
`frequency fc, the carder not physically being present in the
`received rf input signal rf, representing logical “0” and
`logical “l” transmitted signals, the baseband signals I and Q
`are 4 kHz signals, though di?ering in phase, if f :fc. In case
`of a frequency offset of the oscillator frequency fL with
`respect to the rf input signal rf, and so also with respect to
`the canier frequency fc, the baseband signals I and Q have
`di?’erent frequencies. According to the present invention, the
`direct conversion receiver 1 comprises a.f.c. means coupled
`to the quadrature paths 4 and 5 comprising an o?’set fre
`quency detector 17 for delivering a signal dct as an a.f.c.
`control signal for the local oscillator 14, a DC (Direct
`Current) component of the signal dct being proportional to
`the frequency offset f L—fc. The frequency detector 17 com
`prises two series arrangements of a phase shifting arrange
`ment and a multiplication arrangement, and also a subtract
`ing or adding arrangement, to be described in detail with
`
`30
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`35
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention will now be described, by way of
`example, with reference to the accompanying drawings,
`wherein
`FIG. 1 schematically shows a direct conversion receiver
`according to the present invention,
`FIG. 2 shows an embodiment of an offset frequency
`detector and out-of-range detection means according to the
`present invention,
`FIG. 3 shows a window comparison arrangement as an
`out~of-range decision arrangement according to the present
`invention,
`FIG. 4 shows effects on baseband frequencies for various
`frequency o?‘sets,
`FIG. 5A and 5B show digital output signals of a prior art
`offset frequency detector and an offset frequency detector
`according to the present invention, respectively,
`FIG. 6 shows an average of a ?ltered data signal as a
`function of a frequency deviation of a local oscillator with
`respect to a carrier frequency of an FSK signal,
`FIG. 7 shows a frequency characteristic of a ?lter in an
`embodiment of the present invention,
`FIG. 8 shows a phase shifting characteristic in an embodi~
`ment of the present invention,
`FIG. 9 shows an embodiment of a phase shifting arrange
`ment of the present invention,
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`reference to FIG. 2. The signal dct is fed to the local
`oscillator 14 via a smoothing arrangement 18, being an
`analog or digital integrator, or the analog or digital low pass
`?lter, i.e. an actual control signal ct being the smoothed
`signal dct. The signal dot can be an analog or digital signal,
`depending whether or not the quadrature paths comprise
`limiters. Poles and zeroes of the smoothing arrangement 18
`or smoothing ?lter determine the a.f.c. loop dynamics. From
`the practical point of view, a ?lter cut-off frequency could be
`in a range between a ripple frequency of the digital signal
`dot divided by 1000, and the frequency of the digital signal
`dot divided by 20, a trade-off being made between a noisy,
`but fast loop, and a slower, but more stable loop. A fast loop
`response is required for fast channel scanning or for fast
`locking. Thus, a higher ripple frequency allows for a better
`overall performance. The present invention achieves an
`a.f.c. control signal with an inherent correct polarity, obvi
`ating the need for multiplication with demodulated data,
`such as in other prior art receivers, e.g. as disclosed in GB
`2 180 419. Furthermore, as compared with known receivers
`using crystal oscillators without applying an a.f.c. control
`signal thereto, no complicated temperature drift compensa
`tion schemes are necessary. E.g., a less than 2.8 ppm
`temperature drift or aging drift compensation in such known
`receivers in the 900 MHZ band would be expensive or even
`impractical in paging receivers. The present invention pri
`ority using crystals without temperature compensation. The
`offset frequency detector 17 can be implemented analogly or
`digitally. For obtaining demodulated data, the direct con
`version receiver 1 comprises a demodulator 19 to which the
`baseband signals I and Q are fed. The demodulator 19 can
`be a lead-lag phase detector for demodulating FSK data. The
`demodulator is coupled to a microcontroller 20 with RAM
`and ROM memory and digital and/or analog I/O-interfaces.
`Such microcontrollers are well known in the art. For paging
`transceivers, various output signals may be provided for
`such as a signal via an amplifier 21 and a speech loudspeaker
`22, an information message via a display unit 23, a audible
`tone signal via a beeper 24, and a visual alert signal via an
`LED 25. In case of a paging transceiver, allowing for
`sending a return message, transmission means 26 are pro
`vided for, which are controlled by the rrricrocontroller 20,
`the transmission means being coupled to a transmitting
`aerial 27.
`FIG. 2 shows an embodiment of the frequency effect
`detector 17 and out-of-range detection means according to
`the present invention, the same reference numerals having
`been used for corresponding features. In FIG. 2, un?ltered
`data dta are available at an output of the demodulator 19. As
`in the prior art, the said EP 298 484, the offset frequency
`detector 17 comprises a series arrangement of a phase
`shifting arrangement 30 and a multiplication arrangement 31
`in one quadrature path, e.g. the quadrature path 5 as shown
`in FIG. 1. In case of one series arrangement the baseband
`signal Q is fed to the phase shifting arrangement 30 of which
`an output 32 is coupled to a ?rst input 33 of the multipli
`cation arrangement 31. The baseband signal I is fed to a
`second input 34 of the multiplication arrangement 31, of
`which an output 35 forms an output signal ofdl at an output
`36 of the offset frequency detector 17. The baseband signals
`I and Q may also be interchanged. In case of series arrange
`ments in both quadrature paths according to the present
`invention, the offset frequency detector 17 further comprises
`a phase shifting arrangement 37 and a multiplication
`arrangement 38, being coupled to the baseband signals I and
`Q as described, i.e. the series arrangements are cross
`coupled to the baseband signals I and Q. The output 35 of the
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`multipication arrangement 31 and an output 39 of the
`multiplication arrangement 38 are fed to a subtracting
`arrangement 40 for subtracting output signals of the multi
`plication arrangements 31 and 38. An output 41 of the
`subtracting arrangement 17 forms an output signal ofd2 at
`the output 36 of the offset frequency detector 17. The offset
`frequency detector 17 can be implemented digitally, the
`phase shifting arrangements 30 and 37 being clocked shift
`registers, and the multiplication arrangements 31 and 38
`being exclusive-OR digital circuits. In case of a single series
`arrangement, as in the prior an frequency detector, the digital
`signal dot is a bipolar signal with varying pulsewidth, and in
`case of the frequency detector according to the present
`invention having a series arrangement in both quadrature
`paths together with a subtracting arrangement the digital
`signal dot is a unipolar signal of which the polarity depends
`of the sign of the offset frequency fL—fc. Also, the micro
`controller 20 can functionally implement the series arrange
`ments 30, 31 and 37, 38, and subtracting arrangement 40. By
`applying a well known microcontroller with digital I/O
`interfaces and digital-to-analog conversion means the a.f.c.
`signal ct can be fed immediately to the local oscillator 14.
`For a.f.c. range-extension, the direct conversion receiver
`1 comprises the data demodulation arrangement 19 which
`provides the demodulated data signal dta, and further a data
`?lter 42 for ?ltering the demodulated data signal dta, which
`can be a ?lter as described in the European Patent Applica
`tion No. 9220217918 (PI-IN l4.l07 EP-P), or another data
`?lter. An output 43 of the data ?lter 42 is coupled to a ?rst
`input 44 of a switching arrangement 45, the output 36 of the
`offset frequency detector 17 being coupled to a second input
`46 of the switching arrangement 45. The switching arrange
`ment 45, which is controlled by an out-of-range decision
`circuit 47. An input 48 of the out-of-range decision circuit 47
`is coupled to the output 43 of the data ?lter 42. On the basis
`of an average level Vfdm of the filtered data signal fdta,
`which is obtained by feeding the ?ltered data signal to a low
`pass RC-?lter comprising a resistor 90 and a capacitor 91,
`the decision arrangement 47 decides whether the oscillator
`frequency f L falls within a given frequency range around the
`carrier frequency f , or outside this given range. If the
`oscillator frequency f L falls within the given range, the offset
`frequency detector 17 provides the digital frequency control
`signal dct, whereas otherwise the ?ltered data signal fdta is
`used as the digital signal dct. The a.f.c. range-extension
`gives a better result, the more the condition is ful?lled that
`the number of ones in the received signal if is equal to the
`number of zeroes in the signal rf, on the average. The
`out-of-range decision arrangement may also be a software
`based arrangement, at least partially, being comprised within
`the controller 20. Then the decision can be based upon valid
`data, and or frequency measurement of the I signal or Q
`signal, or the product of the I signal and Q signal. A valid
`data decision can be based upon a valid CRC (Cyclic
`Redundancy Code, a BER (Bit Error Rate), or the like, or
`upon a frequency below a threshold frequency. Frequency
`measurements can be made with a frequency-to-voltage
`converter inter alia.
`FIG. 3 shows a window comparison arrangement as an
`out—of-range decision arrangement 47 according to the
`present invention, comprising a ?rst and a second compara
`tor 50 and 51, a minus input 52 of the comparator 50 being
`coupled to a plus input 53 of the comparator 51, the coupled
`inputs 52 and 53 forming the input 48 of the arrangement 47.
`A low threshold signal VL is fed to a plus input 54 of the
`comparator 50, and a high threshold signal VH is fed to a
`minus input 55 of the comparator 51. Outputs 56 and 57 of
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`the respective comparators 50 and 51 are coupled to an
`OR-gate 58 of which an output 59 is coupled to an output 60
`of the out-of-range decision arrangement 47. Within each of
`the comparators 50 and 51 a positive feedback can be
`applied for giving an hysteresis effect to the threshold
`signals VL and V”.
`For a further description of a ?rst embodiment of the
`present invention, in relation to the prior art, FIGS. 4 to 7
`show various signals as a function of frequency or time.
`FIG. 4 shows effects on baseband frequencies for various
`frequency offsets as a function of frequency. On line 4a a
`spectrum for FSK modulated signals in a direct conversion
`receiver 1 is shown, a logical “1” data signal having a
`spectral line at a frequency fC—Af, and a logical “0” data
`signal having a spectral line at a frequency fc+Af, fc being
`the nominal carrier frequency, and Af being a frequency
`deviation, e.g. 4 kHz. On line 4b a situation is displayed
`where the local oscillator frequency fL is equal to the
`nominal carrier frequency fc, giving rise to baseband I and
`Q signals in the quadrature paths 4 and 5 with the same
`frequency, though with a di?’erent phase. On line 4c a
`corresponding spectrum is shown, showing a single spectral
`line for mixed down baseband signals I and Q, both for a “l”
`and a “0” data signal, indicated with f1 and f0 respectively,
`both at a frequency Af, in the given example at 4 kHz. On
`line 40! a frequency o?fset situation is displayed, the local
`oscillator frequency f,_ being higher than the nominal carrier
`frequency fc by an amount 5f, but still within a range fc—Af
`to fC+Af, of being 2 kHz in the example given. In this
`situation, the mixed down data signals “1” and “0” appear at
`f1:6 kHz and fOIZ kHz, i.e. with different frequencies. For
`a negative offset frequency 5f=fL—fC, the mixed down “1”
`and “0” data signals appear at a lower and a higher fre
`quency, respectively, such a situation being shown on line
`4e. Shown is an offset 5f=—5 kHz, f1 being at 1 kHz, and f0
`being at 9 kHz. Also shown on line 42 is a situation where
`the local oscillator frequency f,_ is out-of-range. In an
`embodiment of the present invention, an out-of-range situ
`ation is detected by the out-of-rangedecision arrangement
`47, the ?ltered data signal fdta being the digital signal dct in
`case of out-of-range, and the offset frequency detector 17
`providing the digital signal dct if the oscillator frequency fL
`is in-range.
`I
`FIG. 5A shows the digital output signal ofdl of a prior art
`offset frequency detector 17 as disclosed in EP 298 484,
`having a single series arrangement, as a function of time t.
`The Q-channel baseband signal Q is delayed by a time delay
`td, additional delays occurring of +1t/2 and —1rl2 for “O” and
`“1” data, respectively. Thus, during a “0” the phase differ
`ence between the I-signal and the Q-signal is +1r/2, and
`during a “1” the phase difference between the I-signal and
`the Q-signal is —11:/2. The time delay td is taken around
`l/(2Af), i.e. for Af=4 kHz, td=125 us. The Q-channel delayed
`signal is multiplied by the I-channel baseband signal I. The
`digital signal ofdl is a bipolar signal having a pulse width
`proportional to the frequency offset 5f, up to 1/2Af. A correct
`polarity signal as the control signal ct is obtained by aver
`aging the digital signal ofdl, by means of the ?lter 18.
`FIG. 5B shows the digital output signal ofd2 of the oifset
`frequency detector 17 according to the present invention,
`having two series arrangements and a subtracting arrange
`ment. The digital signal ofd2 can have three values, a
`positive value as shown, or zero, or a negative value,
`depending on the frequency offset 6f, i.e. a correct polarity
`digital signal dct is achieved if the signal ofd2 equates the
`signal dct. The signal ofd2 has got a considerable higher
`ripple frequency than the signal ofdl, thus allowing for
`better loop dynamics.
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`FIG. 6 shows the average level Vfdm of the ?ltered data
`signal fdta, at the output of the data ?lter 42, as a function
`of a frequency deviation of a local oscillator with respect to
`carrier frequency of an FSK signal, fC—fL=—5f, in a ?rst
`out-of-range extension embodiment. The average value Vfdm
`is obtained by feeding the ?ltered data signal fdta t0 the low
`pass RC-?lter 90, 91. The out-of-range detection is based
`upon the insight that the better the condition is ful?lled that
`the average number of zeroes is equal to the average number
`of ones in the data signal dta, the better the out-of-range
`detection works. A situation for a paging signal is shown,
`with a 2 volts signal amplitude for a logical “1” data signal,
`and a 0 volts signal amplitude for a logical “0” data signal
`level. If the average signal Vfdm is out-of-range, i.e. outside
`the window VH—VL, the out-of-range decision arrangement
`47, e.g. a window comparison arrangement, switches the
`signal fdta as the digital signal dct, whereas for an in
`window situation, the signal ofd2 is switched as the digital
`signal dct. In a practical situation, the channel distance
`between paging signals is e.g. 25 kHz, thus the present
`invention achieves quite an out-of-range detection. In FIG.
`6, various signal conditions are shown. A 0% bit-error-rate
`or BER is indicated with a solid line, a 3% BER with a
`dashed line, and a 10% BER with a dotted-dashed line. The
`BER is taken with respect to a zero o?set frequency 8f. It
`can thus be seen that the out-of-range detection according to
`the present invention operates over quite a nominal (zero
`offset frequency) BER, though for a higher BER out-of
`range is detected for a smaller frequency deviation. For
`weaker signals, i.e. with a higher BER, the out-of-range
`detection is thus less distinctive. It is to be noticed that for
`paging applications a 3% BER is allowable.
`FIGS. 7 to 9 show a second out-of-range extension
`embodiment of the present