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`Paper No.
`Filed: October 13, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
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`
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`v.
`
`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
`
`
`
`
`
`
`
`
`Case IPR2015-01524
`Patent No. 6,366,130
`
`
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`
`
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`
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`PETITIONER’S DEMONSTRATIVE EXHIBITS
`
`
`
`

`

`Demonstratives of Petitioner Samsung Electronics Co., Ltd.
`
`Inter Partes Review of
`U.S. Patent No. 6,366,130
`
`IPR2015-01524
`
`Oral Hearing: October 18, 2016
`
`1
`
`

`

`Instituted Grounds
`
`For the reasons given. it 1s hereby
`
`V. ORDER
`
`ORDEREDthatpursuant to 35 U.S.C. § 314(a). an interpartes
`
`over the combination of Sukegawa, Lu. and Hardee:
`
`review 1s hereby instituted as to claims 1—3, 5—7, and 9 of the ‘130 patent
`
`with respect to the following grounds:
`
`1. Whether claims 1. 2. 5, 6, and 9 are unpatentable under 35 U.S.C.
`
`§ 103 as obvious over the combination of Sukegawa and Lu:
`
`2. Whether claim 3 is unpatentable under 35 U.S.C. § 103 as obvious
`
`over the combination of Sukegawa, Lu. and Watanabe: and
`
`3. Whether claim 7 is unpatentable under 35 U.S.C. § 103 as obvious
`
`Institution Decision (Paper No. 9) at 19
`
`

`

`°130 Patent Claim 1
`
`input of the output stage;
`
`1. A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source;
`a differentialbuscoupled to the bus drivers and to the
`voltage precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including
`a cross-coupled latch coupled to a
`
`differentialdatabus.and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an
`
`

`

`Issues Raised in Patent Owner’s Response
`
`1. Whether Sukegawa and Lu teach the claimed differential data bus?
`(all claims)
`
`Patent Owner Resp. at 18-26; Petitioner Reply at 1-6
`2. Whether Sukegawa and Lu teach the claimed precharging?
`(all claims)
`
`Patent Owner Resp. at 26-37; Petitioner Reply at 7-16
`3. Whether Sukegawa and Lu render obvious claim 5?
`Patent Owner Resp. at 37-42; Petitioner Reply at 16-18
`4. Whether Sukegawa, Lu, and Watanabe render obvious claim 3?
`Patent Owner Resp. at 46-50; Petitioner Reply at 18-21
`5. Whether Sukegawa, Lu, and Hardee render obvious claim 7?
`Patent Owner Resp. at 50-55; Petitioner Reply at 21-24
`
`4
`
`

`

`Issues Raised in Patent Owner’s Response
`
`1. Whether Sukegawa and Lu teach the claimed differential data bus?
`(all claims)
`
`Patent Owner Resp. at 18-26; Petitioner Reply at 1-6
`2. Whether Sukegawa and Lu teach the claimed precharging?
`(all claims)
`
`Patent Owner Resp. at 26-37; Petitioner Reply at 7-16
`3. Whether Sukegawa and Lu render obvious claim 5?
`Patent Owner Resp. at 37-42; Petitioner Reply at 16-18
`4. Whether Sukegawa, Lu, and Watanabe render obvious claim 3?
`Patent Owner Resp. at 46-50; Petitioner Reply at 18-21
`5. Whether Sukegawa, Lu, and Hardee render obvious claim 7?
`Patent Owner Resp. at 50-55; Petitioner Reply at 21-24
`
`5
`
`

`

`’130 Patent Claim 1
`
`input of the output stage;
`
`1. A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source;
`a differential bus coupled to the bus drivers and to the
`voltage precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an
`
`

`

`Patent Owner’s Argument
`
`"C" are at the junctions of the pink lines and are also marked “N3” and “N4”).
`
`nodes “C” as the “differential data bus” of the ‘130 patent (Nodes marked
`
`1) Nodes C are simply nodes — not a bus
`
`In Figure 1 of Sukegawa above, the Petitioner improperly identifies
`
`Patent Owner Response (Paper No. 12) at 20
`
`

`

`Sukegawa teaches thatits latching sense amplifier (shown below in purple)
`
`includes a first stage (shown below in light blue) with a cross-coupled latch
`
`coupled to a differential data bus (pink lines below). See, e.g., Ex. 1002, § 31;
`
`Maiame woVeCail
`
`data bus
`
`SukegawaFig. | (annotated below).
`
`Differential
`
`

`

`Preliminary Response
`
`This purple lines are not even a bus; they are simply a pair ofwires
`
`having opposite logic levels within a circuit. A bus typically has the
`
`Patent Owner’s Positions
`property of a controlled impedance. These wires in the Sukegawa do not have that property, they are simply wires.
`
`
`and “N4’”).
`
`Patent OwnerPrel. Resp. (Paper No. 8) at 15
`(image taken from Pet. Expert Decl. at 4 31)
`
`Patent Owner Response
`
`Patent OwnerPrel. Resp. (Paper No. 8) at 16
`(referring to Sukegawa’sfigure to theleft)
`
`1) Nodes C are simply nodes — not a bus
`
`In Figure 1 of Sukegawa above, the Petitioner improperly identifies
`
`nodes “C” as the “differential data bus” of the ‘130 patent (Nodes marked
`
`99>
`"C" are at the junctions of the pink lines and are also marked “N3”
`
`Patent Owner Resp. (Paper No. 12) at 20
`
`

`

`Patent Owner
`
`|
`
`In electronics, a bus is defined as “a commonpath along which
`
`powerorsignals travel from one or several sources to one or
`.
`.
`a
`several destinations.”
`
`Patent Owner Response (Paper No. 12) at 22 (quoting June 2013 JEDEC
`Dictionary of Terms for Solid-State Technology (Ex. 2005))
`Petitioner
`
` Patent Owner’s Definition of “Bus”
`
`data bus
`
`the signal transmission is completed.
`
`[57]
`ABSTRACT
`Differential
`
`
`
`Asignalcircuitwhich enables the distance oftransmission
`signal transmission as measured by the length of the wiring
`electrically connecting a driver circuit and a receiver circuit
`of the signal transmission circuit to be increased, while the
`signal delay and power consumption are reduced. ‘The signal|
`includes the driver circuit, the receiver
`circuit, an equalizer circuit that flattens the output of the
`driver circuit, and an intermediate amplilier circuil.
`Sukegawa (Ex. 1005) at Abstract (cited in Pet. Reply at 3)
`
`Su
`:
`.
`Petition (PaperNo. 1) at 19 (annotating Sukegawa’s Fig. 1)
`
`In this case, as enable terminal EN changes from L level
`to H level, and input terminal IN enters the H level, node N1
`enters the L level, while node N2 remains on the H level;
`hence, node 101 of LINE is driven from intermediate
`voltage V,,,/2 to Hlevel, and node 102 ofthe inverted LINE
`is driven from intermediate voltage V,,,,/2 to the L level, and
`thus the signal is transmitted to receiver circuit 4.
`Consequently, at the receivercircuit 4, node N4 enters the
`L level, while output terminal OUT enters the H level, and
`
`

`

`In electronics, a bus is defined as “a common path along which
`
`powerorsignals travel from one or several sources to one or
`
`Patent Owner Response (Paper No. 12) at 22 (quoting June 2013 JEDEC
`Dictionary of Terms for Solid-State Technology (Ex. 2005))
`
`Patent Owner’s Definition of “Bus”
`
`several destinations.””
` Sukegawa
`°130 Patent
`
`
`
`Differential
`data bus
`
`Coupling first stage
`to differential data
`bus
`
`
`
`7130 Patent (Ex. 1001) at Fig. 2 (annotated)
`
`The second bus. the differential data bus. consists of the two
`
`
`
`lowerlines running between theleft and right of the circuit in Fig. 2, the line
`
`Petition (Paper No. 1) at 22
`
`

`

`Petitioner’s Definition of “Bus”
`
`“Bus” is a term of art widely used and understood at the time of the
`
`alleged invention to be “one or more conductors that are used for the transmission
`
`Pet. Reply (Paper No. 16) at 2 (quoting 1995 [IEEE Standard
`Glossary of Computer Hardware Terminology (Ex. 1010) at 13)
`
`Q.
`
`But you would agree that the lines that
`
`are depicted showing the various connections of N3
`and N4& are conductors?
`
`A.
`
`Well,
`
`I think I explained that ina
`
`little more detail. They*re -- in the classic
`
`sense, you think of a conductor as a metal. These
`
`are partially connected by metal. There may be
`also other conductors,
`
`that complete the connection.
`Patent Owner Expert Depo.Tr. (Ex. 1011) at 49:12-20; see also
`Pet. Reply at 3; id. (citing Sukegawa (Ex. 1005) 9:14-24, 9:4-7)
`
`of signals, data, or power.” Ex. 1010 at 13
` Patent Owner’s Expert Testimony
`such as diffusion areas or polysilicon,
`
`
`Sukegawa
`Couplingfirst stage
`to differential data
`
`
`Asignalcircuitwhich enables the distance oftransmission
`
`bus
`signal transmission as measured by the length of the wiring
`electrically connecting a driver circuit and a receiver circuit
`of the signal transmission circuit to be increased, while the
`signal delay and power consumption are reduced. The
`includes the driver circuit, the receiver
`
`Differential
`data bus
`
`Petition (Paper No.1) at 22
`(annotating Sukegawa’s Fig. 1)
`
`

`

`Patent Owner’s Argument
`
`2) Differential nodes and a bus are not the same
`
`The Petitioner’s analysis on p. 22 of the Petition states that “One of
`
`ordinary skill in the art at the time of the alleged invention of the ‘130 Patent
`
`would have recognized lines associated with nodes C (shownabove in pink)
`
`
`
`as the "differential data bus" because the pink highlighted lines represent an
`
`amplified voltage differential representative of the data to be read out by the
`
`latching sense amplifier’ assumes
`
`that simply because a voltage is
`
`“differential,” This somehow makes the nodes marked C (which the
`
`Petitioner admits are nodes) a bus. This is not correct.
`
`Patent Owner Response (Paper No. 12) at 25
`
`

`

`Petitioner’s Expert
`
`One of ordinary skill
`
`in the art at
`
`the time of the alleged
`
`invention of the °130 Patent would have recognized lines
`
`associated with nodes C (shown above in pink) as the
`
`“differential data bus” because the pink highlighted lines
`
`represent an amplified voltage differential representative of the
`
`data to be read out by the latching sense amplifier. See, e.g.,
`
`skillintheartat
`
`
`
`Sukegawa 9:14-24.Indeed,oneofordinary
`
`Pet. Expert Decl. (Ex. 1002) at
`
`31
`
`

`

`Issues Raised in Patent Owner’s Response
`
`1. Whether Sukegawa and Lu teach the claimed differential data bus?
`(all claims)
`
`Patent Owner Resp. at 18-26; Petitioner Reply at 1-6
`2. Whether Sukegawa and Lu teach the claimed precharging?
`(all claims)
`
`Patent Owner Resp. at 26-37; Petitioner Reply at 7-16
`3. Whether Sukegawa and Lu render obvious claim 5?
`Patent Owner Resp. at 37-42; Petitioner Reply at 16-18
`4. Whether Sukegawa, Lu, and Watanabe render obvious claim 3?
`Patent Owner Resp. at 46-50; Petitioner Reply at 18-21
`5. Whether Sukegawa, Lu, and Hardee render obvious claim 7?
`Patent Owner Resp. at 50-55; Petitioner Reply at 21-24
`
`15
`
`

`

`SRR emer
`
`
`
`1. A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source;
`a differential bus coupled to the bus drivers and to the
`voltage precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`differential data bus; and
`an output stage coupled to an outputofsaid first stage;
`wherein the output of the first stage is coupled to an
`input of the output stage;
`
`

`

`Petitioner’s Expert
`Given the overlapping subject matter between Sukegawa and
`
`Expert Opinion
`
`
`Q-
`
`Why does Sukegawa provide a precharge
`
`voltage that
`
`is Vdd over 2?
`
` Patent Owner’s Expert
`
`Lu and the apparent benefit of precharging to Vdd/2, one of
`
`ordinary skill in the art at the time of the alleged invention of
`
`the °130 Patent would have been motivated to apply the
`
`teachings of one reference to the other.
`Pet. Expert Decl. (Ex. 1002) at 431 (cited in
`Petition at 25-27, Pet. Reply at 10-11)
`
`One of ordinary skill in
`
`the art at the time ofthe alleged invention of the °130 Patent
`
`would have understood that precharging to an intermediate
`
`voltage would have been desirable to speed up operation of the
`
`circuit because pulling up or pulling down a node precharged
`
`to an intermediate voltage to full logic levels would require a
`
`smaller voltage swing (and thus be faster) when compared to a
`
`full Vdd voltage swing when pulling down a node precharged
`
`to Vdd. For example, when theintermediate precharge voltage
`
`is Vdd/2, pulling up or down a node precharged to Vdd/2
`
`would merely require half the voltage change when compared to pulling down a node precharged to Vdd.
`
`A.
`
`In general,
`
`the use of Vdd over 2 means
`
`that you establish a differential signal more
`
`quickly because you're starting in a bid point.
`
`If you have a differential line, one line can go
`
`up,
`
`the other line can go down. And they're both
`
`actively moved to that condition.
`
`So generally -- well,
`
`there's many
`
`advantages to Vdd over 2 precharging depending on
`
`the circuitry. But
`
`in this case,
`
`I believe it's a
`
`speed issue primarily.
`
`Q.
`
`A.
`
`What are the other advantages?
`
`Well,
`
`if you're talking about a memory
`
`device -- for instance,
`
`if you precharge the bit
`
`lines to Vdd over 2, as we'll see later with Lu,
`
`you can minimize the amount of charging current
`
`that's necessary to get
`
`them to that point
`
`because,
`
`in operation, one of the bit lines goes
`
`to Vdd.
`
`The other one goes to ground.
`
`If you tie them together, as Lu does,
`
`that means you don't have to provide any charging
`
`current
`
`from the power supply or from ground.
`
`So
`
`it's a suppression-of-transience,
`
`reduction-of-power situation there.
`
`Q.
`
`A.
`
`Any other advantages you can think of?
`
`Those are the major ones. There may be
`
`

`

`Patent Owner’s Argument
`
`Patent Owner’s Response
`
`teaching that it would be undesirable to bring nodes N3 and N4 to some
`
`intermediate value, but rather that they should be brought completely to
`
`Patent Owner Resp. (Paper No. 12) at 29-30
`
`Preliminary Response
`
`Moreover, while Sukegawa teaches pre-charging LINE and LINE;it
`
`also teachesthatit is advantageous NOTto pre-charge N3 and N4 to an
`
`Vdd.
`
`
`
`
`
`
`termediate voltage,Rather,iteachesthemtoadifferentpre-chargng
`
`
`
`‘tothesamevoltage(assuming that N3 and N4 comprise a differential bus.
`
`

`

`Petitioner’s Argument
`
`Notably, Sukegawa provides no criticism of precharging the “differential
`
`data bus” to a value under Vdd, such as Vdd/2. Thus, one skilled in the art would
`
`
`
`for Sukegawa’s “differential data bus.” Pet. at 25-27: Ex. 1002. 931: supra, Section
`
`not have been turned away from implementing such features. Instead. as explained
`
`above and in the Petition, given the advantages of precharging lines to Vdd/2. as
`
`disclosed by Lu. such a skilled person would have been motivated to do the same
`
`IL.B.
`
`Pet. Reply (Paper No. 16) at 8
`
`

`

`supply Vdd to the circuit except Claim 7.”
`
`And there's nothing in the patent
`
`teaches one of skiil in the art that you wouldn’
`
`» modify Wl and N3 to PMOS transistors,
`
`that question.
`
`It
`
`It only talks about
`
`Ia -- does the
`
`h
`
`silent
`
`mean that one of skill in the art would not want
`
`co modify Nl and N3 to PNOS transistors?
`
`A.
`
`Well, at --
`THE WITNESS:
`
`It teaches NMOS.
`
`doesn't say anything about PMOS.
`
`ordinary skill in the art icoked at this,
`
`they
`
`would say, “Okay. Here’s an inventor.
`
`He has
`
`more knowledge than Ido. He's making it NMOS.
`However,
`I may want
`to make it PMOS. There's
`nothing in there to prevent me from doing so
`
`NMOS transistors (e.g. Nl,
`N3) connecting power
`supply Vdd to the circuit
`
`PMOStransistors (e-g.. Pl, P4,
`P35, P6, P7) connecting power
`
`Pet. Reply (Paper No. 16) at 9 (annotating Patent Owner Expert Decl.
`(Ex. 2004) at 21, Figure A depicting Figs. 1 and 2 of the ’130 Patent))
`
`Patent Owner Expert Depo. Tr. (Ex. 1011) at 19:14-20:10
`(one attorney scope objection removed)(cited in Pet.
`Reply at 9)
`
`

`

`Patent Owner’s Argument
`
`D.
`
`Petitioner's Solution is Unworkable in Practice.
`
`Attempting to apply the Petitioner's solution to the problem,itis
`
`
`
`
`
`suggests simply connecting the nodes to a precharging voltage of Vdd/2.
`
`
`
`
`prechargenodesN3andN4toVdd/2.The Petitioner's expert Dr. Baker
`
`Patent OwnerResp. (Paper No. 12) at 30
`
`As Dr. Huberhas shown, the Petitioner’s expert Dr. Baker’s attempt
`
`to precharge nodes N3 and N4 to Vdd/2 fails in its primary objective.
`
`In
`
`
`
`
`
`addition, the attempt results in anunacceptableandpracticallyunworkable
`
`

`

`etitioner’s Argument and Expert Testimony
`
`|
`
`PO argues that the Sukegawa and Lu combination is unworkable. POR at
`
`30-34. This argumentis flawed in multiple respects. First, PO does not and cannot
`
`argue that the Svkegawa and Lu combination would be inoperable. Second, PO's
`
`Pet. Reply (Paper No. 16) at 12
`
`Petitioner’s Expert
`-- one way is to use a larger threshold
`
`A.
`
`voltage for transistors 39 and 40. Another way is to
`use a longer length. And I can think of several other
`ways sitting here right now to reduce or eliminate the
`
`Petitioner’s Expert
`What effect does such current -- would such a
`
`Q.
`
`current path have on the voltage at the node
`immediately above C,
`the dot?
`A.
`The whole node, N3 or N4 or C,
`
`is a wire.
`
`current through transistors 39 and 40.
`
`
`
`Andifonedoesn'tdesignthecircuitcorrectly,when
`Q.
`If there is -- let's assume there is a
`
`the node is precharged to Vdd over two,
`
`there could be
`
`argument is premised on the assumption that the Sukegawa and Lu system would have been designed poorly.
` Q.
`If there is a
`could be used to minimize the current or a larger A.
`
`two or identical to Vdd;
`am I right?
`
`
`THE WITNESS:Jf/EheCircuitisn'tGesigned
`
`
`correctly,it'spossibletogetanintermediatevoltage>
`EHSEVEUHSENVGSUGEIVETSVEETEWS at nodes N3 and 4 of
`Patent Owner’s Expert
`the differential data bus.
`think you may have answered this,
`ca
`=
`eresa1
`yi
`to make sure I've got it clear.
`
`current.
`
`Some current, small, whatever.
`
`current,
`
`then, at a point between Vdd over two and Vdd,
`
`the voltage will not be either identical to Vdd over
`
`Pet. Expert Depo. Tr. (Ex. 2003) at 84:19-85:9 (cited
`in Pet. Reply at 12-14) (one objection omitted)
`THE WITNESS: During the precharge,
`
`transistors 38 and 41 would precharge the node to vdd
`by two.
`For transistors 39 and 40,
`long L devices
`
`Pet. Expert Depo.Tr. (Ex. 2003) at 83:5-11
`
`(cited in Pet. Reply at 12)
`
`I
`
`reassilee
`sor
`a
`I just want
`
`Making a transistor weaker is one way 4 person o
`
`skill in the art could lower the current that goes
`
`through a transistor, correct?
`
`

`

`Further, the combination of Sukegawa and Lu
`
`is not premised on an incorrect design, but
`
`instead takes into account
`
`the
`
`knowledgeandabilities of one of ordinary skill in the art at the time ofthe alleged
`
`Pet. Reply (Paper No. 16) at 12
`
`Petitioner’s Expert Testimony
`
`Petitioner’s Argument and Expert Testimony
`
`invention.
` THE WITNESS: When we talk about precharging
`
`
`THE WITNESS:
`
`So I did discuss, and we
`
`discussed earlier, Lu and how it would have been
`
`a bus to Vdd over two, we're talking about connecting a
`
`obvious to precharge the differential data bus to Vdd
`
`switch between a bus and Vdd over two.
`
`I don't know
`
`over two.
`
`I did discuss during this deposition how it
`
`what more I can talk about there because it's well
`
`would be simple to reconnect transistors 38 and 41 so
`
`that they were connected to Vdd by two instead of Vdd.
`
`And then I have also discussed that on the outputs of
`
`the inverters, we would want full logic levels, and
`
`it's not significantly challenging to adjust the size
`
`of the devices. One of ordinary skill in the art would
`
`know that, when making modifications,
`
`to adjust the
`
`sizes so the -- so the circuit worked and didn't fail.
`
`within someone of ordinary skill in the art to make
`
`these simple adjustments to precharge the bus to Vdd
`
`over two and adjust
`
`the sizes of any components in
`
`there to do, you know, whatever they would want.
`
`I, frankly, would expect my students in my --
`
`my CMOS IC class to be able to perform these, and
`
`they're certainly not
`
`these kind of edits and these
`
`As far as discussing precharging to Vdd over
`
`kind of modifications. They're certainly not at the
`
`two or precharging the buses,
`
`I gave examples in Lu,
`
`and I also discussed in the declaration how there's an
`
`example of precharging a bus to Vdd over two in
`
`level of one of ordinary skill in the art.
`Pet. Expert Depo. Tr. (Ex. 2003) at 81:11-
`23 (cited in Pet. Reply at 12)
`
`

`

`Patent Owner’s Argument
`
`E.
`
`Lu Fails to Precharge.
`
`After admitting that Sukegawa ‘241 neither discloses nor suggests
`
`
`
`precharging nodes “C” to Vdd/2,thePetitionerseekstousetheLureference
`
`Patent Owner Resp. (Paper No.12) at 34
`
`precharging source Pr, but merely assumes that one side of the bus is near
`
`Vdd and the other side is near ground before the shorting occurs. The hope
`
`Lufails to show any
`
`
`
`
`
`
`
`
`
`
`is that the final value will be somewhere near Vdd/2.‘However,failstoLu
`
`

`

`Petitioner’s Argument
`
`Ludiscloses two mechanisms for precharging to Vdd/2, namely via (1) a
`
`bit-line shorting mechanism or (2) a voltage regulator. See, e.g., Ex. 1008 at
`
`1
`
`(“The bit lines are precharged to a reference voltage approximately equal to Vdd/2.
`
`which can be obtained from a voltage regulator as suggested by Foss and Harland
`
`[3]. or by shorting twobit-line halves after restoring the signal [1]. [2].”)° See also
`
`Pet. Reply (Paper No. 16) at 15
`
`In the voltage regulator mechanism, a voltage precharge source, Vref. is
`
`Ex. 2003 at 18:5-19:5.
`FROM K -7 DECODER Lu (Ex. 1008) at 2 (cited in Pet. Reply at 15-16)
`
`
`
`used to precharge at that same level Vref. Ex. 1008 at Fig.
`
`1 (showing voltage
`
`precharge source “Vref”).
`Pet. Reply (Paper No. 16) at 15
`
`Alternatively, in the bit-line shorting mechanism, two
`
`source voltages are used to precharge to a level midway between those source
`
`voltage levels.
`
`Pet. Reply (Paper No. 16) at 15
`
`At the end of the previous active
`cycle, one bit-line half is at Vp, and the other is at0 V. A
`precharge of the bit line before sensing is initiated by
`switching on ®,
`to turn on the equalization device Qo,
`which shorts two bit-line halves together. The charge shar-
`ing between twobit-line halves results in a precharge level
`at nearly half Vpp.
`
`

`

`Patent Owner’s Argument
`
`Claim | of the ‘130 Patent requires K to have a definite value so that
`
`the precharge voltage does not float.
`
`The mventor has suggested 1/3:
`
`however, as previously discussed any value between 0 and | is allowed (but
`
`valueK:thenodes
`
`
`
`not 0 and not 1).IntheeaseofLu,thereisnofixed
`
`Patent Owner Resp. (Paper No. 12) at 34-37
`
`

`

`°130 Claim 1 and Specification
`
`input of the output stage;
`
`1. A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source;
`a differential bus coupled to the bus drivers and to the
`voltage precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage 1s coupled to an
`
`130 Patent (Ex. 1001) at 4:2-17 (highlighted 4:14-17)
`
`Additionally,
`the speed of the latched sensing amplifieris effected little by
`andthe deviation of the thresh-
`
`old voltage of the input transistors. during the operating cycle of the bus 130 Patent (Ex. 1001) at 3:52-55
`
`The use of domino output stages in accordance with the
`present invention instead of static inverters is necessary to
`avoid leakage currents and output glitches, which may
`
`

`

`Issues Raised in Patent Owner’s Response
`
`1. Whether Sukegawa and Lu teach the claimed differential data bus?
`(all claims)
`
`Patent Owner Resp. at 18-26; Petitioner Reply at 1-6
`2. Whether Sukegawa and Lu teach the claimed precharging?
`(all claims)
`
`Patent Owner Resp. at 26-37; Petitioner Reply at 7-16
`3. Whether Sukegawa and Lu render obvious claim 5?
`Patent Owner Resp. at 37-42; Petitioner Reply at 16-18
`4. Whether Sukegawa, Lu, and Watanabe render obvious claim 3?
`Patent Owner Resp. at 46-50; Petitioner Reply at 18-21
`5. Whether Sukegawa, Lu, and Hardee render obvious claim 7?
`Patent Owner Resp. at 50-55; Petitioner Reply at 21-24
`
`28
`
`

`

`°130 Patent Claim 5
`
`1. A data transfer arrangement comprising:
`two bus drivers;
`
`
`
`a differential bus coupled to the bus drivers and to the
`voltage precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an
`input of the output stage;
`wherein the differential bus and the differential data bus
`are precharge to a voltage Vpr between Vdd and
`ground, where Vpr=K*Vdd, and K is a precharging
`voltage factor.
`
`130 Patent (Ex. 1001) at 4:2-17
`
`5. The data transfer arrangementin accordance with claim
`
`

`

`Sukegawa discloses that ‘[w]hen intermediate amplifier circuit
`
`is in the imtial precharge state, pMOStransistors 5, 7 and
`
`nMOStransistors 6, 8 are all in OFF (nonconductive)state. In
`
`Sukegawa further
`
`this case,
`
`the voltage at nodes 101 and 102 becomes the
`
`discloses that “(t]he BLR node is connected to the drain of the
`
`intermediate voltage VDD/2, gate node N1 of pMOStransistor
`
`nMOStransistor 30 and the drain of nMOStransistor 31, and
`
`10 and gate node N2 of pMOStransistor 11 become the high
`
`the BLR node becomesthe power source voltage VDD/2in the
`
`Petitioner’s Expert
`
`level (referred to as “H level’ hereinafter); and gate node N3 of nMOStransistor 15 and gate node N4 of nMOStransistor 14
`
`initial precharge state.” Sukegawa 8:28-31; see also, e.g., id.
`
`9-14-21.
`
`Pet. Expert Decl. (Ex. 1002) at 4 33 (cited in Petition at 29 )
`
`becomethe low level (referred to as “L level’ hereinafter). This
`
`is because,
`
`in the initial precharge state,
`
`the PC terminal
`
`becomes the H level. while the N-PC terminal becomes the L
`
`level.” Sukegawa 7:26-37 (emphasis added).
`
`Pet. Expert Decl. (Ex. 1002) at ¢ 33 (cited in Petition at 29 )
`
`

`

`Patent Owner’s Argument
`
`teaches or suggests a precharge voltage less than a logic high voltage or greater than a logic low voltage.
`
`The Petitionerfails to show that the combination of Sukegawa and Lu
`
`Patent Owner Resp. (Paper No. 12) at 37-42
`
`

`

`Maia weeeCoils
`
`In fact, an example PO provides in its Response actually supports
`
`Petitioner’s position that one of ordinary skill would have understood that in a
`
`signal transmission system with power supply voltage Vdd, Vdd/2 is less than a logic high voltage and greater than a logic lowvoltage. Pet. at 29; Ex. 1002 at 433.
`0.5 * Vdd
`
`Pet. Reply (Paper No. 16) at 17
`
`JEDEC 1984|JEDEC 2005
`Maximumlogic low voltage, Vi, (max)
`0.2 * Vdd
`Minimumlogic high voltage, Vy (min)
`0.8 * Vdd
`Power Supply Voltage
`(Power Supply Voltage) / 2
`
`1.65 V
`
`Pet. Reply (Paper No. 16) at 18
`
`Viogic high — (Power Supply Voltage) /2 > Viogic low
`
`

`

`Maia weeeCoils
`
`signal transmission system with power supply voltage Vdd, Vdd/2 is less than a logic high voltage and greater than a logic lowvoltage. Pet. at 29: Ex. 1002 at 933.
`
`In fact. an example PO provides in its Response actually supports
`
`Petitioner’s position that one of ordinary skill would have understood that in a
`
`Pet. Reply (Paper No. 16) at 17
`
`TABLE 8: Low Power DDR SDRAM Electrical Characteristics
`(Note: 1; Recommended Operating Conditions.)
`eeen
`
`
`
`Ce.oe|7Seeee
`
`
`
`eeee Ai, BAO, BA1, CKE, CS_RAS,CAS, WE)
`freaWighvomse|VMafoe-vovo|woosTv |_|
`fnetowvetegeSSCOPOY evo|vy||
`
`
`
`
`Patent Owner Response (Paper No. 12) at 40
`MINIMUM Viogic high
`(showing JEDEC 2005 standard)
`
`maximum Viggic iow
`
`*
`
`Viegie high > 0.5 Vad - Viesie low
`0.8*Vjg > 0.5*Vaq > 0.2*Vag
`
`

`

`Issues Raised in Patent Owner’s Response
`
`1. Whether Sukegawa and Lu teach the claimed differential data bus?
`(all claims)
`
`Patent Owner Resp. at 18-26; Petitioner Reply at 1-6
`2. Whether Sukegawa and Lu teach the claimed precharging?
`(all claims)
`
`Patent Owner Resp. at 26-37; Petitioner Reply at 7-16
`3. Whether Sukegawa and Lu render obvious claim 5?
`Patent Owner Resp. at 37-42; Petitioner Reply at 16-18
`4. Whether Sukegawa, Lu, and Watanabe render obvious claim 3?
`Patent Owner Resp. at 46-50; Petitioner Reply at 18-21
`5. Whether Sukegawa, Lu, and Hardee render obvious claim 7?
`Patent Owner Resp. at 50-55; Petitioner Reply at 21-24
`
`34
`
`

`

`an inverted clock signal input.
`
`3. The data transfer arrangement in accordance with claim
`1, wherein the first stage of the latching sense amplifier
`comprises:
`a plurality of input pass transistors each having a gate, a
`source terminal, and a drain; and
`a plurality of NMOS and PMOStransistors each having
`a gate, a source terminal, and a drain;
`wherein the drains of the input pass transistors are
`coupled to the drains of the cross-coupled latch ampli-
`fier NMOS and PMOStransistors, each source terminal
`of the inputpass transistors is coupled to an input, the
`sources of the cross-coupled latch amplifier NMOS
`transistors are coupled to the drain of the NMOS
`transistor coupled to a clock signal
`input, and the
`sources of the PMOStransistors are coupled to the
`drain of the PMOStransistor having a gate coupled to
`
`7130 Patent (Ex. 1001) at 4:21-37
`
`

`

`Patent Owner’s Argument
`
`"wherein theGrinsoftheiapotpastransitsarecoupledtothedeansof
`
`The Petitioner has ignored an explicit
`
`requirement of claim 3
`
`
`
`
`
`
`
`
`
`terminaloftheinputpasstransistorsiscoupledtoaninputthe sources of
`
`the cross-coupled latch amplifier NMOStransistors are coupled to the drain
`
`of the NMOStransistor coupled to a clock signal input, and the sources of
`
`the PMOStransistors are coupled to the drain of the PMOStransistor having
`
`a gate coupled to an invented clock signal." (Ex. 1001, 4:28-37).
`
`Although the connections of the transistors look the same.transistors.
`
`|andPMOStransistors. (See Ex. 2004, Huber Dec.. § 82).
`
`Patent Owner Resp. (Paper No. 12) at 47-48
`
`

`

`°130 Patent Claim 3’s “input passtransistors”
`
`an inverted clock signal input.
`
`3. The data transfer arrangement in accordance with claim
`1, wherein the first stage of the latching sense amplifier
`comprises:
`a plurality ofinputpasstransistors each having a gate, a
`source terminal, and a drain; and
`a plurality of NMOS and PMOStransistors each having
`a gate, a source terminal, and a drain;
`
`wherein the drains of theinputpasstransistors are
`coupled to the drains of the cross-coupled latch ampli-
`fier NMOSand PMOStransistors, each source terminal
`of theinputpasstransistors is coupled to an input, the
`sources of the cross-coupled latch amplifier NMOS
`transistors are coupled to the drain of the NMOS
`transistor coupled to a clock signal
`input, and the
`sources of the PMOS transistors are coupled to the
`drain of the PMOStransistor having a gate coupled to
`
`7130 Patent (Ex. 1001) at 4:21-37
`
`

`

`Watanabe Combination
`
`Patent Owner
`
`an NMOS transistor,
`
`the drain is
`
`For
`
`identified as
`
`the
`
`terminal (considerimg source and drain) with the more
`
`positive voltage. For a PMOStransistor, the drain is
`
`identified as the terminal (considering the source and drain) with the more negative (or less positive) voltage.
`at 2:12-3:3, Fig. 2. As such, each “source” of the two pass transistors is not “directly connected” to an input throughout this preferred embodiment operation.
`
`during the °130 preferred embodiment operation. a pass transistor terminal is
`
`Patent OwnerResp. (Paper No. 12) at 48-49
`
`Petitioner
`
`Because the voltages appearing on the pass transistor terminals change
`
`considered to be a “source”at certain times, and a “drain” at other times. Ex. 1001
`
`

`

`
`
`°130 Patent
`
`Patent Owner’s Expert Testimony
`
`more negative would be the source.
`
`Q.
`
`In Figure 2.
`
`Thank you. When LT is
`
`high and LC is low, what would be the drain and
`
`the source of NMOS transistors N2 and N3 of
`
`Figure 2?
`
`A.
`
`It depends on the voltages at the top
`
`of N2 versus LT and the top of N3 versus LC.
`
`Now,
`
`you recognize that nodes IT and IC were precharged
`
`to Vpr, Vdd over 2.
`
`So whichever terminal is more
`
`positive would be the drain; whichever terminal is
`
`130 Patent. (Ex. 1001) at Fig. 2
`
`Patent Owner Expert Depo. Tr. (Ex. 1011) at 84:4-13 (cited
`in Pet. Reply at 21)
`
`

`

`Issues Raised in Patent Owner’s Response
`
`1. Whether Sukegawa and Lu teach the claimed differential data bus?
`(all claims)
`
`Patent Owner Resp. at 18-26; Petitioner Reply at 1-6
`2. Whether Sukegawa and Lu teach the claimed precharging?
`(all claims)
`
`Patent Owner Resp. at 26-37; Petitioner Reply at 7-16
`3. Whether Sukegawa and Lu render obvious claim 5?
`Patent Owner Resp. at 37-42; Petitioner Reply at 16-18
`4. Whether Sukegawa, Lu, and Watanabe render obvious claim 3?
`Patent Owner Resp. at 46-50; Petitioner Reply at 18-21
`5. Whether Sukegawa, Lu, and Hardee render obvious claim 7?
`Patent Owner Resp. at 50-55; Petitioner Reply at 21-24
`
`40
`
`

`

`°130 Patent Claim 7
`
`1. A data transfer