Case No. IPR2015-01524
`U.S. Patent No. 6,366,130
`
`Attorney Docket No.
`ELBRUS-IPR2
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.
`
`Petitioner
`
`V.
`
`ELBRUS INTERNATIONAL LIMITED
`
`Patent Owner
`
`Case:
`
`IPR2015—01524
`
`U.S. Patent No. 6,366,130
`
`PATENT OWNER'S DEMONSTRATIVE EXHIBITS FOR ORAL
`
`HEARING
`
`SCHEDULED OCT. 18, 2016
`
`Exhibit No. 2010
`
`
`U.S. Patent No. 6,366,130
`
`Attorney Docket No.
`ELBRUS-IPR2
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.
`
`Petitioner
`
`V.
`
`ELBRUS INTERNATIONAL LIMITED
`
`Patent Owner
`
`Case:
`
`IPR2015—01524
`
`U.S. Patent No. 6,366,130
`
`PATENT OWNER'S DEMONSTRATIVE EXHIBITS FOR ORAL
`
`HEARING
`
`SCHEDULED OCT. 18, 2016
`
`Exhibit No. 2010
`
`
`
`Pursuant to 37 C.F.R. § 42.70(b) and the Board's Trial Hearing Order
`
`(Paper 20), the Patent Owner submits the attached demonstrative exhibits as
`
`Patent Owner's Exhibit No. 2010.
`
`Dated: Oct. 13, 2016
`
`Respectfully submitted
`
`/clifford kraft/
`
`Clifford H. Kraft
`
`Reg. No. 35,229
`Lead Counsel for Patent Owner
`
`/joseph hosteny/
`Joseph N. Hosteny
`Reg. No. 28,020
`Back-up Counsel for Patent Owner
`
`
`
`CERTIFICATE OF SERVICE
`
`IPR 2015-01524
`
`The undersigned hereby certifies that the foregoing Patent Owner's
`
`Demonstratives for Oral Hearing, Exhibit 2010 was served on Oct. 13, 2016
`
`by filing this document through the Patent Review Processing System as
`
`well as delivering a copy via electronic mail upon the following attorneys of
`
`record for the Petitioner:
`
`Naveen Modi
`
`naveenmodi@paulhastings.com
`
`Dated: Oct. 13, 2016
`
`Respectfully submitted
`
`/clifford kraft/
`
`Clifford H. Kraft
`
`Reg. No. 35,229
`
`/joseph hosteny/
`Joseph N. Hosteny
`Reg. No. 28,020
`
`
`
`IPR-2015-01524
`
`US. Patent No. 6,366,130
`
`Patent Owner
`
`Hearing Oct. 18, 2016
`
`Slide 1
`
`
`
`INTRODUCTION
`
`The Patent Owner will argue the following:
`
`1) The combination of Sukegawa and Lu fails to teach
`or suggest precharging two buses to Vpr = K * Vdd,
`where K is between 0 and 1.
`
`Patent ownerresponse, paper 12, p. 18.
`
`2) There is no differential data bus (second bus)
`taught or suggested in either Sukegawa or Lu.
`
`Patent ownerresponse, paper 12, p. 17.
`
`Slide 2
`
`
`
`INTRODUCTION
`
`The ‘13O Patent
`
`A data transfer arrangement. The data transfer arrangement includes two
`
`active pull up/active pull down bus drivers and a voltage precharge source.
`A differential bus is coupled to the bus drivers and to the voltage precharge
`source. A latching sense amplifier is coupled to the differential bus and
`serves as the bus receiver. The bus drivers operate in a precharge phase
`and a data transfer phase. The bus receiver operates in an analogous but
`opposite manner, i.e., when the bus drivers are in the precharge phase, the
`bus receiver is in the data transfer phase and when the bus drivers are in
`the data transfer phsae, the bus receiver is in a precharge phase.
`
`‘130 patent, Ex. 1001, Abstract
`
`Slide 3
`
`
`
`INTRODUCTION
`
`The inventive breakthrough of the
`
`‘13O Patent was NOT the
`
`advantages of precharging a bus to
`
`an intermediate value — that was
`
`known in the art.
`
`The inventive breakthrough was:
`
`a differential bus....
`
`a differential data bus....
`
`wherein the differential bus and the
`
`differential data bus are precharge[d] to a
`
`voltage Vpr between Vdd and ground
`
`‘13O Patent, Ex. ‘I001, claim 1.
`
`_
`Slide 4
`
`
`
`ARGUMENT OF PATENT OWNER
`
`The entire last limitation of claim 1 reads:
`
`“"whe1*ei11 the differential bus and tile tlitfei-t~I1I'i;1l (lulu
`
`luv. are p1'ech.z11'g~e to 21 voltage Vpr between Vcld and
`gl‘01Il1(l, where Vpr = K“~‘Vd(l, and K is 21 p1'ecl1a1'ging
`voltage factor.”
`
`Claim 1 of the ‘13O patent requires inter
`alia, “a differential bus coupled to the bus
`drivers and to the voltage precharge
`source” and “a first stage including a cross-
`coupled latch coupled to a differential data
`bus.”
`
`“wherein the differential bus and the
`
`differential data bus are I0FeChar9e(d) to 3
`voltage Vpr between Vdd and ground,
`where Vpr=K*Vdd, and K is a precharging
`voltage factor.
`
`Patent Owner Response, paper 12, p. 18
`
`Patent Owner Response, paper 12, p. 26-27
`
`Slide 5
`
`
`
`ARGUMENT OF THE PETITIONER
`
`The Petitioner cites Sukegawa for the differential bus.
`
`l)ilTeI‘eIIliu| hum
`
`Petition: P. 17
`
`The Patent Owner does not contest that this is a differential bus and
`
`that it is precharged.
`
`Slide 6
`
`
`
`ARGUMENT OF THE PETITIONER
`
`The Petitioner then cites Sukegawa for the differential
`
`data bus.
`
`FiI~.l ’sl:I.*_:t'
`
`“Sukegawateachesthat its latching sense amplifier(shown in purple) includes a
`first stage (shown in light blue) with a cross-coupled latch coupled to a differential
`data bus (shown with pink lines below).”
`
`Petition: p. 19, line 5.
`
`Slide 7
`
`
`
`ARGUMENT OF THE PATENT OWNER
`
`The Petitioner admits:
`
`“Further, Sukegawa discloses that the differential data bus is precharged to a
`
`Voltage Vdd. See, e. g., Sukegawa 9:4-7.”
`
`Patent Owner response, paper 12, p. 27, line 2 and Petition, paper 1, p. 26, line 8.
`
`Sukegawa totally fails to meet the limitation of Claim 1 of the ‘13O patent
`just recited.
`
`Patent Owner response, paper 12, p. 27, line 4.
`
`Slide 8
`
`
`
`ARGUMENT OF THE PETITIONER
`
`The Petitioner then attempts to combine Lu with Sukegawa
`
`stating:
`
`"But one of ordinary skill in the art at the time of the
`
`alleged invention of the ‘B0 patent would have modified
`
`Sukegawa so that the differential data bus is precharged to
`
`an intermediate voltage of Vdd/2 rather than Vdd.”
`Petition, paper 1, p. 26, line 9.
`
`“This reasoning is disclosed by, for
`
`example, Lu."
`Petition, paper 1, p. 26, line 21.
`
`Slide 9
`
`
`
`ARGUMENT OF THE PATENT OWNER
`
`$5:
`
`‘lbl
`
`$5
`
`‘Tbsp
`
`¢2
`
`WL BWL-|¢-i QWLE
`
`‘#3
`
`Lu,Ex. 1008, Fig. 4.
`
`Because Lu JSSC has neither a voltage preoharge source Vpr nor transistors oorre-sponding
`to N5 and N7 in Figure A (from the ‘13D patent), the bit-line halves in Lu are floating during the
`preoharge interval. Thus their voltages can change as the result of leakage currents and/or noise coupling.
`So while they might be initially precharged to “nearly half VDD," the bit—line voltage later in time can vary.
`
`Even ignoring the fact thatthe required Vpr is missing, “K" in Lu JSSC is therefore not fixed at a single value.
`
`Ex. 2004, Huber Dec., 1] 74.
`
`Slide 10
`
`
`
`ARGUMENT OF THE PATENT OWNER
`
`THE CLAIMS REQUIRE TWO BUSES CHARGED TO @
`
`“wl1erei11 the (lifft'l‘(‘llfiiIl bus and the differ:-ntizul daltn
`
`hlls are p1'ecl1a1‘ge to a voltage Vpr between Vdd and
`ground, where Vpr = K""Vdd._, and K is a precharging
`voltage factor.”
`
`Slide 11
`
`
`
`ARGUMENT OF THE PATENT OWNER
`
`The combination of Sukegawa and Lu fails to teach or suggest
`precharging two buses to Vpr = K * Vdd, where K is between
`0 and 1.
`
`Patent Owner response, paper 12, p. 18.
`
`There simply is no primafacie case of obviousness!
`
`Slide 12
`
`
`
`ARGUMENT OF THE PATENT OWNER
`
`There is no differential data bus (second bus) taught
`or suggested in either Sukegawa or Lu..
`
`Patent ownerresponse, paper 12, p. 17'.
`
`Slide 12
`
`
`
`ARGUMENT OF THE PATENT OWNER
`
`In electronics, a bus is defined as “a common path
`along which power or signals travel from one or
`several sources to one or several destinations.” Thus, a
`
`bus has a span or distance between a source and a
`destination, and transfers data from one to the other.
`
`The nodes labeled N3 and N4 in Figure 1 have neither
`source nor destination, and do not form a bus.
`
`Patent Owner’s Expert, Ex. 2004, Huber Dec., 1] 59.
`
`A bus transfers signals over a distance — it has span.
`
`ld.1I62.
`
`Under the Petitioner's argument, any points in a circuit
`
`Can be Called a bUS. Patent Owner response, paper 12, line 10.
`
`Slide 13
`
`
`
`ARGUMENT OF THE PATENT OWNER
`
`A person of ordinary skill in the art simply would not consider the pink
`annotated nodes to be a bus. While the Sukegawa nodes C (N3 and N4)
`exhibit differential voltages, they do not span any space between the
`transistors they connect to.
`
`Patent ownerresponse, paper ‘I2, p. 26 line 2.
`
`SUKEGAWAIN VIEW OF LU FAILS TO ESTABLISH A
`
`PRIMA FACIE CASE OF OBVIOUSNESS FOR
`
`CLAIMS 1, 2, 5, 6AND 9.
`
`Patent owner response, paper 12, p. 17, line 7
`
`Slide ‘I4
`
`
`
`ARUGUMENT OF THE PATENT OWNER
`
`The Patent Owner has shown the following:
`
`1) The combination of Sukegawa and Lu fails to teach or
`suggest precharging two separate buses to a value between
`Vdd and ground.
`
`2) The curcuit points N3 and N4 of Sukegawa are not a bus.
`
`Hence, the Petitioner has not met its burden to prove
`obviousness by a preponderance of the evidence.
`
`Slide 15
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