SAMSUNG EXHIBIT 1021
`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
`
`Page 1 of 14
`
`

`
`U.S. Patent
`
`Oct. 27, 1993
`
`Sheet 1 of 7
`
`5,828,241
`
`<
`
`/,
`
`%%%%%%I
`
` 2::..u....nS£
`
`m
`
`M2:
`
`.32.E_2KInI
`
`5_on
`
`65%
`
`Page 2 of 14
`
`Page 2 of 14
`
`Page 2 of 14
`
`
`
`
`

`
`U.S. Patent
`
`Oct. 27, 1998
`
`Sheet 2 of 7
`
`5,828,241
`
`101
`
`FIG. 4
`
`102
`
`Page 3 of 14
`
`Page 3 of 14
`
`
`Page 3 of 14
`
`

`
`US. Patent
`
`Oct. 27, 1998
`
`Sheet 3 of7
`
`5,828,241
`
`36
`
`FIG.3
`
`20
`
`121
`
`
`
`,+--_...._.
`
`r-4
`
`C1
`
`,-4
`
`N4
`
`02
`
`D
`
`101
`
`102
`
`C2
`
`N3
`
`PC
`
`['1SEC——---------~———-———>-
`
`PC-
`
`“'2rd
`
`Page 4 of 14
`
`Page 4 of 14
`
`
`Page 4 of 14
`
`

`
`U.S. Patent
`
`Oct. 27, 1998
`
`Sheet 4 of 7
`
`5,828,241
`
`~+m ~
`J
`J
`i
`f
`
`—
`
`,
`L
`
`4
`I
`:1
`I
`J
`
`t L» ‘
`
`4-
`
`S
`
`‘
`
`r
`
`E
`4N
`3“2%
`
`i
`~
`~1‘
`
`.
`
`1.8
`1.5
`1.4
`1.2
`
`0.8
`
`0.4
`
`A
`
`N
`7
`L T
`E i
`0.6 I *2 R
`
`r
`
`1
`
`4 *
`
`T
`
`A
`
`é
`
`+
`
`0.2
`
`-V
`
`*
`
`V
`
`O
`
`4
`
`8
`
`12
`
`16
`
`20
`
`24
`
`28
`
`32
`
`35
`
`(x1OUO;zm)
`
`FIG. 8
`
`Page 5 of 14
`
`Page 5 of 14
`
`
`Page 5 of 14
`
`

`
`U.S. Patent
`
`Oct. 27, 1998
`
`Sheet 5 of 7
`
`5,828,241
`
`290
`be ————— ——“+ ———— — — 7-
`
`- our
`
`52
`
`53
`
`51
`
`IN -
`
`50
`
`FIG‘. 10
`
`290
`m p. ———‘:—42}~—~—« p.
`
`50
`
`52
`
`54
`
`53
`
`our
`
`51
`
`FIG.
`
`77
`
`290
`be ——“~{Z>~{2>——— 5-
`
`52
`
`55
`
`55
`
`53
`
`om
`
`51
`
`[N
`
`50
`
`FIG. 12
`
`‘N
`
`50
`
`200
`-42}~+2<>-429*
`
`57
`
`58
`
`59
`
`FIG. 13
`
`OUT
`
`51
`
`Page 6 of 14
`
`Page 6 of 14
`
`
`Page 6 of 14
`
`

`
`U.S. Patent
`
`Oct. 27, 1998
`
`Sheet 6 of 7
`
`5,828,241
`
`4C
`3C
`
`
`
`(x1000p.m)
`
`FIG. 14
`
`——
`
`3
`*7
`
`OC
`
`3
`
`T
`
`—
`
`261
`
`12
`
`10
`
`r'\
`L9,
`
`{
`
`|
`8
`1‘AZ/1
`4
`6
`4 / L
`2 L A
`?
`
`5?
`
`Page 7 of 14
`
`Page 7 of 14
`
`
`Page 7 of 14
`
`

`
`U.S. Patent
`
`Oct. 27, 1998
`
`Sheet 7 of 7
`
`PVC.
`
`76
`
`F70. 77
`
`Page 8 of 14
`
`Page 8 of 14
`
`Page 8 of 14
`
`
`
`

`
`1
`SIGNAL TRANSMISSION CIRCUIT
`PR()\’II)ING AMPLIFIED UUTPUT FROM
`POSITIVE FEEDBACK OF IN'I"I~ZI{VII{DIATE
`AMPLIFIER CIRCUIT‘
`
`This application is a continuation of application Ser. No.
`O8./393,525 tiled Feb. 23, 1995, now abandoned, which was
`a continuation of application Ser. No. 07/979,085 filed Nov.
`19, 1992. now abandoned.
`This invention concerns a type of signal transmission
`circuit. More specifically, this invention concerns a type of
`signal transmission circuit wherein the signal is amplified
`and transmitted by means of the positive feedback of an
`intermediate amplifier circuit having input/output shared
`terminals.
`
`ll.‘
`
`BACKGROUND 0}‘ THE lNVliN'l‘I()N
`
`lleretofore, I'll, logic used to be the main type of
`generahpurpose logic. However, in the recent years, CMOS
`logic has replaced the 'I'I‘L logic as the main type.
`The types of (‘MOS logic include standard (JMOS logic
`(with a chip size about 20 mm and a transmission delay time
`about 80 nsec), high—speed CMOS logic (with the same chip
`size as above, and a transmission delay time about 15 nsec),
`new high speed CMOS logic (with the same chip size and a
`transmission delay time about 8 nsec), and advanced high»
`speed CMOS logic (with the same chip size and a transmis-
`sion delay time about 4 nsec).
`In a conventional LSI chip, such as a CMOS circuit
`providing a signal
`transmission circuit,
`inverters may he
`used as a driver circuit and a receiver circuit.
`
`FIGS. IILI3 show some examples of a conventional
`signal transmission circuit.
`In the circuit shown in FIG. 10, driver circuit 50 using
`inverter 52 and receiver circuit 51 using inverter 53 are
`connected to each other by wiring 200, and the signal is
`transmitted from driver circuit 50 to receiver circuit 51 by
`wiring 200, so that the so-called rounding of the signal can
`be reduced.
`'
`
`5.at
`
`40
`
`In the circuits shown in FIGS. 11-13, in the case when the
`signal transmission time becomes longer as the signal trans-
`mission distance is increased so that the time constant RC
`due to parasitic resistance and capacitance of wiring 200,
`corresponding to the delay in the signal transrnission time,
`inverter 54 (l?‘I(i. ll). inverters 55, 56 (FIG. 12), or inverters
`57——59 (FIG. 13) are connected in series between driver
`circuit 50 and receiver circuit 5l to improve the delay of the
`signal transmission time. These inverters 54—S9 act as an
`intermediate amplifier circuit, respectively.
`FIG. 14 shows a diagram otlcharacteristics illustrating the
`relationship between the power consumption of thc conven~
`tional signal
`transmission circuit and the wiring length
`shown in FIGS. 10—13.
`
`In this figure, curve OC in the case when no inverter is
`used as the intermediate amplifier circuit (the graph which
`shows the characteristics of the signal transmission circuit in
`FIG. 10) indicates that the power consumption is about 1.05
`rnW for a wiring length of 2(Ix1()()(t [KY1 (2 cm) in an LS1
`chip. In this case, the signal cycle. time is 60 uscc, the wiring
`capacitance is 0.35 l~’l‘/I tan, and there is a wiring resistance
`of 0.1 £2/square.
`Curve ZC in the case when inverter 54 is used as the
`intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 11)
`indicates that the power consuniption is about I .1 mW for a
`
`St.»
`
`60
`
`5,828,241
`
`7-
`
`wiring length of 20><1ttU0 itm. Curve 3C in the case when
`inverters 55, 56 are used as the intermediate amplifier circuit
`(the graph illustrating the characteristics of the signal trans-
`mission circuit of FIG. I2) indicates that the power con-
`sumption Ls about 115 mW' for a wiring length of 2U><1000
`,u.m. Curve 4C in the case when inverters 57—-59 are used as
`the intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 13)
`indicates that the power consumption is about 1.2 mW for a
`wiring length of 2Il><lU()(l rim.
`That is, in the conventional signal transmission circuit,
`when the wiring length is kept constant such as 2 cm, as
`more inverters 54—59 are connected in series as intermediate
`amplifiers interposed in the wiring 200 (FIGS. 10—13), the
`power consumption of the signal
`transmission circuit
`increases. When the signal transmission circuit without an
`inverter used as an intermediate amplifier as shown in FIG.
`10 is compared with the signal transmission circuit shown in
`FIG. 13 with three inverters that are used as intermediate
`amplifiers. it can be seen that while the power consumption
`of the signal transmission circuit in FIG. 10 is 1.05 mW, for
`the signal transmission circuit shown in FIG. 13, the power
`consumption is increased to 1.2 mW.
`FIG. 15 shows the relationship between the wiring length
`and the delay in signal transmission. FIGS. l0—l3 show the
`simulation results
`In FIG. 15, the ordinate represents the delay, while the
`abscissa represents the wiring length.
`For example, when the wiring length within ISI chip is
`20><l0t!0 _um (2 cm). curve OC in the case when no inverter
`is used as the intermediate amplifier circuit (the graph which
`shows the characteristics of the signal transmission circuit in
`FIG. 10) indicates a delay of about 5.5 nsec; curve 2(,‘ in the
`case when inverter 54 is used as the intermediate amplifier
`circuit (the graph illustrating the characteristics of the signal
`transmission circuit of FIG. II) indicates a delay of about 5
`nsec; curve 3C in the case when inverters 55, 56 are used
`the intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 12)
`and curve 4C in the case when inverters 57~59 are used as
`the intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 13)
`indicate a delay of about 4.5 nsec.
`That is, in the conventional signal transruission circuit,
`when the wiring length is kept constant at 2 cm, as more
`inverters 54-59 are connected in series as intermediate
`amplifiers interposed in the wiring Z00 (FIGS. 10-13), the
`delay time becomes shorter. When the signal transmission
`circuit without an inverter used as an intermediate amplifier
`as shown in FIG. 10 is compared with the signal transmis-
`sion circuit shown in FIG. 13 with three inverters that are
`used as intermediate amplifiers, it can be seen that while the
`delay of the signal transmission circuit in MG. 10 is about
`5.5 nsec, for the signal transmission circuit shown in FIG.
`13, the delay is shortened to 4.5 nscc.
`As pointed out hereinbefore, in the aforementioned con-
`ventional example, when a number of inverters are con»
`nccted as intermediate amplifiers so as to reduce the delay of
`the signal transmission, the power consumption is increased.
`This is a problem of contradiction. In addition, when the
`number of the inverters used as intermediate amplifiers is
`small, the power consumption is still high. Besides, when
`the number of the inverters used as intermediate amplifiers
`is increased. there is a limitation on the improvement of the
`delay of the signal transmission.
`FIGS. 16 and 17 show specific circuit examples of other
`(conventional signal
`transmission circuits designed for
`
`Page 9 of 14
`
`Page 9 of 14
`
`
`Page 9 of 14
`
`

`
`5,828,
`
`241
`
`3
`improving the aforementioned problems of a signal trans-
`mission circu it using inverter circuits.
`in the signal transmission circuit shown in FIG. 16, driver
`circuit 60 and receiver circuit 61 are connected by a pre-
`charge circuit 62.
`Driver circuit 60 comprises CMOS inverters 63, 64,
`driving p—typc MOS transistors 65, 67, and driving n—type
`MOS transistors 66, 68.
`input terminal IN is connected to the input of inverter 63
`and the gate of nMOS transistor 68; the output ofinvertcr 63
`is connected to the gate of pMOS transistor 65. The voltage
`applied on input terminal IN is applied as the gate voltage on
`the gate of pMOS transistor 65 and the gate of nM()S
`transistor 68, respectively.
`The inverted input terminal N»lN is connected to the input
`of inverter 64 and the gate of nMOS transistor 66, and the
`output of inverter 64 is connected to the gate of pMOS
`transistor 67. The voltage applied on inverted input terminal
`N—lN is then applied as the gate voltage on the gate ofpMOS
`transistor 67 and the gate of nM()S transistor 66 as the gate
`voltage.
`The drain of nMOS transistor 66 is connected to the drain
`of pM()S transistor 65 to form a first transistor pair, while
`the drain of nM()S transistor 68 is connected to the drain of
`pMOS transistor 67 to form a second transistor pair.
`On the other hand, receiver circuit 61 comprises HMOS
`transistors 71, 72, pMOS transistors 73-76, and CMOS
`inverters 77 and 78; nMOS transistors 71, 72 and pMOS
`transistors 73—~76 are cross—coupled to each other.
`The source of nMOS transistor 72 and the gate of pM(')S
`transistor 74 are connected to the input side of CMOS
`inverter 77; the source of nM()S transistor 7] and the gate
`of pMOS transistor 75 are connected to the input side of
`CMOS inverter 78.
`
`The precharge circuit 62 comprises nMOS transistors 69,
`70. The source of nMOS transistor 69 is connected to the
`drain of nM().’\‘ transistor 65 of the driver circuit 60 and the
`drain of nMOS transistor 71 of the receiver circuit 61; the
`source of nMOS transistor 70 is connected to the drain of
`pM()S transistor 67 and the drain of nMOS transistor 72.
`lhe gate of nMOS transistor 69 is connected to the gate
`and equalizer terminal EQ of nM()S transistor 70; the drain
`of nMOS transistor 69 is connected to the drain and VDD/'2
`terminal of nMOS transistor 70.
`
`is used in the signal
`transmission circuit
`this signal
`circuit with a large wiring length of several cm, such as the
`address circuit, etc., in the LS1 chip. As V0,)/2 prcchargcr
`functions,
`the signal
`is sent from the driver circuit 60 to
`receiver circuit 61 by prechargc circuit 62; by means of the
`nMOS transistors 71, 72 of receiver circuit 61, the diffc-r—
`ential signal of the circuit threshold voltage V,h is derived.
`This ditlerential signal
`is then converted to the CMOS
`voltage level by means of CMOS inverters 77, 78.
`lo this way, improvement can he realized with respect to
`the signal transrnissiou delay, and the power consumption
`can he reduced.
`
`FIG. 17 shows the circuit diagram of the intermediate
`amplifier circuit connected between the driver circuit and
`receiver circuit of the signal transrnission circuit shown in
`FIG. 16.
`
`In this intermediate amplifier circuit, the aforementioned
`differential signal is amplified by converting the differential
`signal to the CMOS signal, followed by reconverting the
`CMOS signal to the diifercntial signal. The conversion is
`accomplished by a receiver circuit 79 which converts the
`
`4
`differential signal of the input signal to a CMOS signal and
`a driver circuit 80 which converts the (‘MOS signal to the
`differential signal.
`Receiver circuit 79 comprises input terminal IN, inverted
`input terminal N—lN, nMOS transistors 81, 82 for converting
`the diilercntial signal to the CMOS signal, pMOS transistors
`X3—86, and CMOS inverters 87, 88 for amplifying the
`CMOS signal.
`The nM()S transistor 81 and rLMOS transistor 82 are
`connected to each other with their gates and drains con-
`nected in a crossed form; the pMOS transistor 84 and pMOS
`transistor 85 are connected to each other with their gates and
`sources connected in a crossed form.
`
`at
`
`10
`
`CMOS inverters 87, 88 are connected to the gates of
`pM()S transistors 84, 85, respectively.
`Driver circuit 80 comprises (‘MOS inverters X9, 90,
`pMOS transistors 91, 93 for converting, the (‘N105 signal to
`the ditferential signal, nMOS transistors 92, 94, output
`terminal OUT and inverted output terminal N—()U'l‘.
`The outputs of (‘MOS inverters 89, 90 are connected to
`the gates of pMOS transistors 91, 93, the inputs of CTMUS
`inverters 89, 90 are connected to the gate of nM()S transistor
`94 and the gate of nMOS transistor 92,
`However, as shown in FIGS. 1(l~—13, for the conventional
`signal transmission circuit made of CMOS inverter circuits
`connected in series, as the chip size is increased, and the
`parasitic capacitance and parasitic resistance are increased,
`delay of the signal transmission time and increase in the
`power consumption cannot be ignored anymore.
`As a replacement of the aforementioned signal transmis»
`sion circuit, the signal transmission circuit shown in Flt}. 16
`has been proposed. Compared with the CMOS inverter
`circuit, the performance of this signal transmission circuit is
`improved, with the speed increased by about 10%, and
`power consumption decreased by about 30~40‘}’Zr.
`However, in the signal transmission circuit shown in FIG.
`16, for exarrtple, when the signal
`transmission distance
`within the ISI chip becomes longer than about 20 mm, it is
`impossible to make a simple serial connection of several
`intermediate amplifiers as in the signal transmission circuit
`shown in HGS. 1043. This is a disadvantage.
`For the intermediate amplifier circuit for combining the
`driver circuit and the receiver circuit as shown in lil G. 17,
`as the differential signal has to be converted to a CMOS
`signal on the input side, while the CMOS signal has to be
`converted to a differential signal on the output side.
`the
`speed characteristic is naturally poorer than that of the
`conventional signal
`transmission circuit made of (TMOS
`inverter circuits (FIGS. 1l—13). This is a problem.
`The purpose ofthis invention is to provide a type of signal
`transmission circuit wherein the signal transmission distance
`can be increased, and the signals can be transmitted at It high
`speed and with low‘ power consumption. Another purpose of
`this invention is to provide a type oi‘ signal transmission
`circuit in which the signal is transmitted while being ampli-
`fied by the positive feedback of an intermediate amplifier
`circuit having iripr.it/oritptrt shared terminals.
`SUMMARY OF THE ll\‘VENllON
`
`transmission circuit
`This invention provides a signal
`having a driver circuit, a receiver circuit, an equalizer circuit
`for tiattcnirrg the output of the aforementioned driver circuit,
`and an intermediate amplifier circuit,
`the intermediate
`amplifier circuit being connected to input/output shared
`terminals in the wiring that connects the driver circuit and
`
`t.) It
`
`40
`
`g.tjt
`
`60
`
`Page 10 of 14
`Page 10 of 14
`
`
`Page 10 of 14
`
`

`
`5,828,241
`
`5
`receiver circuit. With the aid of the positive feedback of the
`intermediate amplifier circuit,
`the signal from the driver
`circuit
`is amplified and then transmitted to the receiver
`circuit.
`
`Before the signal transmission, the equalizer circuit flat-
`tens the signal between the driver circuit and the receiver
`circuit; the driver circuit converts the input level signal to a
`differential signal, the intermediate amplifier circuit ampli~
`fies by positive feedhacl; the dillerential signal output from
`the driver circuit and sends the amplified signal
`to the
`receiver circuit, and the receiver circuit converts the input
`differential signal to a level signal.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a circuit diagram otia signal transmission circuit
`provided with an intermediate amplifier circuit
`in an
`embodiment of the invention.
`
`FIG. 2 is a circuit diagram of the intermediate amplifier
`circuit as the main portion of a signal transmission circuit in
`an ernboditnent of the invention.
`
`FIG. 3 is a diagram illustrating the signal waveforms at
`the various nodes of the intermediate amplifier circuit in an
`embodiment of the invention.
`
`FIG. 4 is a circuit diagram illustrating the connecting state
`of the signal transmission circuit in an emhodirnent of the
`invention.
`
`.4 U»
`
`FIG. 5 is a circuit diagram illustrating the connecting state
`of the signal transmission circuit in an embodiment of the
`invention.
`
`10
`
`FIG. 6 is a circuit diagram illustrating the connecting state
`of the signal transmission circuit in an embodiment of the
`invention.
`
`FIG. 7 is a circuit diagram illustrating the connecting state
`of the signal transmission circuit in an embodirnent of the
`invention.
`
`FIG. 8 is a graph showing the relation between the wiring
`length and the power consumption ofthe signal transmission
`circuit for the simulation circuit configurations of FIGS.
`4~7.
`
`4!,‘
`
`FIG. 9 is a graph showing the relation hctween the wiring
`length and the delay of the signal transmission circuit for the
`simulation circuit configurations of FIGS. 4-7.
`FIG. 10 is a circuit diagram illustrating an example of the
`signal
`transmission circuit using conventional
`(‘MOS
`inverters.
`
`FIG. 11 is a circuit diagram illtistratirig an example of the
`signal
`transmission circuit using conventional
`(.‘M()S
`inverters.
`
`FIG. 12 is a circuit diagram illustrating an example of the
`signal
`transmissiori circuit using conventional CMOS
`inverters.
`
`FIG. 13 is a circuit diagram illustrating an example of the
`signal
`transmission circuit using conventional CMOS
`inverters.
`
`’J\'1»
`
`FIG. 14 is a graph showing the relationship between the
`wiring length and power consumption of the signal trans-
`mission circuit corresponding to the inverter connection
`configurations of FIGS.
`I.0~13 using the conventional
`CMOS inverters.
`
`6!)
`
`FIG. 15 is a graph showing the relationship hctween the
`wiring length and delay of the signal transmission circuit
`corresponding to the inverter connection configurations of
`FIGS. 10-13 using the conventional (FTMOS inverters.
`FIG. 16 is a circuit diagram ol‘ a conventional signal
`transmission circuit using the difiiercntial signal.
`
`FIG. 17 is a circuit diagram of an intermediate amplifier
`circuit used in the conventional signal transmission circuit
`using the ditlcrential signal such as shown in FIG. 16.
`RI3l"EREN(.‘E NUMERALS AS EMl’I.()YliD IN
`THE DRAWINGS
`
`1, intermediate amplifier circuit
`2, driver circuit
`3, equalizer circuit
`4, receiver circuit
`5, driving transistor
`6, driving transistor
`7, driving transistor
`8, driving transistor
`9, precharging transistor
`10, prechargng transistor
`11, precharging transistor
`12, precharging transistor
`13, precharging transistor
`14, precharging transistor
`15, precharging transistor
`16, precharging transistor
`17, transistor
`18, transistor
`19, transistor
`20, transistor
`21, CMOS inverter
`22. NAND circuit
`23, NAND circuit
`24, (‘MOS inverter
`25, (TMUS inverter
`36, CMOS inverter
`37, (‘MOS inverter
`
`l)I£S(.'RIP’lI()N O17 Pl{ILl*‘ERRED EMB()DIMI3N'I‘
`
`FIG. I is a circuit diagram illustrating an embodiment of
`the signal transmission circuit in accordance with the inven-
`tion. FIG. 2 is a circuit diagram illustrating an intermediate
`amplifier circuit as a main portion of the signal transmission
`circuit in an embodiment of the invention. FIG. 3 shows the
`waveforms of signals at the various nodes of the interme-
`diate arnplitier circuit in an embodiment of the invention.
`FIGS. 4~7 are circuit diagrams illustrating connection forms
`of signal transmission circuits in accordance with the inven-
`tion.
`
`transmission
`In these figures. A represents the signal
`circuit used in the case when the signal transrnission dis-
`tance is very long, such as when the wiring length is over 2
`cm. This signal
`transmission circuit A comprises several
`intermediate amplifier circuits 1,
`IA, Ill with the same
`circuit configuration, a driver circuit 2, an equalizer circuit
`3, and a receiver circuit 4.
`As shown in FIG. 1, in this intermediate amplifier circuit
`1, positive line LINE which connects connecting terminal 311
`of equalizer circuit 3 and input terminal 4a ofreceiver circuit
`4 is connected to input..-‘output sliarcd terminal la at node
`101, and inverted line N-LINE (where N— represents the
`negative side) which connects output terminal 3}) of equal»
`izcr circuit 3 and input terminal 4!) of receiver circuit 4 is
`connected to inputioutput shared terminal 1}) at node 102.
`There are several intermediate amplifier circuits 1. In the
`configuration shown in FIG. 1, there are three intermediate
`amplifier circuits 1, IA, and 113 connected between equal—
`izcr circuit 3 and receiver circuit 4.
`
`FIG. 2 is a circuit rliagram illustrating the specific con-
`figuration of the tirst intermediate arnplitier circuit 1.
`
`Page 11 of 14
`Page 11 of 14
`
`
`Page 11 of 14
`
`

`
`5,828,241
`
`8
`high—~speed operation can be realized in the unsaturated
`region of the transistor. As a result, the amplification opera~
`tion can be realized with the signal rise (fall) being about
`8-10 nsec faster than that suggested by the characteristics of
`the conventional signal
`transmission circuit without
`the
`intermediate amplifier circuit (curves C1, C2 in FIG. 3).
`Consequently, by means of the positive feedback of the
`intermediate amplifier circuit having input/output shared
`terminals, the signal can he amplified and transmitted at a
`high speed and with a low power consumption.
`Driver circuit 2 comprises input terminal IN, enable EN
`terminal, NAND gates 22, 23, CMOS inverters 21, 24, 25,
`pMOS transistors 26, 28, and nM(')S transistors 27, 29.
`The input terminal IN of driver ClICUll 2 is connected
`through (TMOS inverter 21 to one input terminal of NANI)
`gate 22, and the input terminal IN is also connected to one
`input terminal of NANI) gate 23.
`Enable EN terminal
`is connected to the other
`terminals of NAND gates 22, 23.
`In the driver circuit 2, in the initial prechargc state, the
`enable EN terminal is at L level, while node N1 and node N2
`on the output sides of NAND gates 22, 23 are at 11 level.
`On the other hand, equalizer circuit 3 comprises BLR
`node with the balance signal applied to it, precharge
`(referred to as PC hereinafter) node and nMOS transistors
`30—32.
`The BLR node is connected to the drain of nM()S
`transistor 30 and the drain of nMOS transistor 31, and the
`BLR node becomes the power source voltage V,,,,/2 in the
`initial precharge state.
`The PC node is connected to the gates of nMt)S transis-
`tors 30, 31, and 32. In the initial prccharge state, the PC node
`enters the 11 level; in the drive state, the PC‘ node changes
`from 11 level to L level; in the precharge state,
`it changes
`from I. level to H level.
`
`input
`
`The drain of pMOS transistor 26 of driver circuit 2 is
`connected to the sources of nMOS transistors 30, 32 of
`equalizer circuit 3; the drain of pMOS transistor 28 of driver
`circuit 2 is connected to the source of nM()S transistor 31
`and the drain of iLM()S transistor 32 ot‘ equalizer circuit 3.
`"llie equalimr circuit 3 can flatten the output of the driver
`circuit 2.
`
`5
`
`10
`
`35
`
`.
`
`30
`
`35
`
`4!’)
`
`7
`1 Comprises
`interrnediate amplifier circuit
`In FIG. 2,
`input/output shared terminals 1/1, lb, driving pMOS tran~
`sistors 5, 7, and nMOS transistors 6, 8, prechargiug pMOS
`transistors 9—12 and nMOS transistors 13—16, as well as
`switching nMOS transistors 17, 18 and pMOS transistors 19,
`20.
`
`Connected to input/output shared terrninal 1a are the drain
`of pMOS transistor 5, the drain of nMOS transistor 6, the
`source of nMOS transistor 18, and the source of pMOS
`transistor 20.
`
`Connected to the gate ofpMOS transistor 5 are the drains
`of pMOS transistors 9, 10, the gate of pM(')S transistor 11,
`and the drain of nM(.)S transistor 17.
`
`Connected to the gate of nMOS transistor 6 are the drain
`olpMOS transistor 19, the gate of nMOS transistor 15, and
`the drains of rMOS transistors 13, 14.
`In addition, the drains of pMOS transistors 11, 12, the gate
`of pMOS transistor 10 and the drain of nMOS transistor 18
`are connected to the gate of pMOS transistor 7, and the drain
`of pMOS transistor 20, the gate of nM()S transistor 14, and
`the drains of nM()S transistors 15, 1.6 are connected to the
`gate of nMOS transistor 8.
`Besides, the drain of pM()S transistor 7 and the drain of
`nM()S transistor 8 are connected to output terminal lb.
`When intermediate amplifier circuit
`1
`is in the initial
`precharge state, pMOS transistors 5, 7 and nMOS transistors
`6, 8 are all in OFF (nonconductive) state.
`In this case, the voltage at nodes 101 and 102 becomes the
`intermediate voltage VDDQ; gate node N1 of pM()S tran~
`sistor 10 and gate node N2 of pMOS transistor 11 become
`the high level (referred to as “H level” hereinafter); and gate
`node N3 of nM()S transistor 15 and gate node N4 of nM()S
`transistor 14 become the low level (referred to as “L level”
`hereinafter). This is because, in the initial precharge state,
`the PC terminal hecomes the H level, while the NPC
`terminal becomes the L level.
`
`When intermediate amplifier circuit 1 is in the driving
`state, the voltage levels at node 101 and node 102 start
`drifting from V0,)/'2,
`the intermediate voltage of power
`source voltage V0,), to the II level and I. level, respectively.
`The characteristics at this point are represented by point D
`in FIG. 3.
`
`In this case, for the cross—connc-cted transistor pair of
`nM()S transistor 17 and pM()S transistor 19 and the tran-
`sistor pair of nM()S transistor 18 and pM OS transistor 20,
`the effective threshold values become equal to the threshold
`voltage V.,. of the respective transistor.
`Consequently, as node 101 enters the [I level and node
`102 enters the I ,levcl, the threshold voltages at node 101 and
`node 102 are separated from each other by a threshold
`voltage 1 V7, and node N2 changes from II level to 1. level,
`while node N4 changes from L level to H level.
`In this case, pMOS transistor 5 and nMOS transistor 8
`become ON (conductive state).
`As node 101, which has heen on II level, is driven further
`to an even higher H level, while node 102, which has been
`on L level, is driven further to I. level, a positive feedback
`takes place for node 101 and node 102, and hence the circuit
`1 can operate as an intermediate amplifier circuit.
`That is, for intermediate amplifier circuit 1, as shown by
`the characteristic diagram of FIG. 3 the signal waveform in
`the signal transrnission region is split in two on the inter-
`mediate voltage level (point I) in FIG. 3). On one hand
`(point D1 in FIG. 3), there is a steep rise. On the other hand
`(point D2 in FIG. 3), there is a steep lall. Coiiscqticntly, a
`
`45
`
`St}
`
`till
`
`On the other hand, receiver circuit 4 comprises output
`terminal OUT, inverted output terminal N—()U’I‘, PC terminal
`with the preeharge signal applied to it, inverted PC terminal
`N~PC, nMOS transistors 33~35, CMOS inverters 36, 37,
`pMOS transistors 38440, and pM()S transistor 41.
`In the receiver circuit 4, node 101 of the positive line is
`connected to terminal 4a, while node 102 of the inverted line
`is connected to terminal 4b.
`Terminal 4a of the receiver circuit 4 is connected to the
`source of HMOS transistor 33, the drain of nMOS transistor
`. 34, and the gate of nMOS transistor 35.
`On the other hand, terminal 417 of receiver circuit 4 is
`connected to the drain of riMOS transistor 33, the gate of
`nMOS transistor 34, and the drain of nM()S transistor 35.
`The source of UIVIOS transistor 34 is connected to the
`input of CMUS inverter 36. the drains of pMOS transistors
`38, 39, and the gate of pM()S transistor 40. The source of
`nM()S transistor 35 is connected to the input of CMOS
`inverter 37, the gate of pMOS transistor 39, and the drains
`of p?.\/10$ transistors 40, 41.
`The output side of CMOS inverter 36 is connected to
`inverted output terminal N—()U’l‘, while the output side of
`(‘MOS inverter 37 is connected to output terminal (i)U'l'.
`
`Page 12 of 14
`Page 12 of 14
`
`
`Page 12 of 14
`
`

`
`
`
`1828,24 l
`
`10
`9
`configuration of FIG. 6 with two stages of the intermediate
`is connected to the gate of nMOS
`The PC terminal
`amplifier circuit set in place. Curve 4N shows the relation
`transistor 33, while inverted PC.’ terminal N—PC is connected
`between the wiring length and the power consumption ofthe
`to the gates of pMOS transistors 38, 41.
`signal transmission circuit for the circuit eoririguratioii of
`For this rgggivgf cjrcuii 4, in {hg jnjfiat prfichafgc grate’
`5 FIG. 7 with three stages of the intermediate amplifier circuit
`node N3 and node N4 emu the 11 lever, pg iemnmii carers
`set in place-
`the II level, inverted PC temztirtal N~P(f enters the L level,
`As the results shown in FIG. 8 are compared with the
`and output terminals OUT and N—OU'I‘ become L level.
`results shown in FIG. 14, which show the relationship
`'n;¢-m7 in ihc drive 513(3) the PC igrmmat Changes from H
`bclwecn POW” CU“5UmPll0“ imvvl and Wlrlng lcnillll
`level to L level, inverted PC terminal N—PC changes from I.
`level to H level, and the precharge state of signal transmis— 10 (XIOOG Mm)
`In the 5lg“3l
`lrafismlsslm Cllcull Wllh “I5
`sign Cir¢u,'1A;S 1-chased,
`conventional (‘MOS inverters connected in series in the
`
`3:
`
`Ella”! Comlhllraumls "_f HGS‘ 1043’ H F“ be 5°C” film
`As a result, node 101, node 102, node N3 and node N4
`when the wiring length is 20 (_><1{)0O,um), tor curve ZN with
`enter the floating state.
`one stage of the intermediate amplifier circuit 1 set in place
`In this case, as enable terminal EN changes from I. level
`15 as shown in FIG. 8, the power consumption is about 0.75
`to H level. and input terminal IN enters the II lcvcl, node NI
`mW (as compared with l.l rnW for the conventional curve
`enters the I, level, while node N2 remains oi) the II level;
`2C as shown in FIG. 14), that is, there is a reduction of about
`hence, node 101 of LINE is driven from intermediate
`0.35 mW in the power consumption.
`voltage V171,./2 to H level, and node 102 ofthc inverted LINE
`For curve 3N for the configuration with two stages of the
`is driven from intermediate voltage \«’,,,,/2 to the I. level, and
`3” ititerrncdiate amplifier circuit
`1 connected in place,
`the
`thus the Signal is mmsmmcd 10 mcciver Circuit 4.
`power Cansumpmn
`abm” 0'9 mvif (35 mmpalcd Will: 1'13
`Consequently, at the receiver circuit 4, node N4 enters the
`mW.f(lr ‘he C.0nWm1On.a1 curve 3C as ihown in “(L 14)’
`I. level while output terminal OUT enters the II level, and
`that is, there is a reduction of about 0.23 mW in the power
`, ’_
`.
`.
`.,
`_
`_
`_
`t.
`the signal transmission is completed.
`.
`,
`_
`N
`,
`FIGS. 4-7 are schematic diagrams illustrating the cort— 3; W[.‘,wn_]p Km‘
`nectirig state of the signal transmission circuit of this invcri«
`. km tulw 4N mrihé L’0.nfig.mauUn wnh mam: Stages of the
`mm’
`intermediate anipliiicr circuit
`I connected in place,
`the
`In the circuit conliouration shown in FIG. 4 between
`POW” Consumpmm about 09 ml?’ (35 wmpa»red—w]}b 1'2
`driver circuit 2 connecied to input terminal IN ariil receiver
`mw for me L-Omcmmmi} Cu“/C ‘K’ as Show? ~m H0’ 14)’
`circuit 4 connected to output terminal OUT, intermediate 30 that 15’ more is 3' mducmm Of abom “'3 m“ m the pmwr
`consumption.
`amplifier circuit 1 is not connected between node 101 of
`Consequently, compared with the signal
`transmission
`positive line LINE and node 102 of inverted line N-LINE.
`circuit using conventional CMOS inverters connected in
`Although this coriliguratiori is not related to an embodiment
`series, the signal trarisrnission circuit of the invention can
`of the invention, it is presented for convenience of expla-
`reduce the power consumption by about 0.254).} mW.
`nation.
`FIG. 9 is a graph illustrating the relatioiisliip between the
`wiring length and the delay for the simulation circuit con-
`figurations shown in FIGS, 4—7.
`In FIG. 9, the ordinate represents the delay (nsec), and the
`Jk./'1
`, ahscima represents the wiring length (X1000 itm).
`In FIG. 9, curve ON shows the relati