SAMSUNG EXHIBIT 1020
`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
`
`Page 1 of 8
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`

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`U.S. Patent
`
`Apr. 2. 2002
`
`Shectl «£2
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`US 6,366,133 B1
`
`Bus drivers Precbarge Bus limits Bus rocicvcr
`Ciititlit
`
`FIGJ.
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`

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`US. Patent
`
`A9122, 29:12
`
`8116432 csf 2
`
`US 6,366,131} Bi
`
`V53
`
`FIG.2.
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`

`
`’
`
`0
`
`2
`
`5'
`
`1
`HIGH SPEED LOW POWER DATA
`TRANSFER SCHEME
`
`2
`DETAILED DESCRIPTION OF THE
`PREFERRED EXEMPLARY EMBODIMENTS
`
`US 6,366,130 Bl
`
`This application claims priority from US. Provisional
`Patent Application No. 60/120,531, filed Feb. 17, 1999, the
`disclosure of which is incorporated herein by reference in its
`entirety.
`
`BACKGROUND OF THE INVENTION
`
`Lit
`
`FIG. 1 illustrates a data transfer arrangement circuit 10
`that includes two bus drivers 11, 12, a precharge circuit 13,
`and two complementary bus lines 14, 15. The bus lines are
`inputs to a bus receiver 16 that is arranged as a latching sense
`amplifier.
`The two bus drivers are complementary and consist,
`preferably, of two active pull up/active pull down bus
`rivers.
`10 d .
`
`.
`.
`.
`1. Field of the lnvention
`The present invention relates to a data transfer scheme,
`.
`,
`and more Pam-culaflv to a high Wgcd and low POW“ CMOS
`Operation ofthe data transfer arrangement consists oftwo
`.
`,
`"
`°
`hases: A bus
`recharae base and a data transfer hase.
`data transfer scheme.
`p
`p
`D p
`‘P
`1)
`2‘ Description of mu, prior A”
`p Duringthe bus precharge phase,‘the_ control
`input PR
`T0day’s requirements for electronic circuits require high D (?On,l§O.1 S1%mg]f(g bi” greychlérgc f"Cl;l:i1[3)fu1S glgh mg
`speed. Additionallv,
`the circuits should be as small and
`Slgm mlm 5
`ml’ P A56 O
`U? lral
`a a .m Ion) an
`sim le as possible’ due to the ever increasin
`number of
`DC (Complement phase of dual-rm data funcmml arc low’
`-
`p»
`l
`-
`,
`,,
`-
`,-
`,
`g
`The true phase driver on transistors 20 and 21 and the
`circuits that are crowding today s chip deVices. Furthermore,
`_
`.
`I
`,
`_.
`p 7
`.
`.
`circuits for data transfer should not be sensitive to circuit
`(fomplememphase dnwr on mmfs1510“ 2“ and 23 are In hlgh
`Parameter mismatches noise
`and deviations in various :0 lmpedancé Slaw an.d bmh bus hues are Cguallzed and pm’
`a
`had Voltages
`’
`‘
`charged to a potential VP, (buses precharging voltage level)
`pp
`D ‘
`through the turned on transistors 24, 25 and 26.
`SUMMARY OF THE INVENTION
`During the data transfer phase, the control input PR is low.
`The present invcmjon pmvidgs 3 high spccd and law V The signal inputs become dillerential: DTis high and DC is
`power CMOS data transfer arrangement that includes two ‘"5 WW: and V159‘ V’€1'S?1: OD‘? Offhc dT1"€Y5
`15 Pulled “P and
`active pull up/‘pull down bus drivers, a differential bus that
`‘—‘h3Tg‘35 ‘he 3PPT0PU3l§ bu‘ 1113‘: {mm the P5e‘fhaY:‘%°d le“'°‘l
`preeharges to a specific voltage level and a latched differ-
`V,» loward 3 “TOW P0319“? Vdd_V: (‘lfhefe V; 15 1“? ‘mesh’
`ential sense amplifier that serves as a bus receiver.
`Old Voltage 0f ‘be P11” “P NMQS ”3Y1515l01’ ilflhfi ilF1V'3T)» Al
`_
`,
`,
`-.
`.4
`-.
`,
`r
`In accordance with 0% Cmbodimcm of the present
`the same time, the other driver is pulled down and discharges
`invention, 3 data Harmer arrangement mdudes two bus
`the opposite bus line from the preeharged luel.Vp,. towards
`drivers, a voltage precharge source,
`a differential bus
`3 m_0l° ll“gall"e llivel V5.5 (8I0U“d)- This proy ides a dif1"er-
`coupled to the bus drivers and to the voltage precharge
`emlalvollagel +dV and "llv llom llle P‘efl““g1“SleV‘” V1"
`source, and a latching sense amplifier coupled to the differ-
`belwcffn mm and Complenlelll bus lllles‘ _ lo Plmllfle pmp“
`Cmial bus
`operation of the bus receiver (the sensing amplifier), the
`.
`.
`d_l‘“2"V,.'
`.
`In
`with anode e".’l"“l¥”“‘*“‘ of the
`l?$§§?$’§§ Efiliiiit 8‘l?§’53.°§tiv. il~ii:'i;$3‘ZL‘li§J2e§§?§;' ff:
`invention, the latching sense amplifier is arranged as a cross
`.
`.
`.
`.
`”
`~
`coupled latched amplifier
`basis to obtain high frequency of data transfer through the
`'
`bus.
`iD£:n::;!Or:l}:l:::V(?/ggls2::/:r:::[:iS(:(2?::§‘:f ‘SE lgrefiburfi
`FIG. 2 illustrates sensing amplifier 16. Preferably. the
`A
`down bus’ driven
`’
`‘
`P
`P P
`*0 sensing amplifier is a cross—couplcd latched amplifier.
`Thus
`the present
`invention provides a data transfer
`The Sensc amplifier Opemles in two phascs’ 3 pwchalgc
`zm_m";ncm that Oparmeg at a mob Qpged and us“ low
`phase and a data transfer phase. However,
`the sensing
`'°
`,
`‘
`5‘
`'1
`’
`amplifier operates opposite to analogous phases of the bus
`power. The data transfer arrangement is faster because the
`driver
`A
`_
`_
`.
`'
`bus voltage swing passes directly to high gain nodes of the 45
`_ when the “onmll lnplll CLK ls low and lb”. bus .dll.V6l ls
`cross-coupled latched amplifier. Additionally, the data trans—
`lll
`lllc ddla llallsllfljl mode’ lb“ sellslllg alllpllllcl lS.lll lllc
`fer arrangement uses a lower number of stacked transistors
`Plecllalge, mode‘
`rlle ClOSS'C0llpl°d ,lal°lled ampllfiel
`ls
`coupled between the Supply voltage and the high gain nodes
`lsolaled lmm llle POW“ buses (llanslslols 30 and 31 are
`when compared to the prior art. Additionallv, the arrange—
`merit according to the present invention is less sensitive to 50 lllmcd Opllll
`deviations in voltage sources and the deviation of threshold
`T“ln5l5l0_l5 32 and 33 3”?‘ lllmsd 0“ and lllusa lhC_l?“5
`voltage concerns of the input transistors. Additionally, the
`Voltage _5Wmg R5595 10 the mlemal mldes Ir _(P051l1Ve
`arrangement
`is less sensitive to circuit parameter
`bl“3Y.V51ng1°‘Y31l1m‘3“3alP0l1“°flh9 $<“-115mg amplifier) and
`mismatches, data bus common mode noise and power bus
`IC (DCSQUVC binary 5lflgl‘~"l’3ll dam lnpul Phase‘
`lmcmal
`noises.
`55 point of the sensing amplifier) of the latched amplifier. The
`Other features and advantages of the present invention
`lllllplll “Odes (ll bolll llylllllnlc gal“ llle Plccllalged lo V431
`will be understood upon reading and understanding the
`and the Collllllemenlaly Olllpllls QT (mlc plus“ Of d‘lal'”lll
`detailed description of the preferred embodiments below, in
`‘lala Olllplll Slgllal) and QC (wlllplelllelll Phase of dll“.l’lall
`conjunction with reference to the drawings, in which like
`Olllplll ‘lam Slgllal) of lllc Sellslllg ampllflel become lllgll
`numgrals rgprcgcnt “kg ¢.]¢,mem5_
`on When the control input CLK is high and the bus driver is
`fl ,
`,
`,
`in the precharge mode, the sensing amplifier is in the data
`BRIEF DESCRIPTION OF THE DRAWINGS
`transfer mode. Transistors 32 and 33 are turned of and
`FIG 1
`IS 3 Schbmiillc Of
`21 dlfffife-111131 data l1'é11'1Sf€F
`isolate the internal nodes IT and IC of the latched amplifier
`arrangemwnt In 3CC’0fdaI1C€ Wllh the PFCSCII1 iUVCD1i0H; and
`from the bus lines. The cross—coupled latched amplifier is
`HG. 2 is a schematic of a circuit for a sense amplifying 65 connected to power buses (transistors 30 and 31 are turned
`latch for use in the data transfer arrangement illustrated in
`on) and it begins to amplify the low voltage swings of the
`FIG. 1.
`internal nodes IT and IC to full logic levels. The output node
`
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`

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`US 6,366,130 Bl
`
`4
`
`3
`of one of the dynamic gates is discharged to ground and the
`appropriate output QT or QC of the sensing amplifier
`becomes low.
`
`What is claimed is:
`1. A data transfer arrangement comprising:
`two bus drivers;
`The use of domino output stages in accordance with the
`a voltage precharge source;
`present invention instead of static inverters is necessary to
`a differential bus coupled to the bus drivers and to the
`avoid leakage currents and output glitches, which may
`voltage precharge source; aid
`appear because potentials of nodes IT and IC are approxi-
`a latching sense amplifier coupled to the differential bus;
`mately equal to V , during the operating cycle of the bus
`wherein the latching sense amplifier comprises:
`driver. Weak PM6S transistors 34 and 35 are preferably
`a first stage including a cross-coupled latch coupled to a
`included in the sensing amplifier to help prevent output
`differential data bus‘ and
`.
`an output stage coupled to an output of said first stage;
`gh,mheS'
`.
`.
`wherein the output of the first stage is coupled to an
`we (lam Ufmsfcr alrangembnl m aC.CmdanC€ Wnh the
`in m of the Om ul Sta C,
`‘
`present invention provides an increase in speed due to the
`.p
`.
`.
`g ’
`.
`.
`differential low voltage swing bus driver in combination
`wherein the dlficremlal bus and the dlfferemml (Ema bus
`with the use of the latched differential sense amplifier as the
`are precharge to a vpltage Vpr between \ dd and
`bus receiver.
`§:f1)::f:f:::::€ Vpr=K vdd’ and K 1S a pmchargmg
`A further increase in speed is attained with the data
`2.The dtata transfer arrangement in accordance with claim
`lramfer arrangement due 10 the pun up/pun dgwn bus
`1 whcmin the bus dn-WIS comprise aclivc puH_up and ac“-W
`drivers, which provide equal low differential voltage swings
`+dV/’ —dV in both bus lines. This allows both bus lines to be :0 puH_dOwn bus drivers.
`active during the data transfer phase, eliminates the rieces—
`3‘ The data transfer armnnemem in accordance with C1“-m
`shy to use special circuits for holding the precharged level
`1 wherein ms 55'‘ Stage if the hitching SW86 amplifier
`and leads to a reduction in the capacitance load ofthe driver.
`Cémprises:
`3
`The buses prcchargmg [0 the 5P“?‘fi° 1eW,} bclweeff
`a plurality of input pass transistors each having a gate, a
`ground and \/a,(\/p.r=K*V,,d, where K=‘/3 forpthe ideal M05 35
`Source terminal’ and a drain; and
`model) also provides: equal charge and discharge driver
`3 mm“ _ of NMOS, and PMOQ trangqorg each havmfl
`currents l¢,,7=ldL,,,, provided by the NMOS pull up follower
`p
`I_y
`V
`‘)
`.
`‘I
`(E
`d
`"
`D
`,
`ram’
`a
`and the NMOS pull down switch,
`respectively, and
`a gin’ a sour“? lamina ‘ all
`lraflswmrs “.6
`therefore, equal dilferential voltage swings dV in both
`Whcrem the drains . of the Hip“? 13355
`charged and discharged bus during the data transfer phase 3“
`;OU}3i2(‘)O‘1'hc‘d;:[:§f lbs .L\r(_)&s_LO1{§1f3'd Mich amphi
`Pdtf:+dV=Irh,,Ddfl/C‘GAD; and _dV=Id(h,i wdifjtcl GAD ‘Ch
`er i
`.
`5 ant’
`,
`.lId[]%1..Slt)IS,C2tL sottrce termina
`represents the driver pull up output current (which provides
`at ‘me mpm passjuianslsmrs ls Coupled m ‘.m mpm’ me:
`the CLOAD Charging from V” up 10 V“); Idm mprcscms [ho
`sources of the cross-coupled latch ‘ ainphficr NMOS
`driver pull down output current (providing the (‘LOAD dis-
`transistors are Coupled to [hf film“ ?f the NMOS)
`charging from VP, up 10 V55); CLOAD represents the bus 35
`transistor couple)d to a clock signal
`input, and the
`lines’ cornpacitances; +dV represents the bus voltage change
`Soufccs of 3:6 IMOS Ilanslslolf am Coupled [0 the
`up from VP, during data transfer phase; —dV represents the
`drain of mg I‘]IVfi{)S‘_”a'nIS1,S1Or havmg a gale Coupled to
`bus voltage change down from VP, during data transfer
`4 §%HC1iV:'Ttf Q?‘ Slgnd mpmf
`d
`.th ‘1 .
`1
`phase; and T4,, represents the data transfer phase duration.
`'7h) 6. 3 :1 Fans er arridngeilegt T aChC,O: éncé W,‘
`L1.afl”:n
`The buses precharging to the specific level between ground 40 " V‘ gs”? 1 3 Output stage 0 t 6 am ml" Sense ‘imp I H
`and VM also provides high noise immunity due to active
`mmpnsesj
`,_
`_
`_
`mode for both buses that equal low output resistances of the
`a plumlny of mpm lrarllslslms each having 3 gam’ 3 Source
`drivers in pull up and pull down mode and; low total power
`lcrmmali and 3 dmlni and
`consumed by drivers during the cycle of operation (transfer
`3 Pal‘ Of C1'055‘°0“P1€_d P-MOS mm5l5l01”5 each h3ViD8 3
`Pius pmcharggy
`gate, a source terminal, and a drain;
`The latched sense amplifier is faster due to the bus voltage
`3 fir“ PMOS l1'3U5l5l‘“ having 3 Sales 3 509133 lamina},
`swing passing directly to the high—gain nodes IT and IC of
`{md 3 drains ‘he gal‘? 591113 C0Ul31Cd 10 3 Clock Signal
`the cross- coupled latched amplifier, the lower number of
`mill“; lb‘ SUUICV bfimg Coullled 10 lh“ SOUTCE5 Of the F55‘
`stacked transistors that are connected between the supply
`Offhe C1'0$'C0UP15d PMQS lY"U15lv‘310Y'3§ an‘? the f"-lralfl
`voltage Vdd(or Va) and nodes IT andlC, the fact that during 5.3
`bemg C"“Pl‘7d l0 the dram 0f m6 firs‘ 01 1119 mp“
`latching of the IT and K‘, nodes, the nodes are charged by
`1F3H5lSl0YS; and
`a source
`K*Vdd and (1-K)*Vdd jnsigad of simply Vdd, Additionally,
`a second PMOS transistor having a gate,
`the speed of the latched sensing amplifier is efiected little by
`lfifmiflfll, and 3 drain, I118 gate being COUp1':d 10 it C1OCk
`the deviation of voltage V1,, and the deviation of the thresh-
`signal input; the source being coupled to the source of
`Old Vgltage of [he input transigjofs.
`a second of the cross—coupled PMOS transistors; and
`In addition to the higher speed and low power consump—
`lhc dram Wing C0UPl3d 10 the drain of ‘he Secmld Of the
`tion of the data transfer arrangement in accordance with the
`1”PU1 “anslslorsé
`present invention, the arrangement is also less sensitive to
`Wheféifl Ihfi SOUl'C€S Oflhc iI1p1lllf&DSiSl0fS are COUPIBG 10
`circuit parameters mismatching, data bus common mode
`3 SOUFCC Of an NMOS U'8DSiSl0r having 3 gate COUpl€d
`noise and power buses’ noises since both drivers are active 50
`10 8 C1001‘: signal input;
`during data transfer phase. During the appropriate bus
`wherein the sources of the cross—coupled PMOS transis-
`precharge phase, the bus receiver is isolated from the bus
`tors are coupled to a voltage supply, the drains of the
`lines.
`cross—coupled PMOS transistors are coupled to the
`Although the invention has been described with reference
`df3iHS Of lb?» input 11’3I1SiS1OfS; and
`to specific exemplary embodiments, it will be appreciated 65
`wherein the drains of the cross—coupled transistors pro-
`vide a true and a complement phase of a data output
`that it is intended to cover all rnodifications and equivalents
`signal.
`within the scope of the appended claims.
`
`vi
`
`10
`
`is
`
`45
`
`.35
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`

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`US 6,366,130 B1
`
`5
`5. The data transfer arrangement in accordance with claim
`1, wherein the Voltage precharge source is configured to
`precharge the differential bus to a predetermined voltage that
`is less than a logic high voltage and greater than a logic low
`voltage.
`6; The data transfer arrangement in accordance with claim
`1 further comprising a precharge circuit coupled between the
`precharge source and the differential bus.
`7. The data transfer arrangement in accordance with claim
`2 wherein the active pull up and pull down bus drivers are to
`NMQS transistors.
`
`U:
`
`1‘
`
`3 A Tf1‘°«‘h0d Of 0P¢1'31l0“ Of 3 dam “'3U5f‘3T amlngfimfim
`wmlmsmgi
`two bus drivers;
`a Voltage precharge source;
`a differential bus coupled to the bus drivers and to the
`voltage prccharge source; and
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross—coupled latch coupled to
`a differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an
`input, and
`wherein the sense amplifier operates in two phases:
`a precharge phase and a data transfer phase;
`wherein the precharge phase operates when a control
`input clock signal is low, said phase comprising the
`steps of:
`
`6
`isolating the cross-coupled latch amplifier from a plu-
`rality of power buses by turning off an NMOS
`transistor coupled to the clock signal
`input and a
`PMOS transistor coupled to the inverted clock signal
`input;
`passing a bus voltage swing to a plurality of internal
`nodes IT and IC of the latched amplifier;
`precharging both dynamic gates to Vdd; and
`
`Profidlng 3 high “U5 Phlw afid 3 high Ctlmplemfim
`phase of a data output signal; and
`
`wherein the data transfer phase operates when a control
`input clock signal is high, said phase comprising the
`Steps Of;
`isolating the internal nodes of the latched amplifier
`from the bus lines by turning off the pass input
`transistors;
`to
`connecting the cross—coupled latched amplifier
`power buses by turning on an NMOS transistor
`coupled to the clock signal
`input and a PMOS
`transistor coupled to an inverted clock signal input;
`amplifying each low voltage swing of the internal
`nodes to full logic levels;
`discharging an output node of one of the dynamic gates
`to ground; and
`providing a low true phase and a low complement
`phase of the data output signal.
`
`V
`Pace 6 of 8
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`{:22 INTER PARTES LREZLEXAMINATION CERTIFICATE {L9?.4th}
`United States Patent
`
`M‘)? Number:
`
`£35 6366.130 C1
`Certificate Issued:
`Aug. 4? 2934
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`Pcediesny at at
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`Circuit
`
`Page 7 of 8
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`

`
`1
`INTER PARTES
`
`US 6,366,130 Cl
`
`2
`
`REEXAMINATION CERTIFICATE
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`ISSUED UNDER 35 U.S.C. 316
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`'2:
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`THE I’A’I‘El\'T IS HEREBY AMENDED AS
`INDICATED BELOW.
`
`Matter enclosed in heavy brackets [ ] appeared in the
`patent, but has been deleted and is no longer a part of the 10
`patent; matter printed in italics indicates additions made
`to the patent.
`
`AS A RESULT OF REE}LAMINATION._ IT HAS BEEN
`DETERMINED THAT:
`A
`
`15
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`The patentability of Claims 1-2 and 5-7 is confirmed.
`New claim 9 is added and detenninod to be paicntable.
`Claims 3-4 and 8 were not reexamined.
`9. The dam transfer arrangement czfclaim I wherein the 30
`output slage includes cross-coup]:-dfiacdback.
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`>3
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