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` DR. WILLIAM R. HUBER
` UNITED STATES PATENT AND TRADEMARK OFFICE
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` Case IPR2015-01524
` Patent No. 6,366,130
`- - - - - - - - - - - - - - - - - - - - - - -
` SAMSUNG ELECTRONICS COMPANY, LTD.,
` Petitioner
` v.
` ELBRUS INTERNATIONAL LIMITED
` Patent Owner
`- - - - - - - - - - - - - - - - - - - - - - -
`
` DEPOSITION OF DR. WILLIAM R. HUBER
` Pinehurst, North Carolina
` Friday, July 1, 2016
`
`Reported by:
`Karen K. Kidwell, RMR, CRR, CRC
`JOB 109222
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`SAMSUNG EXHIBIT 1011
`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
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`Page 1 of 121
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` DR. WILLIAM R. HUBER
` UNITED STATES PATENT AND TRADEMARK OFFICE
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` Case IPR2015-01524
` Patent No. 6,366,130
`- - - - - - - - - - - - - - - - - - - - - - -
` SAMSUNG ELECTRONICS COMPANY, LTD.,
` Petitioner
` v.
` ELBRUS INTERNATIONAL LIMITED
` Patent Owner
`- - - - - - - - - - - - - - - - - - - - - - -
`
` DEPOSITION OF DR. WILLIAM R. HUBER
` Pinehurst, North Carolina
` Friday, July 1, 2016
`
`Reported by:
`Karen K. Kidwell, RMR, CRR, CRC
`JOB 109222
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`SAMSUNG EXHIBIT 1011
`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
`
`Page 1 of 121
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` DR. WILLIAM R. HUBER
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`Page 2
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` July 1, 2016
` 8:54 a.m.
`
` Deposition of DR. WILLIAM R. HUBER held at
`Homewood Suites by Hilton, 250 Central Park
`Avenue, Pinehurst, North Carolina, before Karen K.
`Kidwell, RMR, CRR, CRC.
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` DR. WILLIAM R. HUBER
`A P P E A R A N C E S:
` PAUL HASTINGS
` Attorneys for Petitioner
` 1170 Peachtree Street, NE
` Atlanta, Georgia 30309
` BY: STEVEN PARK, ESQ.
`
` and
` 1117 South California Avenue
` Palo Alto, California 94304
` BY: JOSEPH RUMPLER II, ESQ.
`
` NIRO LAW
` Attorneys for Patent Owner
` 181 West Madison Street
` Chicago, Illinois 60602
` BY: JOSEPH HOSTENY, ESQ.
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` DR. WILLIAM R. HUBER
` FRIDAY, JULY 1, 2016, PINEHURST, NORTH CAROLINA
` 8:54 a.m.
` P R O C E E D I N G S
` -oOo-
` WILLIAM R. HUBER
`being first duly sworn, testified as follows:
` EXAMINATION
` BY MR. PARK:
` Q. Dr. Huber, good morning.
` A. Good morning, Attorney Park.
` Q. Could you state your full name and
`address for the record?
` A. William Huber, 108 Lewallen Court, West
`End, North Carolina.
` Q. Dr. Huber, have you been deposed
`before?
` A. Yes, I have.
` Q. How many times?
` A. Fourteen.
` Q. You know it right off heart?
` A. Joe asked me that yesterday.
` Q. Have they all been in the context of an
`expert position?
` A. Yes.
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` DR. WILLIAM R. HUBER
` Q. And in patent cases, all 14 of those?
` A. Yes.
` Q. When was the last time you were
`deposed?
` A. About a year ago. And that's in my CV,
`which is in my report.
` Q. And who were you retained by?
` A. Let me take a look.
` Q. Well, let me -- let's just --
` A. The law firm was Sterne Kessler.
` Q. Okay.
` A. The client was -- I'd have to look.
` Q. Okay. Have you ever been an expert in
`a PTAB proceeding?
` A. Yes.
` Q. How many of those?
` A. Two.
` Q. Is this --
` A. Prior to this one.
` Q. This is your third?
` A. Yes.
` Q. What were your other two?
` A. They were both -- the client was Sterne
`Kessler, and they were obviously patents in the
`
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` DR. WILLIAM R. HUBER
`memory area.
` Q. And were you on the petitioner side or
`were you on the patent owner side?
` A. I was on the patent owner side in both
`of those.
` Q. Okay. So you've obviously been through
`several depositions. You know the rules. I'll
`just go through a couple of the ground rules.
` You understand you're here under oath
`today?
` A. I do.
` Q. You understand I'll be asking you some
`questions, and you're going to try to answer my
`questions to the best of your ability?
` A. I understand.
` Q. Is there any reason why you can't fully
`answer any of my questions today?
` A. I don't believe so.
` Q. You also understand, in PTAB
`proceedings, once this cross-examination starts,
`you're not allowed to talk about the substance of
`your testimony either that you've had or in the
`future with your attorneys during breaks or
`anything?
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` DR. WILLIAM R. HUBER
` A. Understood. Until the deposition is
`over, correct?
` Q. That's correct. We'll take -- we'll
`take periodic breaks. But, of course, if you ever
`need a break, please feel free to ask me.
` A. All right.
` Q. When were you retained in this matter?
` A. Probably February of this year --
`January or February of this year.
` Q. Who contacted you?
` A. Anthony Brown.
` Q. Do you know what law firm he is or if
`he's a lawyer?
` A. It's not a law firm. I don't remember.
`Joe will know.
` Q. Okay.
` A. He represents the patent owner.
` Q. Is that Elbrus?
` A. Yeah. He doesn't work for Elbrus per
`se.
` Q. And how long after you were contacted
`were you actually retained?
` A. Within two weeks.
` Q. Have you previously worked with
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` DR. WILLIAM R. HUBER
`Mr. Brown in any matter?
` A. I have not.
` Q. Have you previously worked with Elbrus,
`the patent owner, in any other matter?
` A. I have not.
` Q. Have you worked with your counsel or
`your counsel's law firm Niro in any other matter?
` A. No.
` Q. Are you currently working on any other
`projects with Elbrus or your counsel, the Niro
`firm?
` A. Only this one.
` Q. Are you being compensated for your
`time?
` A. Yes, I am.
` Q. Do you know approximately how much you
`have been compensated to date?
` A. I would have to guess.
` Q. Do you have a ballpark estimate?
` A. On the order of $50,000.
` Q. You charge by the hour?
` A. I do.
` Q. What is your hourly rate?
` A. 450.
`
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` DR. WILLIAM R. HUBER
` Q. Did you do anything to prepare for
`today's deposition?
` A. Yes.
` Q. What did you do?
` A. I read through my declaration and met
`with counsel yesterday.
` Q. Did you read through anything other
`than your declaration?
` A. I didn't read through it word by word,
`but I scanned most of the other documents.
` Q. And the other documents being the
`exhibits to your declaration?
` A. Yes.
` Q. Anything other than the exhibits to the
`declaration?
` A. I don't know that the patent is an
`exhibit, but I looked at the patents that are --
`both the asserted patent and the ones that have
`been put forth as alleged prior art.
` Q. You said you met with your attorney
`yesterday; is that right?
` A. That's correct.
` Q. How long did you meet with him?
` A. Oh, about four hours.
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` DR. WILLIAM R. HUBER
` Q. Was that here in, I guess, in the
`Pinehurst area?
` A. Yes.
` Q. Who did you meet with?
` A. Attorney Hosteny.
` Q. Anyone else?
` A. No.
` Q. Did you speak with anyone else as part
`of your preparations?
` A. No.
` Q. Okay. I think you mentioned that you
`had -- you had reviewed the asserted patent, and I
`believe you're referring to the '130 patent to
`Podlesny; is that correct?
` A. Correct.
` Q. I'm going to give you what's already
`been marked as Exhibit 1001, which is the '130
`patent. Is this the asserted patent in -- or, I
`guess, the patent at issue in this PTAB
`proceeding?
` A. Yes, it is.
` Q. Do you understand the teachings of this
`patent?
` A. Yes.
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` DR. WILLIAM R. HUBER
` Q. Can I ask you to turn to Figure 1?
` A. I have that.
` Q. There are only two figures in the '130
`patent, correct?
` A. That's correct.
` Q. And those two figures combined form the
`circuitry of the preferred embodiment; is that
`correct?
` A. Yes.
` Q. Are there any other figures depicting
`any other embodiments in the '130 patent?
` A. There are only two figures, as you
`indicated.
` Q. Is it your understanding that the
`patentee -- the present invention described by the
`patentee in the '130 patent is limited to the
`circuitry of Figures 1 and 2?
` A. No.
` Q. Why not?
` A. Well, the scope of the patent is
`defined by the claims, not just the figures.
` Q. So your understanding is the claims of
`the '130 patent are broader than the circuitry
`depicted on Figures 1 and 2; is that correct?
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` DR. WILLIAM R. HUBER
` A. I didn't say that. I said that the
`scope of the patent is defined by the claims. The
`figures show one embodiment.
` Q. So when I asked you the question,
`maybe -- maybe I -- I may have misstated the
`question. But I'm just trying to understand based
`on what you said: Are the -- do the scope of the
`claims cover circuitry broader than the circuitry
`depicted by Figures 1 and 2 of the '130 patent?
` A. They may very well. The figures do not
`limit the scope of the patent. They simply
`provide one embodiment.
` Q. So there are other embodiments, to your
`understanding, that would be different from the
`embodiment depicted by Figures 1 and 2 of the '130
`patent that could fall under the scope of the
`claims of the '130 patent?
` MR. HOSTENY: Objection. Foundation.
` THE WITNESS: It's possible that there
`may be other embodiments. But the claims define
`the scope of the patent, not the figures.
` BY MR. PARK:
` Q. Well, can I ask you: Looking at
`Figures 1 and 2 of the '130 patent, can you just
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` DR. WILLIAM R. HUBER
`give me a brief overview of what is being depicted
`here?
` A. Well, basically, if you look at Figure
`1, on the left side, there's two inputs, DT and
`DC. Those inputs are amplified, if you will, by
`the two inverter circuits which are called bus
`drivers. Those -- the outputs of those bus
`drivers then go to the data bus, which is
`indicated by LT and LC. The resulting data on
`those -- on that data bus is transmitted to the
`circuitry indicated by SA in Figure 1, and one
`embodiment of that circuitry of SA is shown in
`Figure 2.
` There you can see in Figure 2 that the
`two inputs, LT and LC, come into a cross-coupled
`sense amplifier circuitry, or at least the first
`stage of it, where they are amplified again and
`sent to -- over the differential data bus to the
`second stage of the sense amplifier. There is no
`particular number that indicates that, but it's
`the right half of Figure 2.
` And then, finally, that information or
`data is sent out over lines QT and QC. So it's a
`data -- data detection transmission system.
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` DR. WILLIAM R. HUBER
` Q. You mentioned that, in Figure 1, the
`data signals are DT and DC; is that correct?
` A. That's correct. That's the incoming
`data, yes.
` Q. Are those complementary signals?
` A. Not -- not all the time, no.
` Q. What do you mean?
` A. Well, let me refer to the
`specifications so I get the terminology right.
`Okay. If you look at Column 2, starting around
`line 15, "Signal inputs DT (true phase of
`dual-rail data function) and DC (complement phase
`of dual-rail data function) are low."
` So at the beginning of the operation,
`they're both low. Later on, they become
`complementary.
` Q. So during the precharge phase, the
`signals DT and DC are low, but during the data
`transfer phase, they become complementary; is that
`correct?
` A. I believe that's correct. Let me,
`again, look further in the specification where
`that's indicated.
` Yes. Again, in Column 2 about line 23,
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` DR. WILLIAM R. HUBER
`it says, "During the data transfer phase, the
`control input PR is low. The signal inputs become
`differential." For example, "DT is high and DC is
`low or vice versa."
` Q. You mentioned that DT and DC are
`connected to inverters. Are you referring to the
`NMOS transistors N1, N2, N3 and N4?
` A. That's correct, in Figure 1.
` Q. Is it your understanding that one of
`skill in the art looking at Figure 1 would
`understand that, for example, the inverters
`depicted by transistors N1, N2 could be modified
`to a different topology such as a PMOS transistor
`instead of a NMOS transistor?
` A. In general, you can make inverters with
`one PMOS and one NMOS transistor or with two NMOS,
`as is shown in Figure 1. That would not -- well,
`we'll get on to some more questions, I'm sure.
`The claims define -- at least one of the claims
`defines the topology of those inverters.
` Q. But your understanding is one of skill
`in the art would understand that the N1, N2
`circuitry could be modified to a PMOS transistor
`and an NMOS transistor and still fall within the
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` DR. WILLIAM R. HUBER
`scope of the present invention; is that correct?
` A. That's a different question. If you
`look at Claim 7 -- and it's short, so I'll read
`it. "The data transfer arrangement in accordance
`with Claim 2, wherein the active pull-up and
`pull-down bus drivers are NMOS transistors."
` So what you're proposing, that is,
`changing the N1, for instance, to a PMOS
`transistor, would not be within the scope of that
`claim.
` Q. Would it be within the scope of Claim 1
`to change N1 to P1? And by "P1," I mean a PMOS
`transistor.
` A. Understood. That would not appear to
`violate Claim 1.
` Q. Do you see any reason why one of skill
`in the art would not modify the circuits to
`replace N1 with a PMOS transistor to operate the
`circuit?
` A. Well, it depends what you're intending
`to do. As your witness said -- your expert said,
`a PMOS transistor takes somewhat more area to lay
`out. But if that's not a major concern, then it
`could be changed to a PMOS and still function
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` DR. WILLIAM R. HUBER
`properly.
` The issue, I think, is not whether you
`can do it, it's would it then violate the claim.
`Claim 1 would be satisfied. Claim 7 would not.
` Q. Besides the possibility that a PMOS
`transistor would take more space than an NMOS
`transistor, is there any other reason why one of
`skill in the art would not modify this circuit to
`replace N1 with a PMOS transistor?
` A. Well, again, Dr. Baker proposed a
`couple other reasons which in this particular
`circuit I don't think were applicable. So I would
`see no reason to not use a PMOS except that it
`does take slightly more area.
` Q. Is there any benefit to using a PMOS
`even though it takes more area than an NMOS
`transistor?
` A. Yeah, let me have my declaration, and
`I'll point you to where I discuss that.
` Q. Okay. And we can get to there. I just
`wanted to ask you some -- some questions about the
`patent before we get into your declaration.
` A. Well, there's -- the declaration
`specifically answers your question.
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` DR. WILLIAM R. HUBER
` Q. Okay.
` A. So I'd like to point to where that is.
` Q. Sure. Let me ask you this similar
`question. Going back to Figure 1 of the '130
`patent: Would one of skill in the art appreciate
`that transistor N5, N6, and N7 could be modified
`to PMOS transistors and still fall within the
`scope of the present invention described by the
`'130 patent?
` MR. HOSTENY: Objection to scope.
` THE WITNESS: I don't see anything in
`the claims that would -- that would not be
`satisfied by a PMOS arrangement for N5, N6, and
`N7. Obviously, some of the voltages would have to
`change.
` BY MR. PARK:
` Q. Is there anything in the '130 patent
`that would inform a person of skill in the art not
`to use PMOS transistors in place of N5, N6, N7?
` MR. HOSTENY: Same objection.
` THE WITNESS: Well, clearly the
`description is written assuming that those are
`NMOS transistors, but I don't see anything that
`would prevent you from using PMOS transistors if
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` DR. WILLIAM R. HUBER
`the appropriate voltage changes were made.
` BY MR. PARK:
` Q. Is there anything in the '130 patent
`that would inform a person of skill in the art not
`to use a PMOS transistor in place of N1 or N3
`transistors?
` A. Well, as I've said, Claim 7 makes it
`clear that they are to be NMOS transistors.
` Q. But with respect to Claim 1, you said
`that change would be fine, correct?
` A. I said it would not violate Claim 1,
`that's correct.
` Q. And there's nothing in the patent that
`teaches one of skill in the art that you wouldn't
`want to modify N1 and N3 to PMOS transistors,
`correct?
` A. It's silent on that question. It
`doesn't talk about PMOS. It only talks about
`NMOS.
` Q. Is -- does the fact that it's silent
`mean that one of skill in the art would not want
`to modify N1 and N3 to PMOS transistors?
` A. Well, it --
` MR. HOSTENY: Same -- I'm sorry. Same
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` DR. WILLIAM R. HUBER
`objection. Scope.
` THE WITNESS: It teaches NMOS. It
`doesn't say anything about PMOS. So if one of
`ordinary skill in the art looked at this, they
`would say, "Okay. Here's an inventor. He has
`more knowledge than I do. He's making it NMOS.
`However, I may want to make it PMOS. There's
`nothing in there to prevent me from doing so
`except Claim 7."
` BY MR. PARK:
` Q. You had explained to me earlier kind of
`a high level of how the circuit depicted by
`Figures 1 and 2 operate. Could you explain now
`the precharging operation that Figures 1 and 2
`provide?
` A. All right. Starting with Figure 1 in
`the -- in the precharge condition. First of all,
`the voltage Vpr, as defined in the -- in the
`patent with the specification in the claims is a
`voltage between Vdd and ground.
` And let's say -- for simplicity, let's
`assume it's Vdd over 2. In the precharge
`condition, the signal PR is high, which turns on
`transistors N5, N6, and N7, thereby coupling the
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` DR. WILLIAM R. HUBER
`Vpr voltage to the true data line, LT, through
`transistor N5 and also to the complement data bus
`line LC through transistor N7. In addition,
`transistor N6 is turned on and that couples the
`two data bus lines together.
` And "data bus line" is incorrect. It's
`differential bus lines. So that's the precharging
`on Figure 1.
` And remembering then that LT and LC are
`both precharged to Vpr, carry that over to Figure
`2. And in the precharge condition for Figure 2,
`that would mean that the clock signal itself is
`low and the inverted clock, which comes from the
`first inverter at the top left of Figure 2, the
`inverted clock would be high.
` So that inverted clock turns on
`transistor N2 and couples the LT signal to the IT
`line, which is part of the differential data bus.
`And transistor N3 turns on and couples the LC
`signal to the IC line, which is the other half of
`the differential data bus.
` So the differential data bus is
`precharged through transistors N2 and N3 from the
`differential bus signals LT and LC. So all of
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` DR. WILLIAM R. HUBER
`those lines, both the differential bus lines and
`the differential data bus lines, are precharged to
`Vpr, which I've said may be Vdd over 2.
` Q. Can you describe now what happens after
`the precharge phase?
` A. Well, looking first at Figure 1, the
`precharge is turned off when the PR signal goes
`low. And shortly thereafter, although there's no
`wave form shown -- shortly thereafter, the DT and
`DC data signals that we talked about become
`differential instead of the same, instead of both
`low, as they were previously.
` So let's assume that DT goes high.
` Can I write on here?
` Q. Sure.
` A. I'm going to assume that DT is high and
`DC is low.
` Q. Why don't you mark with a red pen so we
`can distinguish what you've written, and then
`we'll identify that as a separate exhibit.
` A. All right. (Drawing) DT is high, which
`I've noted in red. DC is low. And depending on
`the data, those can be inverted, but we will
`assume that for now.
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` DR. WILLIAM R. HUBER
` All right. If DT is high, that is at
`Vdd, that will pull up the true line, the LT half
`of the differential bus to a high level, which
`turns out to be Vdd minus VT, V threshold of N1.
` The -- with DC low, that turns off
`transistor N2, thus allowing the true line LT to
`rise up to that level, Vdd minus VT, N1.
` On the other side, DC being low turns
`off transistor 23 -- I'm sorry -- transistor N3.
`And DT being high turns on transistor N4, thereby
`pulling the complement line LC to ground, which
`I'll indicate by Vss. So that establishes the
`condition of the differential bus lines, which are
`then transferred over to the sense amplifier.
` Q. So the operation you just described
`where the DT and DC signals provide complementary
`data, that's during the same clock cycle where the
`transistors N2 and N3 are on, correct?
` A. I'm sorry. You're going to have to go
`back and tell me that again.
` Q. Absolutely. The operation you
`described where DT and DC provide complementary
`data signals, thereby pulling up the LT line to
`Vdd minus VT and pulling down the LC line to Vss,
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` DR. WILLIAM R. HUBER
`that operation occurs during the same clock cycle
`where transistors N2 and N3 are on; is that
`correct?
` A. No. Oh, you're looking at a
`different -- you're looking in Figure 2 for
`transistors N2 and N3.
` Q. Yes, I'm sorry.
` A. Oh, okay.
` Q. I'm sorry. That was confusing. I
`failed to realize they're all similarly numbered.
` A. Yes.
` Q. Yes. When I said transistors N2 and
`N3, I was talking about the transistors labeled in
`Figure 2 as N2 and N3.
` A. No, they're not on because the
`precharge cycle is ended and the -- let me see.
`These are still in precharge. Let me refer back
`to the specification because the -- these circuits
`operate one in precharge and the other active and
`then -- then go to the opposite state.
` So when the -- Figure 1 is active,
`which I've been talking about, Figure 2 is in the
`precharge state. So yes, N2 and N3 -- transistors
`N2 and N3 in Figure 2 would be on while Figure 1
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` DR. WILLIAM R. HUBER
`is in the active state, and thereby transferring
`the signals on LT and LC to the nodes IT and IC.
` Q. So the question I'm asking is: When
`the precharge voltage Vpr is transferred to IT and
`IC through the transistors N2 and N3 of Figure 2,
`do those transistors stay on the whole time as the
`data signals, then provide complementary signals
`onto the LT and LC lines and then get coupled to
`the Figure 2 N2 and N3 transistors?
` A. That's a long question.
` Q. It is. Do you want me to try to break
`it up?
` A. Yeah, please.
` Q. Sure. You mentioned that, during a
`precharge phase, LT and LC would be precharged to
`Vpr, correct?
` A. Yes.
` Q. And I believe you're saying, during
`that same phase, transistors N2 and N3 of Figure 2
`will be turned on because clock will be low and
`that inverted clock would be high, correct?
` A. That's correct.
` Q. And because N2 and N3 of Figure 2 are
`on, the Vpr precharge of LT and LC will then be
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` DR. WILLIAM R. HUBER
`provided to IT and IC charging the differential
`data bus of Figure 2, correct?
` A. Precharging that differential data bus
`to Vpr, that's correct.
` Q. Does the transistors N2 and N3 of
`Figure 2 shut off before the DT and DC signals
`provide complementary data?
` A. No.
` Q. During the precharge phase when the
`differential data -- strike that. Let me start
`over.
` During the precharge phase when the
`precharge Vpr voltage is provided to the
`differential data bus of Figure 2, is the
`circuitry of Figure 2 operative in any other way?
` MR. HOSTENY: Objection. Foundation.
` THE WITNESS: It has power supplied to
`it. I don't -- I guess I'm not sure what you mean
`by "operative."
` BY MR. PARK:
` Q. You had mentioned that the circuitry
`described by Figures 1 and 2 of the Podlesny
`patent operates in two phases, a precharge phase
`and a -- I believe a data -- data transfer phase,
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` DR. WILLIAM R. HUBER
`correct?
` A. I didn't use that word, but it's all
`right.
` Q. But that's correct, though, it does
`operate in two different phases?
` A. Yeah, it's sort of a push/pull if you
`like.
` Q. So I'm just trying to understand: When
`the precharge phase is in operation, what is the
`data transfer phase? What operation is occurring?
` A. You have to specify precharge of which
`one. And I think maybe the issue here is there's
`a setup phase before the data becomes
`complementary. And at that point, both of these
`circuits, both Figure 1 and Figure 2, are in
`precharge condition.
` In other words, the data bus -- the
`differential bus and the differential data bus are
`both precharged to Vpr. Then once the data starts
`flowing, they go into this push/pull mode where
`one is active and the other is in precharge and
`vice versa.
` Q. So you're saying there's a third phase?
`There's a setup phase, there's a precharge phase,
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` DR. WILLIAM R. HUBER
`and there's a data transfer phase; is that
`correct?
` A. That's my understanding, yes.
` Q. Can you -- can you point to me where in
`the patent it describes the setup phase that
`you're referring to?
` A. Okay. That whole description is in
`Column 2 starting at roughly line 9. And it goes
`on for quite a ways. I don't know if you want me
`to read that or not, but it's described there.
` Q. I'm just looking for wherever you think
`there is support for a third setup phase outside
`of the precharge phase and the data transfer
`phase.
` A. Where I get that is from the fact --
`the citation I read previously where it said,
`line 15 -- or line 16, "Signal inputs DT" -- and
`I'll skip the parenthetical -- "and DC are low.
`The true phase driver on transistors 20 and 21 and
`the complement phase driver on transistors 22 and
`23 are in high impedance state, and both bus lines
`are equalized and precharged."
` So that -- when there's basically no
`data, that I would call the third phase of
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` DR. WILLIAM R. HUBER
`operation. Once the data starts, it'll flow in a
`continuous manner. And then you have the other
`two active precharge, precharge active conditions.
` Q. The paragraph that you just read starts
`in line 14 and states, "During the bus precharge
`phase, the control input PR" -- and I'll skip the
`parenthetical as well -- "is high and signal
`inputs DT and DC are low."
` Do you see that?
` A. I see that.
` Q. Isn't the patent teaching that that's
`actually during the precharge phase and not a
`separate setup phase?
` A. It -- yes, it calls that the bus
`precharge phase. I think in practice, though,
`there is an initialization phase where everything
`gets precharged.
` Q. Are you talking about the initial
`start-up on power-up or do you mean before every
`data is transferred?
` A. Before the first data is transferred.
` Q. Are you saying that the precharge that
`you referred to where the differential data bus of
`Figure 2 is precharged to Vpr only happens in that
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` DR. WILLIAM R. HUBER
`initial setup phase before the very first data is
`transferred?
` A. I'm sorry. Can you read that again?
` Q. Sure. Are you saying that the
`precharge that you referred to where the
`differential data bus of Figure 2 is precharged to
`Vpr occurs in the initial setup phase that you
`just described before the very first data is
`transferred?
` A. It does occur then, yes.
` Q. Does it occur any other time?
` A. It occurs whenever the differential bus
`is in the precharge condition and the clock signal
`is low, thus turning on transistors N2 and N3 in
`Figure 2.
` Q. So before every new complementary data
`is provided, the precharge phase would precharge
`both the differential bus and the differential
`data bus of Figure 2, correct?
` A. I would have to go back and look in
`detail at that. I don't know if that's the case.
` MR. HOSTENY: A tardy objection.
`Scope.
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` DR. WILLIAM R. HUBER
` BY MR. PARK:
` Q. Let me refer you to Column 2, line 46.
`Do you see where it says, "When the control input
`clock is low and the bus driver is in the data
`transfer mode, the sense amplifier is in the
`precharge mode"? Do you see that?
` A. Exactly, yes.
` Q. So is it your understanding, when clock
`is low, the transistors N2 and N3 of Figure 2 are
`active, correct?
` A. When the clock is low -- and, again,
`I'm going to write in red on Figure 2 (Drawing) --
`that means that the signals driving transistors N2
`and N3, their gates, are high. So they are turned
`on, that's correct.
` Q. And that also means that the bus driver
`of Figure 1 is in data transfer mode, correct?
` A. Excuse me. There's not a direct -- in
`other words, clock does not come into Figure 1
`except in the sense amplifier in Figure 2. So
`there's no direct correlation between clock and
`the precharge. But from the text, that would be
`correct.
` Q. If the bus driver is in data transfer
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` DR. WILLIAM R. HUBER
`mode, then LT and LC are not precharged, correct?
`They are being either pulled up to Vdd or pulled
`down to VSS, correct?
` A. I'm sorry. Read that again?
` Q. Sure.
` A. I'm looking -- N2 and N3 are in both
`figures. It's confusing.
` Q. Sure. If the bus driver of Figure 1 is
`in data transfer mode, then LT and LC are not
`being precharged to Vpr, they're actually being
`pulled up to either Vdd, minus Vth, I think is
`what you s
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