Paper No. ____
`Filed: June 26, 2015
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`Filed on behalf of: Samsung Electronics Co., Ltd.
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`By: Steven L. Park (stevenpark@paulhastings.com)
`Naveen Modi (naveenmodi@paulhastings.com)
`Paul Hastings LLP
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
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`
`
`U.S. Patent No. 6,366,130
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`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,366,130
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`
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`

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` Petition for Inter Partes Review – Patent No. 6,366,130
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`TABLE OF CONTENTS
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`V.
`
`C.
`
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 .................................. 1
`III.
`PAYMENT OF FEES UNDER 37 C.F.R. §§ 42.15 AND 42.103 ................ 2
`IV. GROUNDS FOR STANDING AND IDENTIFICATION OF
`CHALLENGE ................................................................................................ 2
`BACKGROUND ............................................................................................ 4
`A.
`The ’130 Patent .................................................................................... 4
`B.
`Prosecution History of the ’130 Patent ................................................ 6
`C.
`Reexamination History of the ’130 Patent ........................................... 7
`D.
`Prior Art Raised in This Petition .......................................................... 7
`VI. CLAIM CONSTRUCTION ........................................................................... 8
`A.
`Latching Sense Amplifier (Claims 1, 3) .............................................. 9
`B.
`Stage (Claims 1, 3, 9) ......................................................................... 10
`VII. DETAILED EXPLANATION OF UNPATENTABILITY ......................... 11
`A.
`Brief Description of the Prior Art ...................................................... 11
`Ground 1: Sukegawa and Lu Render Claims 1, 2, 5, 6, and 9
`B.
`Obvious............................................................................................... 14
`1.
`Claim 1 ..................................................................................... 14
`2.
`Claim 2 ..................................................................................... 27
`3.
`Claim 5 ..................................................................................... 29
`4.
`Claim 6 ..................................................................................... 29
`5.
`Claim 9 ..................................................................................... 31
`Ground 2: Sukegawa, Lu, and Watanabe Render Claim 3
`Obvious............................................................................................... 33
`D. Ground 3: Sukegawa, Lu, and Hardee Render Claim 7 Obvious ...... 45
`VIII. STATEMENT REGARDING OTHER PETITION .................................... 47
`IX. CONCLUSION ............................................................................................. 48
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`i
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`TABLE OF AUTHORITIES
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` Page(s)
`
`Cases
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ................................................................................ 27, 34, 47
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ............................................................ 9
`
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................ 9
`
`In re Yamamoto,
`740 F.2d 1569 (Fed. Cir. 1984) ............................................................................ 8
`
`Statutes
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`35 U.S.C. § 102(a) ..................................................................................................... 3
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`35 U.S.C. § 102(b) ..................................................................................................... 3
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`35 U.S.C. § 102(e) ..................................................................................................... 3
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`35 U.S.C. § 103 .......................................................................................................... 1
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`35 U.S.C. § 103(a) ................................................................................................. 3, 4
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`35 U.S.C. § 112 ...................................................................................................... 3, 7
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`Other Authorities
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`37 C.F.R. § 42.1(b) .................................................................................................. 48
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`37 C.F.R. § 42.8(b)(1) ................................................................................................ 1
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`37 C.F.R. § 42.8(b)(2) ................................................................................................ 1
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`77 Fed. Reg. 48,756 (Aug. 14, 2012)......................................................................... 8
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`77 Fed. Reg. 48,764 (Aug. 14, 2012)......................................................................... 8
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`Modern Dictionary of Electronics (7th ed. 1999) .................................................... 11
`
`ii
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`

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`Petition for Inter Partes Review — Patent No. 6,366,130
`
`Exhibit
`No.
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`LIST OF EXHIBITS
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`Description
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`U.S. Patent No. 6,366,130 (“the ’130 Patent”) to Podlesny et al.
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`1002
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`Declaration of Dr. R. Jacob Baker
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`1003
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`File History of the ’ 130 Patent
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`Excerpts from File History of the Inter Partes Reexamination of the
`’ 130 Patent
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`1005
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`U.S_ Patent No. 5,828,241 to Sukegawa
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`1006
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`U.S. Patent No. 6,108,254 to Watanabe et al.
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`1007
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`U.S. Patent No. 6,249,469 to Hardee
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`1008
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`“Half—VDD Bit—Line Sensing Scheme in CMOS DRAM’s,” IEEE
`Journal of Solid-State Circuits, Vol. SC-19, No. 4, August 1984 by
`Lu et al.
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`1009
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`Excerpts from the Modern Dictionary of Electronics (7th ed. 1999)
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`iii
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`

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`
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`I.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner”) requests inter partes review of
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`claims 1-3, 5-7, and 9 of U.S. Patent No. 6,366,130 (“the ’130 Patent”) (Ex. 1001),
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`which Petitioner understands is assigned to Elbrus International Limited (“Patent
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`Owner”).1 This Petition shows that there is a reasonable likelihood that Petitioner
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`will prevail with respect to at least one of the challenged claims, and thus a trial
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`should be instituted. This Petition also establishes by a preponderance of the
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`evidence that the challenged claims are unpatentable under 35 U.S.C. § 103. These
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`claims should be canceled.
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`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Party-in-Interest: Pursuant to 37 C.F.R. § 42.8(b)(1), Petitioner
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`identifies Samsung Electronics Co., Ltd. as the real party-in-interest.
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`Related Matters: In accordance with 37 C.F.R. § 42.8(b)(2), Petitioner
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`identifies the following related matters. Patent Owner asserted the ’130 Patent
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`against Petitioner in a patent litigation filed on July 24, 2014, in the Northern
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`District of Illinois (case no. 1:14-cv-05691), which remains pending. Patent Owner
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`also asserted the ’130 Patent against Hynix Semiconductor, Inc. and SK Hynix Inc.
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`1 Petitioner understands that the ’130 Patent is exclusively licensed to Cascades
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`Computer Innovation, LLC.
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`1
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`

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` Petition for Inter Partes Review – Patent No. 6,366,130
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`on June 27, 2011 in the Northern District of Illinois (case no. 1-11:cv-04356), but
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`this case was dismissed on February 6, 2014. Hynix Semiconductor Inc. sought
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`inter partes reexamination (control no. 95/000,657) on January 19, 2012, but that
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`proceeding resulted in a reexamination certificate that issued on August 4, 2014.
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`Petitioner is concurrently filing a second petition for inter partes review also
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`challenging claims 1-3, 5-7, and 9.
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`Counsel and Service Information: Lead counsel is Steven L. Park (Reg. No.
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`47,842), Paul Hastings LLP, 1170 Peachtree Street, NE, Suite 100, Atlanta, GA
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`30309, Telephone:
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`(404)
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`815-2223, Fax:
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`(404)
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`685-2223, E-mail:
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`stevenpark@paulhastings.com. Back-up counsel is Naveen Modi (Reg. No.
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`46,224), Paul Hastings LLP, 875 15th St. N.W., Washington, D.C., 20005,
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`Telephone:
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`202.551.1700,
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`Fax:
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`202.551.1705,
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`E-mail:
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`naveenmodi@paulhastings.com. Petitioner consents to electronic service
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`III. PAYMENT OF FEES UNDER 37 C.F.R. §§ 42.15 AND 42.103
`Petitioner submits the required fees with this petition. Please charge any
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`additional fees required for this proceeding to Deposit Account No. 50-2613.
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`IV. GROUNDS FOR STANDING AND IDENTIFICATION OF
`CHALLENGE
`Petitioner certifies that the ’130 Patent is available for inter partes review,
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`and that Petitioner is not barred or estopped from requesting such review of the
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`’130 Patent on the grounds identified below.
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`2
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`

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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Petitioner challenges claims 1-3, 5-7, and 9 of the ’130 Patent and requests
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`that these claims be found unpatentable and canceled in view of the following prior
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`art references: U.S. Patent No. 5,828,241 to Sukegawa (“Sukegawa”) (Ex. 1005);
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`U.S. Patent No. 6,108,254 to Watanabe et al. (“Watanabe”) (Ex. 1006); U.S. Patent
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`No. 6,249,469 to Hardee (“Hardee”) (Ex. 1007); and “Half-VDD Bit-Line Sensing
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`Scheme in CMOS DRAM’s,” IEEE Journal of Solid-State Circuits, Vol. SC-19,
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`No. 4 by Nicky Chau-Chun Lu et al. (“Lu”) (Ex. 1008).
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`The ’130 Patent attempts to claim priority to provisional application no.
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`60/120,531 (“the ’531 provisional application”), filed February 17, 1999. For
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`purposes of this proceeding, Petitioner has assumed that the ’130 Patent is entitled
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`to the February 17, 1999 date.2 Lu was published more than one year before this
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`date and is therefore prior art under pre-AIA 35 U.S.C. § 102(b). Sukegawa issued
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`on October 27, 1998 and is thus prior art under pre-AIA 35 U.S.C. § 102(a).
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`Watanabe and Hardee were both filed prior to February 17, 1999 and issued after
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`that date, and are therefore prior art under pre-AIA 35 U.S.C. § 102(e).
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`Petitioner requests cancellation of the challenged claims on the following
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`2 Petitioner does not concede that the ’130 Patent claims comply with 35 U.S.C.
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`§ 112 or that they are entitled to the assumed priority date. Petitioner reserves the
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`right to raise these and other issues in a district court or another forum.
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`3
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`

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`
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`grounds:
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Ground 1: Claims 1-2, 5-6, and 9 are unpatentable under pre-AIA 35 U.S.C.
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`§ 103(a) as obvious over Sukegawa in view of Lu.
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`Ground 2: Claim 3 is unpatentable under pre-AIA 35 U.S.C. § 103(a) as
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`obvious over Sukegawa in view of Lu and Watanabe.
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`Ground 3: Claim 7 is unpatentable under pre-AIA 35 U.S.C. § 103(a) as
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`obvious over Sukegawa in view of Lu and Hardee.
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`V. BACKGROUND
`The ’130 Patent issued from U.S. Patent Application No. 09/505,656 (“the
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`’656 application”), filed February 17, 2000, and attempts to claim priority to the
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`’531 provisional application. Ex. 1001 Title Page.
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`A. The ’130 Patent
`The ’130 Patent is purportedly directed to a data transfer scheme that
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`includes two bus drivers, a precharge circuit, two complementary bus lines, and a
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`latching sense amplifier. Ex. 1001 2:1-8; Ex. 1002, ¶ 17. Fig. 1 of the ’130 Patent
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`illustrates two bus drivers 11, 12 (consisting of transistors 20, 21, 22, and 23) and
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`two complementary bus lines 14, 15 as inputs to a latching sense amplifier 16:
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`4
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`See also, e.g., Ex. 1002, ¶ 17. According to the patent, the data transfer scheme
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`operates in two phases: a precharge phase and a data transfer phase (Ex. 1001 2:12-
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`13; Ex. 1002, ¶ 18), with the bus drivers and complementary bus lines operating in
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`opposite phases to the latching sense amplifier (Ex. 1001 2:43-44; Ex. 1002, ¶ 18).
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`In other words, when the complementary bus lines and the bus drivers are in the
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`precharge phase, the sense amplifier is in data transfer phase and vice versa. Ex.
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`1002, ¶ 18.
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`
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`The ’130 Patent includes 9 claims with claims 1 and 8 being independent
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`and claims 2-7 and 9 being dependent from claim 1. Claim 9 was added during
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`reexamination. Independent claim 1 is reproduced below:
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`1. A data transfer arrangement comprising:
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`two bus drivers;
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`a voltage precharge source;
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`a differential bus coupled to the bus drivers and to the voltage precharge
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`5
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`source; aid [sic]
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`a latching sense amplifier coupled to the differential bus;
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`wherein the latching sense amplifier comprises:
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`a first stage including a cross-coupled latch coupled to a differential
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`data bus; and
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`an output stage coupled to an output of said first stage;
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`wherein the output of the first stage is coupled to an input of the
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`output stage;
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`wherein the differential bus and the differential data bus are precharge to a
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`voltage Vpr between Vdd and ground, where Vpr = K*Vdd, and K is a
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`precharging voltage factor.
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`Prosecution History of the ’130 Patent
`
`B.
`During prosecution, all claims of the ’656 application that eventually issued
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`as the ’130 Patent were initially rejected as unpatentable over prior art. Ex. 1003,
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`pp. 43-44. In response, claim 1 of the application was amended to clarify that the
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`“latching sense amplifier” comprises of a “first stage including a cross-coupled
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`latch coupled to a differential data bus” and an “output stage” coupled to the output
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`of the “first stage.” Id., p. 53. Applicants explained that the latching sense
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`amplifier disclosed by the prior art did not include two stages, whereas amended
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`claim 1 now included both a “first stage” and an “output stage” of a latching sense
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`6
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`amplifier. Id., p. 50-51. Applicants also distinguished the purported invention over
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`the cited prior art by noting the purported invention “teaches precharging the buses
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`to a specific level between ground and Vdd (Vpr = K*Vdd, where K is precharging
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`voltage factor),” rather than Vdd as taught by the prior art. Id., p. 50 (emphasis
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`added). Applicants later submitted a supplemental amendment to claim 1 to recite
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`the intermediate precharge voltage Vpr (id., p. 60-62), and a notice of allowance
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`was issued shortly thereafter (id., pp. 64-68).
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`C. Reexamination History of the ’130 Patent
`As noted above, Hynix filed an inter partes reexamination, i.e., control no.
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`95/000,657 (“the ’657 proceeding”). See Ex. 1004 (excerpts from the ’657
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`proceeding). During inter partes reexamination, claims 1-3 and 5-7 were
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`confirmed. Patent Owner also submitted new claims, but all but one were rejected
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`under 35 U.S.C. § 112. Id., pp. 134-44. This one claim eventually issued as claim
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`9. Ex. 1001 Reexam Cert. 1:20-21.
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`Prior Art Raised in This Petition
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`D.
`This Petition relies on prior art that the U.S. Patent and Trademark Office
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`(“PTO”) did not have before it or did not fully consider during prosecution and
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`reexamination. In fact, with the exception of Watanabe, none of the other prior art
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`7
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`references were cited during prosecution or reexamination.3 As for Watanabe, it
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`was cited in an Information Disclosure Statement during reexamination but was
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`never discussed or relied on in any rejection. As explained below, the prior art
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`discussed in this Petition renders obvious the claims of the ’130 Patent, especially
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`when considered in light of the declaration of Dr. R. Jacob Baker (Ex. 1002).
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`VI. CLAIM CONSTRUCTION
`In an inter partes review, the Board applies the broadest reasonable
`
`interpretation (“BRI”) standard to construe claim terms.4 Under the BRI standard,
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`claim terms are given their “broadest reasonable interpretation, consistent with the
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`specification.” In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); Office
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`Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,764 (Aug. 14, 2012). Claim
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`terms are also “generally given their ordinary and customary meaning,” which is
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`3 Hynix relied on European patent publication no. EP 0 597 231 during
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`reexamination. This European publication is related to Hardee. Hardee was,
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`however, never considered as presented herein, especially in light of the
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`accompanying expert testimony.
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`4 Petitioner notes that the district courts apply a different claim construction
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`standard and reserves its rights to make arguments based on that standard in the
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`district court.
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`8
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`the meaning that the term would have to a person of ordinary skill in the art.5 See
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`In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (quoting
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`Phillips v. AWH Corp., 415 F.3d 1303, 1312, 1313 (Fed. Cir. 2005) (en banc)).
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`Petitioner proposes a construction for a few of the claim terms below and submits
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`that the remaining terms in the ’130 Patent should be given their plain and ordinary
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`meaning under the BRI standard.
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`A. Latching Sense Amplifier (Claims 1, 3)
`Claims 1 and 3 recite the term “latching sense amplifier.” For purposes of
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`this proceeding, “latching sense amplifier” should be construed to mean “a circuit,
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`including a latch, that detects and amplifies signals.” This construction is
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`consistent with the use of the term in the claims and specification of the ’130
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`Patent. Ex. 1002, ¶ 22.
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`Neither the claims nor the specification explicitly define “latching sense
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`amplifier.” The ’130 Patent’s specification describes its latching sense amplifier to
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`include a latch (see, e.g., Ex. 1001 2:39-40, 2:48-50) for detecting (see, e.g., Ex.
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`5 A person of ordinary skill in the art at the time of the alleged invention of the
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`’130 Patent would have had an undergraduate degree in Electrical Engineering or
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`equivalent and at least two to three years of experience in the design and/or
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`analysis of data transfer circuits or the equivalent. Ex. 1002, ¶ 15.
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`9
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`1001 2:33-38, 2:64-67) and amplifying received signals (see, e.g., Ex. 1001 2:64-
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`67). See also Ex. 1002, ¶ 22. Also, latching sense amplifiers were well known at
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`the time of the alleged invention of the ’130 Patent by those skilled in the art, and
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`such individuals would have understood the term to be consistent with the
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`Petitioner’s proposed construction. Ex. 1002, ¶ 22. Indeed, Petitioner’s
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`construction is consistent with dictionary definitions of similar terms. See, e.g., Ex.
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`1009 at 679 (defining “sense amplifier” as “[a] circuit used to sense low-level
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`voltages ... and to amplify these signals to the logic voltage levels of the system”);
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`see also Ex. 1002, ¶ 22.
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`The claims additionally specify what a “latching sense amplifier” has to
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`include. Ex. 1002, ¶ 22. For example, claim 1 requires that the “latching sense
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`amplifier” include both a first stage with a cross-coupled latch and an output stage.
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`See, e.g., Ex. 1001 4:8-13; Ex. 1002, ¶ 22. Accordingly, in the context of the ’130
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`Patent, the broadest reasonable interpretation of “latching sense amplifier” is “a
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`circuit, including a latch, that detects and amplifies signals,” wherein the claims
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`further define what that circuit includes. Ex. 1002, ¶ 22.
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`Stage (Claims 1, 3, 9)
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`B.
`Claims 1, 3, and 9 recite the term “stage.” For purposes of this proceeding,
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`“stage” should be construed to mean “portion of a circuit.” This construction is
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`consistent with the use of the term in the claims and specification of the ’130
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Patent as well as dictionary definitions for the term. Ex. 1002, ¶ 23.
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`Neither the claims nor the specification explicitly define “stage.” However,
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`independent claim 1 uses the term to indicate that a latching sense amplifier
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`comprises of a “first stage” and an “output stage” and dependent claims 3 and 9
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`use the terms in context of particular circuitry found within a “first stage” and
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`“output stage” of a latching sense amplifier. See, e.g., Ex.1001 4:8-13, 4:21-23,
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`Reexam Cert. at 1:20-21; Ex. 1002, ¶ 23. Claim 1 notes that the “first stage” of the
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`latching sense amplifier must include cross-coupled latch circuitry. See, e.g., Ex.
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`1001 4:8-13; Ex. 1002, ¶ 23. In claim 3, the “first stage” is described to include
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`specific transistor circuitry and clock signals. See, e.g., Ex. 1001 4:8-13; Ex. 1002,
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`¶ 23. The “output stage” of claim 9 includes circuitry for cross-coupled feedback.
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`See, e.g., Ex. 1001 Reexam Cert. at 1:20-21; Ex. 1002, ¶ 23. The specification uses
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`the term “stages” once (Ex. 1001 3:4-5) and that usage is consistent with the
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`definition proposed here. Ex. 1002, ¶ 23. In addition, the Modern Dictionary of
`
`Electronics (7th ed. 1999) defines “stage” as “[a] single section of a multisection
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`circuit or device.” Ex. 1009 at 728. Accordingly, in the context of the ’130 Patent,
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`the broadest reasonable interpretation of “stage” is “portion of a circuit.”
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`VII. DETAILED EXPLANATION OF UNPATENTABILITY
`A. Brief Description of the Prior Art
`As explained in detail below, the prior art identified and applied in this
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`11
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Petition discloses and/or suggests the limitations of claims 1-3, 5-7, and 9. Ex.
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`1002, ¶¶ 16, 24, 30-43. For example, Sukegawa describes “a type of signal
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`transmission circuit wherein the signal is amplified and transmitted by means of
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`the positive feedback of an intermediate amplifier circuit having input/output
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`shared terminals.” Sukegawa 1:11-15; see also, e.g., Ex. 1002, ¶ 25. The signal
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`transmission circuit disclosed sought to increase the signal transmission distance as
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`well as increase the speed and lower the power consumption of a transmission.
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`Sukegawa 4:52-55; see also, e.g., Ex. 1002, ¶ 25. Sukegawa discloses that its signal
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`transmission circuit comprises of “a driver circuit, a receiver circuit, an equalizer
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`circuit, and an intermediate amplifier circuit.” Sukegawa 4:62-65; see also, e.g.,
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`Ex. 1002, ¶ 25. The intermediate amplifier circuit relies on positive feedback to
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`amplify the signal provided by the driver circuit and transmit the amplified signal
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`to the receiver circuit. See, e.g., Sukegawa 5:1-4; see also, e.g., Ex. 1002, ¶ 25.
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`Lu also describes a signal transmission system, and in particular, a sense
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`amplifier utilized by DRAMs (Dynamic Random Access Memory). See, e.g., Lu
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`Abstract; Ex. 1002, ¶ 26. Lu introduces “a sensing scheme for CMOS DRAM’s
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`[sic] in which the bit line is precharge to half-VDD.” Lu 451; Ex. 1002, ¶ 26. Similar
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`to Sukegawa, Lu discloses the need to develop signal transmission systems faster in
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`speed and lower in power consumption. See, e.g., Lu 453-54; Ex. 1002, ¶ 26.
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`Watanabe additionally relates to the transmission of signals in electronic
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`12
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`circuits. See, e.g., Watanabe Abstract, 1:10-13; Ex. 1002, ¶ 27. Specifically,
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`Watanabe introduces a “data transfer circuit incorporated in a DRAM.” Watanabe
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`3:38-39; Ex. 1002, ¶ 27. “[T]he data transfer circuit comprises a differential
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`amplifier circuit 10, an equalizing circuit 11, a data latch circuit 12, a pair of first
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`data lines 13, a pair of second data lines 14, and a pair of data output lines 15.”
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`Watanabe 3:41-44; see also, e.g., id. Fig. 1; Ex. 1002, ¶ 27. Like Sukegawa and Lu,
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`the circuit disclosed by Watanabe was motivated by a need to increase the
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`transmission speed of signals in electronic circuits. See, e.g., Watanabe. 2:52-56
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`(“No time is therefore required to equalize either data lines, unlike in the
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`conventional data transfer scheme. Hence, data can be transferred at high speed in
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`DRAM according to the present invention.”); Ex. 1002, ¶ 27.
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`Hardee is yet another prior art reference relating to signal transmission, and
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`in particular, “integrated circuit memories” and “sense amplifiers for use therein.”
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`See, e.g., Hardee 1:8-10; Ex. 1002, ¶ 28. Hardee introduces a sense amplifier
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`highlighted by three “salient” features:
`
`(1) the connection of each sense amplifier via transistors
`or other switching devices to the power supply lines
`without directly connecting together power supply lines
`for multiple sense amplifiers;
`(2) the use of local read amplifiers;
`(3) the use of local write circuitry.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`See Hardee 5:24-32; see also, e.g., Ex. 1002, ¶ 28.
`
`All the prior art references mentioned above relate to signal transmission and
`
`were motivated to improve the efficiency of such transmissions. Ex. 1002, ¶ 29. As
`
`such, one of ordinary skill in the art at the time of the alleged invention of the ’130
`
`Patent would have been motivated to combine the teachings of these references.
`
`Ex. 1002, ¶ 29.
`
`B. Ground 1: Sukegawa and Lu Render Claims 1, 2, 5, 6, and 9
`Obvious
`1.
`
`Claim 1
`“A data transfer arrangement comprising:”
`i.
`Sukegawa discloses a data transfer arrangement. See, e.g., Ex. 1002, ¶ 31.
`
`For example, Sukegawa introduces “[a] signal transmission circuit which enables
`
`the distance of signal transmission as measured by the length of the wiring
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`electrically connecting a driver circuit and a receiver circuit of the signal
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`transmission circuit to be increased, while the signal delay and power consumption
`
`are reduced.” Sukegawa Abstract; see also, e.g., id. 6:37-39, Fig. 1.
`
`“two bus drivers6;”
`ii.
`Sukegawa discloses two bus drivers. See, e.g., Ex. 1002, ¶ 31. For example,
`
`6 Petitioner has used color and annotated figures throughout this Petition to
`
`illustrate how the prior art discloses the various claimed features.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`as demonstrated below in annotated Fig. 1 of Sukegawa, transistors 26-27 and
`
`transistors 28-29 serve as bus drivers for bus lines LINE and LINE_:
`
`
`
`
`
`See also, e.g., Ex. 1002, ¶ 31. Sukegawa teaches:
`
`Driver circuit 2 comprises input terminal IN, enable EN
`terminal, NAND gates 22, 23, CMOS inverters 21, 24,
`25, pMOS transistors 26, 28, and nMOS transistors 27,
`29. The input terminal IN of driver circuit 2 is connected
`through CMOS inverter 21 to one input terminal of
`NAND gate 22, and the input terminal IN is also
`connected to one input terminal of NAND gate 23.
`Enable EN terminal is connected to the other input
`terminals of NAND gates 22, 23. In the driver circuit 2,
`in the initial precharge state, the enable EN terminal is at
`L level, while node N1 and node N2 on the output sides
`of NAND gates 22, 23 are at H level.”
`Sukegawa 8:11-23; see also, e.g., id. 9:14-21; Ex. 1002, ¶ 31.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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` “a voltage precharge source;”
`iii.
`Sukegawa discloses a voltage precharge source. See, e.g., Ex. 1002, ¶ 31.
`
`For example, as demonstrated below in annotated Fig. 1 of Sukegawa, the voltage
`
`precharge source is disclosed as BLR (see, e.g., Ex. 1002, ¶ 31):
`
`Voltage precharge source
`
`
`
`Sukegawa discloses that “BLR node becomes the power source voltage VDD/2 in
`
`the initial precharge source.” Sukegawa 8:29-31 (emphasis added), 7:29-37; Ex.
`
`
`
`1002, ¶ 31.
`
`iv.
`
` “a differential bus coupled to the bus drivers and to
`the voltage precharge source; aid [sic]”
`Sukegawa teaches a differential bus coupled to the bus drivers and voltage
`
`source. See, e.g., Ex. 1002, ¶ 31. For example, as shown below in annotated Fig. 1
`
`of Sukegawa, the differential bus LINE and LINE_ is coupled to the bus drivers
`
`(transistors 26-27 and transistors 28-29) and voltage precharge source BLR:
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`Petition for Inter Partes Review — Patent No. 6,366,130
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`FIG.
`
`1
`
`
`
`
`Voltage precharge source
`
`See also, e.g., Sukegawa 6:54-61; Ex. 1002, 1] 31. One of ordinary skill in the art at
`
`the time of the alleged invention of the ’130 Patent would have recognized that
`
`LINE and LINE_ constitute “the differential bus” because a voltage differential
`
`(i.e., a difference in voltages between the two bus lines) can develop on these two
`
`bus lines. See, e.g., Sukegawa 7:38-43; Ex. 1002, 1] 31.
`
`V.
`
`“a latching sense amplifier coupled to the differential
`bus;”
`
`Sukegawa discloses a latching sense amplifier (shown below in purple)
`
`coupled to the differential bus LINE and LINE_. See, e.g., Ex. 1002, 1] 31;
`
`Sukegawa Fig. 1 (annotated below).
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`Petition for Inter Partes Review — Patent No. 6,366,130
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`Latching sense
`amplifier
`
`FIG.
`
`1
`
` Differential bus
`
`Consistent with Petitioner’s proposed construction of “latching sense amplifier,”
`
`the circuitry identified in above in annotated Fig.
`
`1 of Sukegawa is a circuit,
`
`including a latch,
`
`that detects and amplifies signals. Ex. 1002,
`
`1] 31. Each
`
`intermediate amplifier 1, IA, and 1B provides a latch that detects and amplifies the
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`signal on LINE and LINE_. See, e.g., Ex. 1002, 1] 31; Sukegawa Fig. 2, 7: 1-826.
`
`Sukegawa discloses that “[a]s shown in FIG. 1, in this intermediate amplifier
`
`circuit 1, positive line LINE which connects connecting terminal 3a of equalizer
`
`circuit 3 and input terminal 4a of receiver circuit 4 is connected to input/output
`
`shared terminal la at node 101, and negative line N-LINE (where N— represents the
`
`negative side) which connects output terminal 3b of equalizing circuit 3 and input
`
`terminal 4b of receiver circuit 4 is connected to input/output shared terminal lb at
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`node 102.” Sukegawa 6:54-61.
`
`vi.
`
`“wherein the latching sense amplifier comprises: a
`first stage including a cross-coupled latch coupled to a
`differential data bus; and”
`
`Sukegawa teaches that its latching sense amplifier (shown below in purple)
`
`includes a first stage (shown below in light blue) with a cross-coupled latch
`
`coupled to a differential data bus (pink lines below). See, e.g., Ex. 1002, 1] 31;
`
`Sukegawa Fig. 1 (annotated below).
`
`Differential
`
`data bus
`
`
`
`‘ Latching sense
`amplifier
`
`See also, e.g., Sukegawa Fig. 2 (further disclosing circuitry of first stage). As
`
`indicated above, the circuitry identified as the first stage comprises of intermediate
`
`amplifier 1. Ex. 1002, 1] 31. Consistent with Petitioner’s proposal that “stage” be
`
`construed to mean “portion of a circuit,” the elements identified as the “first stage”
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`Petition for Inter Partes Review — Patent No. 6,366,130
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`are a portion of the latching sense amplifier circuit. Ex. 1002, 1] 31. In particular,
`
`intermediate amplifier 1 latches and amplifies voltages received through nodes la
`
`and lb, and outputs the amplified voltages through the same nodes. See, e.g.,
`
`Sukegawa 7:1-8:6; Ex. 1002, 1| 31.
`
`Sukegawa teaches that
`
`the first stage includes a cross—coupled latch
`
`consisting of transistors 10, ll, 14, and 15. See, e.g., Ex. 1002, 1] 31; Sukegawa
`
`Fig. 2 (armotated below).
`
`PMOS part of cross—coupled latch
`
`LINE
`
`1
`
`LINE.
`
`101
`
`102
`
`NMOS part of cross-coupled latch
`
`One of ordinary skill in the art at the time of the alleged invention of the ’130
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`Patent would have recognized, based on the disclosure of Sukegawa, that the cross-
`
`coupled latch comprises of transistors 10, 11, 14, and 15 because these transistors
`
`act to regenerate full logic levels (both high and low) on LINE and LINE_. See,
`
`e.g., Ex. 1002, ¶ 31; Sukegawa 9:14-21. Moreover, these transistors are cross-
`
`coupled because the output of a first transistor (e.g., 10) is tied to the input of a
`
`second transistor (e.g., 11), and the output of the second transistor (e.g., 11) is tied
`
`to the input of the first transistor (e.g., 10). See, e.g., Ex. 1002, ¶ 31; Sukegawa Fig.
`
`2. Similarly, the output of transistor 14 is tied to the input of transistor 15, and vice
`
`versa. See, e.g., Ex. 1002, ¶ 31; Sukegawa Fig. 2.
`
`The first stage of Sukegawa is also coupled to the differential data bus via
`
`LINE, LINE_ and transistors 34, 35. See, e.g., Ex. 1002, ¶ 31; Sukegawa 6:54-61,
`
`Fig. 1 (annotated below).
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`Petition for Inter Partes Review — Patent No. 6,366,