IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 4, AUGUST 1984
`
`Papers
`
`Half-VDD Bit-Line Sensing Scheme in
`CMOS DRAM’s
`
`NICKY CHAU-CHUN LU. MEMBER, IEEE, AND HU H. CHAO, MEMBER, IEEE
`
`Abstract —A sensing scheme in which the bit line is precharged to half
`VDD is introduced for CMOS DRAM’s. The study shows that the half- VDD
`bit-line sensing scheme has several unique advantages, especially for high-
`performance high-density CMOS DRAM’s, when compared to the full- VDD
`bit-line sensing scheme used for NMOS memory arrays or the grounded
`bit-line sensing scheme for PMOS arrays in CMOS DRAM’s.
`
`ca
`B T LINE
`
`I.
`
`INTRODUCTION
`
`N this paper a sensing scheme for CMOS DRAM’s in
`which the bit line is precharged to half VDD is intro-
`duced. The study shows that half-VDD bit—line sensing has
`several unique advantages, especially for high—performance
`high-density CMOS DRAM’s, when compared to the full-
`VDD bit—line sensing scheme used for NMOS memory
`arrays or the grounded bit—line sensing scheme for PMOS
`arrays in CMOS DRAM’s (n-well CMOS technology is
`assumed in this paper).
`The half-VDD bit—line sensing was used in early NMOS
`DRAM chips with 4 kbits [1]—[3]. One of the most widely
`used variants is shown in Fig. 1 [3]. The bit lines are
`precharged to a reference voltage approximately equal to
`VDD/2, which can be obtained from a voltage regulator as
`suggested by Foss and Harland [3], or by shorting two
`bit—line halves after restoring the signal [1], [2]. After the
`sense latching clock (IDS is activated, the load clock (PL is
`turned on, pulling up the high bit line to fully overdrive the
`cross-coupled latch and also to restore a full signal. After
`the 4 kbit NMOS DRAM generation, a 5 V-only VDD
`power supply was widely adopted. Sensing was converted
`to full-VDD bit—line precharge, sometimes with an active
`restore circuit, such as shown in Fig. 2 [4] or in Fig. 5 of
`[5], to obtain sufficient overdrive on the NMOS latch for
`higher speed and to restore the full signal. Half-VDD bit—line
`sensing lost its importance in NMOS DRAM’s because of
`the following disadvantages:
`1)
`there is less overdrive on the NMOS latch,
`degrading the latching speed: and
`'
`
`thus
`
`Manuscript received October 17, 1983; revised December 22, 1983.
`The authors are with IBM T. J. Watson Research Center, Yorktown
`Heights, NY 10598.
`
`FROM X 2
`DECODER
`
`CELL AND
`NODE 2
`NODE 1
`
`Fig. 1.
`
`Schematic of the NMOS half- Vm, bit—line sensing circuitry with
`associated timing signals [3].
`
`2) for static pull-up loads [4], dc power is consumed on
`the low bit—line side. For an active restore circuit [5]. the
`timing control is sensitive. Without pull-up circuits, only
`partial signal is restored and both sensing speed and sensi-
`tivity are degraded because of voltage droop at two sensing
`nodes, due to latch-device gate-capacitance coupling as
`latching speed is fast (Fig. 3).
`Recently, CMOS is beginning to be used in DRAM
`designs. Advantages include decreasing the radiation-in-
`duced soft errors and isolating cells from substrate noise by
`putting the array in a well, reducing the number of clock
`generators in peripheral circuits, and obtaining lower
`standby power
`[6],
`[7]. For grounded-substrate n-well
`CMOS technology, an NMOS array may be difficult to use
`because minority carrier
`injection due
`to localized
`forward-biasing of junctions will cause destruction of stored
`
`0018-9200/84/0800-O451$01.00 ©1984 IEEE
`
`Page 1 of 4
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`SAMSUNG EXHIBIT 1008
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`121313 JOURNAL or SOLID-STATE CIRCUITS, VOL, sc-19, No. 4. AUGUST 1984
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`Schematic of the NMOS Vm, bit-line sensing circuitry with
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`Schematic of the CMOS ha1f—Vm, bit-line sensing circuitry. CD1
`Fig. 4.
`and ('02 clocks are used for multiplexing bit lines, <l>3 clock controls the
`equalization device and <D4 clock is used to es ab ish he reference
`voltage.
`(D5 and <13“, are complementary clocks to control the sense-
`amplifier latching 11),, is the column-selection clock.
`
`complementary sense amplifier consisting of NMOS and
`PMOS cross—coupled pairs, 2) clocked pulldown of the
`latching node, 3) complementary clocking of the PMOS
`pullup. 4) full-sized dummy cell generation of reference
`potential for sensing, 5) shorting transistor to equalize
`precharge potential of bit lines, and 6) depletion NMOS
`decouphng transistors for multiplexing bit lines (4 and 6
`are not mandatory).
`The operation of the circuit is described by the simulated
`waveforms in Fig. 5. At the end of the previous active
`cycle, one bit-line half is at I/DD and the other is at O V. A
`precharge of the bit line before sensing is initiated by
`switching on <I>3
`to turn on the equalization device Q EQ,
`which shorts two bit-line halves together. The charge shar-
`ing between two bit—line halves results in a precharge level
`at nearly half VDD. The reference voltage established on a
`full-size dummy cell is obtained by activating (134
`to turn
`on Q DS for charge sharing between two dummy cells ( QD1
`
`‘Time for a differential signal of 0.3 V to be amplified to 2.5 V across
`two bit-line halves.
`Z High-performance design,
`
`information in the array [8].1 If a PMOS array in the well is
`used, full—VDD bit-line precharge is not desirable because it
`gives large junction capacitance and high sensitivity of the
`junction capacitance to voltage variation, which can in-
`crease sense—arnplifier mismatch and any word—line noise
`can easily cause stored charge leakage. For grounded bit-
`line precharge, a PMOS cross—coupled latch must be used,
`which has slower sensing speed even when used with an
`NMOS restore circuit (Fig. 3). This is because the PMOS
`device has lower mobility and higher threshold voltage,
`since it is also used as cell transfer device? In comparison,
`half-VDD bit-line sensing gives almost the same speed for
`the latching operation, as shown in Fig. 3. Although the
`NMOS cross—coupled latch with PMOS restore circuit using
`VDD precharge is fastest, the NMOS array may be difficult
`to use for grounded—substrate n—well CMOS technology.
`
`11. CMOS HALF-I/DD BIT-LINE SENSING
`CIRCUITRY
`
`The proposed CMOS sense-amplifier circuitry for the
`half—VDD sensing scheme using a PMOS memory array is
`shown in Fig. 4. It incorporates the following features; 1) a
`
`1Applying a substrate bias in n~well CMOS has the advantages of
`relaxing the constraints of junction forward—bias1ng and latchup, decreas-
`ing the junction capacitances, and reducing the substrate sensitivity of the
`threshold voltage, thus allowing high—performa.nce peripheral circuits. If
`the system solution to the soft error problem is acceptable to the memory
`applications [9]. use of an NMOS array may be considered due to some
`superior device characteristics.
`3Unlcss an extra mask plus ion-implantation is used to generate a
`second PMOS threshold voltage.
`
`Page 2 of 4
`
`

`
`LU AND CHAOZ HALF VDD BIT-LINE SENSING SCHEMIE
`
`4.53
`
`
`
`VOLTAGE(V)
`
`TIME (nsec)
`
`Fig. 5. Simulated waveforms for the CMOS half- VDD sensing circuitry.
`Refer to Fig. 4 for node numbers.
`
`and QD2 ), one having a stored high and the other a stored
`low level. READ can be performed by selecting a word line
`and the corresponding dummy word line (DWL1), which
`establishes a differential signal on the two sensing nodes (4
`and 5) of the flip-flop pair. The worst-case charge transfer
`is to read the stored low level or 0 V, which starts after the
`word line is pulled down to (VDD /2)— ]VTP|, where V7,, is
`the PMOS threshold voltage. The stored charge is fully
`transferred to the bit line without threshold loss even if the
`
`word line is not boosted. The word-line boosting -can be
`used subsequently for restoring the full signal (0 V) into
`the cell and does not delay the read access time.
`To amplify the signal, the NMOS cross-coupled pair (Q1
`and Q2) and the PMOS cross-coupled pair (Q3 and Q4)
`are switched on by (PS and its complementary signal <I>w,
`respectively. The NMOS latch gives fast initial sensing.
`The PMOS cross-coupled pair pulls up the high bit-line-half
`to give full overdrive on the latch and full signal for
`restoring. The PMOS cross-coupled pair also pulls up the
`voltage droop at the high sensing node (5 in Fig. 5) due to
`the gate capacitance of the NMOS cross-coupled transis-
`tors, which can seriously degrade the sensitivity of the
`sense amplifier, especially for high performance. To activate
`’ a PMOS cross-coupled latch in the grounded bit-line sens-
`ing scheme,
`the latching node charges from 0 to 5 V;
`however, the half- VDD sensing is activated by discharging
`the latching node only from VDD/2 to 0 V, thus reducing
`the voltage droop at the two sensing nodes. Since half- VDD
`is close to the switching point of both the NMOS and
`PMOS cross-coupled pairs, the active pullup of the droop-
`ing voltages at two sensing nodes by the PMOS cross-cou-
`pled pair is more effective. As a result, the sensitivity of the
`sense amplifier is also improved (Fig. 3).
`,
`
`III.
`
`FEATURES or HALF—VDD B1T—Line Sensing
`
`As mentioned earlier, the half- VDD bit-line sensing gives
`almost the same latching speed as grounded bit-line sens-
`ing, as shown in Fig. 3, because NMOS devices are used in
`the sensing latch and the PMOS cross-coupled pair can
`effectively avoid the voltage droop on the two sensing
`
`for
`nodes and also supplies sufficient overdrive. Also,
`half-VDD bit-line sensing, the stored charge can be fully
`transferred onto the bit lines during the read cycle without
`boosting the word line. If a boosted word line is used to
`store a full—level charge into the cell, the boosted level is
`needed only during the restore period,
`thus causing no
`extra delay during ‘read access due to boosting. This makes
`the word line boosting attractive using the half—VDD sens-
`ing scheme. By comparing the speed of a complete charge
`transfer from the memory cell to the bit lines, the half- VDD
`sensing scheme has a much faster rate than the grounded
`bit-line sensing scheme because the complete transfer can
`start when the word line is pulled down to one |VT,,| below
`VDD/2 rather than being boosted down below 0 V in the
`grounded bit-line sensing scheme. As a result, the elapsed
`time from word-line activation to turning on the bit switch
`is faster in the half-VDD bit-line sensing scheme.
`In addition, the NMOS cross-coupled pair and the PMOS
`cross-coupled pair form a complementary pair, which does
`not have dc power dissipation and can be clocked simply.
`In CMOS DRAM’s, therefore, half-VDD bit-line sensing
`, has none of the disadvantages which it has when used in
`NMOS DRAM’s and also shows advantages in comparison
`to the grounded bit-line sensing scheme. It has other addi-
`tional advantages, which are very important for high-den-
`sity high-performance DRAM design:
`1) Reduces the peak currents at both sensing and bit-line
`precharge by almost a factor of two due to the half—VDD
`swing, which reduces the electromigration problem and the
`IR drop. The chip reliability can _be increased and the
`resulting narrower metal lines decrease the parasitic wiring
`capacitances thus giving better speed.
`I
`2) Reduces the d1/dt by a factor of two during bit-line
`precharge and discharge if the time is fixed, which de-
`creases the voltage bouncing noise. due to wiring induc-
`tance. If the voltage bouncing is not the limit, the pre-
`charge and discharge time can be shortened by a factor of
`two.
`
`3) Reduces the ac power for charging and discharging
`the bit lines because the precharge voltage is obtained by
`charge sharing between the two bit-line halves instead of
`charging bit lines to VDD.
`4) Atlsensing and bit-line precharge in half-VDD sensing,
`the pullup and pulldown of bit lines are balanced and have
`only half—VDD swing. By using folded bit lines, coupled
`noises due to bit-line swing to the memory cell plate, the
`array substrate, and word lines can be largely reduced due
`to local cancellation. This also relaxes the requirement of
`using a low-impedance cell plate. Even if the plate has
`voltage bumping (for example, write at high plate voltage
`and read at low plate voltage), therewill be no significant
`signal loss- because the cell transfer device is operated in
`the linear
`region in half-VDD sensing.
`In contrast,
`in
`grounded bit-line sensing, only one of the two segments of
`bit lines is pulled up (at sensing) or down (at precharge) by
`full- VDD, which gives much larger coupling noises. The
`signal loss due to plate voltage bumping’ is also larger
`because the cell transfer device is operated in the satura-
`tion region.
`
`Page 3 of 4
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`

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`454
`
`IEEE JOURNAL or soLID-STATE CIRCUITS, VOL. sc—19, No. 4, AUGUST 1984
`
`The only drawback may be a longer period of bit-liI1e
`floating such that
`the bit-line precharge levels can be
`perturbed to cause mismatch due to radiation noise, sub-
`strate noise, and leakage effects. However, studies show
`that this is tolerable by using the following design ap-
`proach, some of which is unique to CMOS technology:
`1) Use folded metal bit
`lines to minimize the noise
`mismatch between two halves and also to minimize the
`
`junction area which reduces the leakage, substrate noise,
`and radiation noise.
`
`2) Use a PMOS array in an n-well such that the p ' —»n
`junctions are protected by the n-well. This reduces the
`leakage current, the substrate noise, and radiation-induced
`soft error rates.
`
`3) Keep the bit-line equalization device on until just
`before the word-line activation. Differential noises occur-
`
`ring on a bit-line half during precharge will be distributed
`over
`the two halves in a common mode to minimize
`mismatch. The noise distribution is fast because the metal
`
`bit line gives very small resistance. For example, if a PMOS
`equalization device has W/L=4 ptm/1.2 ,um and each
`bit-line half has 200 fF, a 500 nA 10 ns square-pulse noise
`gives less than 3 mV mismatch noise which decays with a
`time constant of 2 ns.
`
`4) Use a dummy cell to generate the reference potential
`so that the absolute bit-line precharge level and the word-
`line to bit-line coupling noise causing sensing signal mis-
`match are not crucial at least to first—order.
`
`5) Use distributed refresh to shorten the time of bit-line
`floating at chip standby.
`
`VI. CONCLUSION
`
`The use of a half— I/DD bit-line sensing scheme in CMOS
`DRAM’s has been described. It shows several advantages
`over the grounded bit-line sensing schemes used in existing
`CMOS DRAM’s. The half-VDD sensing has not been em-
`ployed in NMOS DR:AM’s with chip density larger than 16
`kbits; however,
`in CMOS DRAM’s,
`the following ad-
`vantages have been demonstrated:
`1) Comparable sensing speed with better sensitivity of
`sense amplifier.
`2) Complete charge transfer can be read from the cell
`without word-line boosting provided that |VT,.| is less than
`VDD/2 minus the sensing signal which depends on the
`charge transfer ratio.
`3) Faster when compared to the word-line boosting _
`scheme to read full signal.
`4) Delayed word-line boost for full-signal restoring gives
`no penalty on read speed.
`5) Smaller peak currents at both sensing and bit-line
`precharge.
`6) Smaller ac power consumption for bit-line charge and
`discharge.
`7) Smaller d1/dt,
`wiring inductance.
`8) Smaller coupling noises to the cell plate, the array
`substrate, and word lines because of balanced bit-liIIe
`swing.
`9) Less signal loss due to cell-plate voltage bumping.
`
`thus smaller bouncing noise due to
`
`ACKNOWLEDGMENT
`
`The authors wish to thank Drs. L. M. Terman and H. N.
`
`Yu for many helpful discussions and support of this study.
`
`REFERENCES
`
`, K. U. Stein, A Sflilin , and E. Doering, “Storage array and sense/re-
`fresh circuits for sing e-transistor memory cells,” IEEE J. Solid-State
`Circuits, vol. SC—7, pp. 336-340, Oct. 1972.
`K. U. Stein and H. Friedrich, “A 1 mill single-transistor memorv
`cell in II silicon-gate tecllnology,” IEEE J. Solid-State Circuits, vol.
`SC—8, pp. 319-323, Oct. 1973.
`R. C. Foss and R. Harland, “Peripheral circuits for one-transistor
`cell MOS RAM’s,” IEEE J. Solid-State Circuits, Vol. SC-10, pp.
`255—26l, Oct. 1975.
`C. N. Ahlquist, J. R. Breivogel, J. T. Koo, J. L. McCollum, and
`W. G. Oldham, “A 16384—bit dynamic RAM,” IEEE J. Solid—State
`Circuits, vol. SC—11, pp. 570—574, Oct. 1976.
`S. S. Eaton, “A 5 V-only 2K><8 dynamic RAM,” in Proc. IEEE
`ISSCC, 1979, p. 144—145.
`K. Shimohigas ', H. Masuda, Y. Kamigalci, K. Itoh, N. Hashimoto,
`and E. Arai, “An n-well CMOS dynamic RAM,” IEEE J. Solid—Szate
`Circuits, Vol. SC—17, pp. 344-348, Apr. 1982.
`R. Chwang, M. Choi, D. Creek, S. Stern, P. Pelley, J. Schutz, M.
`Bohr, P. Warkentin, and K. Yu, “A 70 ns high density CMOS
`DRAM,” in Proc. IEEE ISSCC, 1983, pp. 56-57.
`H. Masuda et al., “A 5 V—only 64K dynamic RAM based on high
`S/N design,” IEEE J. S0/id—Srate Circuits, Vol. SC-15, pp. 846~854,
`Oct. 1980.
`y
`D. C. Bossen and M. Y. Hsiao, “A system solution to the memory
`soft error problem,” IBM J. Res. DeveIop., vol. 24, no. 3, pp.
`390-397, 1980.
`
`Nicky Chau-Chun Lu (M’82) received the B.S.E.E.
`from National Taiwan University, Taipei, Re-
`public of China, in 1975, and M.S. and Ph.D.
`degrees in electrical engineering from Stanford
`University, Stanford, CA, in 1978 and 1981, re-
`spectively.
`From 1975 to 1977, he served ROTC service in
`the Chinese Air Force. From 1977 to 1981, he
`was a Stanford Fellow and then Research Assis-
`tant at
`the Integrated Circuits Laboratory at
`Stanford University. He was Visiting Associate
`Professor at the Institute of Electronics, National Chiao-Tung University,
`and Lecturer at Electronic Research and Service Organization, ITRI,
`Taiwan, ROC, from 1981 to 1982. He is now a Research Staff Member at
`IBM Thomas J. Watson Research Center, Yorktown Heights, NY. His
`current technical interests focus on the design of high—performance VLSI
`MOS memory chips, exploratory silicon devices and technology, and
`physics of polysilicon devices. In these areas, he has published 24 papers
`and filed 21 invention disclosures for patent applications.
`Dr. Lu is a member of Sigma Xi and Phi Tau Phi.
`
`Hu H. Chao (M’81) was born in the Republic of
`China on June 12, 1947. He received the BS.
`degree in electrical engineering from National
`Taiwan University in 1968,
`the M.E. degree in
`electrical engineering from Syracuse University,
`Syracuse, NY, in 1970, the Ph.D. degree in elec-
`trical engineering from Princeton University,
`Princeton, NJ, in 1978.
`In 1976, he joined Texas Instruments Inc. and
`was involved in the research and development of
`charged-coupled devices. III 1978 he joined the
`IBM T. J. Watson Research Center, Yorktown Heights, NY, and has been
`engaged in the research and development of MOS devices.
`
`Page 4 of 4