Ulllted States Patent
`
`
`Sukegawa
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`[19]
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`[11] Patent Number:
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`[45] Date of Patent:
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`5,828,241
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`Oct. 27, 1998
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`US005828241A
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`
`[54]
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`SIGNAL TRANSMISSION CIRCUIT
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`PROVIDING AMPLIFIED OUTPUT FROM
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`POSITIVE FEEDBACK or INTERMEDIATE
`AMPLIFIER CIRCUIT
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`
`
`Inventen Snnnnln Snkeenwn» Onnne» Jnnnn
`[751
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`1731 Assrgnee: Texas Instruments Incorporated,
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`Da11as>TeX~
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`[21] APPI. No; 553,755
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`F1 d:
`. 5 1996
`22
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`1 6
`Jun ’
`[
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`Related U_S_ Application Data
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`i
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`[63] Continuationofser. No. 393,525, Feb. 23, 1995, abandoned,
`which is a continuation of Ser. No. 979,085, Nov. 19, 1992,
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`d.
`b
`d
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`a an one
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`Foreign Application Priority Data
`
`[30]
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`Japan .................................... 3—334121
`[JP]
`Jan. 22, 1991
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`Int. Cl.6 ..................................................... .. H03K 5/22
`[51]
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`[52] U.S. Cl.
`............................... .. 327/67; 327/55; 327/57;
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`327/208; 327/391
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`[58] Field of Search ................................... .. 307/530, 279,
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`307/572, 443; 365/203, 205; 327/51, 54,
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`55’ 57’ 65’ 67’ 206’ 208’ 379’ 389’ 391;
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`326/21, 23, 24
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`[56]
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`References Cited
`U.S. PATENT DOCUMENTS
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`
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`4,716,320 12/1987 McAdams ............................. .. 307/530
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`2
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`3
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`3; 1;”
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`******** “
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`LINE
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`1
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`LINE_
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`101
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`Page 1 of 14
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`SAMSUNG EXHIBIT 1005
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`
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`
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`4,939,691
`
`
`4,943,944
`,
`,
`5,010,523
`
`
`§:§’§§:§Zi
`
`
`2:133:33?
`
`5,227,697
`
`5,231,318
`
`5,307,317
`
`
`.............. .. 365/189.01
`7/1990 Mizukami et al.
`
`
`
`
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`
`
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`365/189.05
`7/1990 Sahui et al.
`
`<T3ht1)ntete1~ ~~
`. . . ..
`0 1 a . . . . . . . . .
`4/1991 Yamauchi
`............................. .. 365/205
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`11/133: 315255157'...::::""""'"""""::::: 383/338
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`Z1333 E‘:‘&‘;?2;§2fZ1.
`..
`::::: §2§§§3§’
`
`
`
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`7/1993 Sakagami . . . . . . . .
`. . . .. 365/203
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`.. 307/530
`7/1993 Reddy
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`4/1994 Shiraishi eta. ...................... .. 307/530
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`Primary Examiner—Terry Cunningham
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`Attorney, Agent, or FLrm—W1ll1am B. Kernpler; Richard L.
`Donaldson
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`ABSTRACT
`[57]
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`A signal transmission circuit which enables the distance of
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`signal transmission as measured by the length of the wiring
`electrically connecting a driver circuit and a receiver circuit
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`of the Signal transmission Circuit to be increased’ While the
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`signal delay and power consumption are reduced. The signal
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`transmission Circuit includes the driVer Circuit, the reCeiVer
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`circuit, an equalizer circuit that flattens the output of the
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`driver eireiiiis arid ari
`iriierrriediaie arripiirier eireiiii~ The
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`intermediate amplifier circuit is connected to input/output
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`shared terminals in the Wiring that connects the driver circuit
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`and the receiver circuit. With the aid of the positive feedback
`of the intermediate amplifier circuit, a differential signal
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`output from the driver circuit is amplified and then trans-
`mitted to the receiver circuit.
`
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`4 Claims, 7 Drawing Sheets
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`IN AMP
`
`IN AMP
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`1 I
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`N AMP
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`if 71 fin
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`Page 1 of 14
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`SAMSUNG EXHIBIT 1005
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`

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`U.S. Patent
`
`Oct. 27, 1998
`
`Sheet 1 of 7
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`5,828,241
`
`owm_
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` _2I1:23:::::\I.
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`5_on
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`K.0?»
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`Page 2 of 14
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`Page 2 of 14
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`
`

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`U.S. Patent
`
`Oct. 27, 1998
`
`Sheet 2 of 7
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`5,828,241
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`Page 3 of 14
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`Page 3 of 14
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`

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`U.S. Patent
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`5,828,241
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`
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`%%8§8£§w¢
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`Page 4 of 14
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`Page 4 of 14
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`

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`Oct. 27, 1998
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`Sheet 4 of 7
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`5,828,241
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`Page 5 of 14
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`

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`U.S. Patent
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`Oct. 27, 1998
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`Sheet 5 of 7
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`5,828,241
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`
`
`our
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`51
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`OUT
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`51
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`our
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`51
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`OUT
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`51
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`290
`m p. _____ __‘.‘. ____ __ >.
`
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`53
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`50
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`52
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`FIG’. 70
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`200
`IN >- ———3—4z>—————— be
`
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`54
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`53
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`50
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`52
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`FIG.
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`77
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`200
`__“.__R)__.R,____ >.
`
`52
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`55
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`56
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`53
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`FIG. 72
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`[N p.
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`
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`50
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`IN
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`50
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`ZQO
`-42*-+20-+2<>“*
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`57
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`58
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`59
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`FIG. 13
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`Page 6 of 14
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`Page 6 of 14
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`

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`U.S. Patent
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`Oct. 27, 1998
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`Sheet 6 of 7
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`5,828,241
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`Page 7 of 14
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`Page 7 of 14
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`

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`U.S. Patent
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`Oct. 27, 1998
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`Sheet 7 of 7
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`5,828,241
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`r I I I II I I I II III I II I II II I IIL
`
`________________
`
`FIG. 17
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`Page 8 of 14
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`Page 8 of 14
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`

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`5,828,241
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`1
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`SIGNAL TRANSMISSION CIRCUIT
`
`
`
`PROVIDING AMPLIFIED OUTPUT FROM
`
`
`
`
`POSITIVE FEEDBACK OF INTERMEDIATE
`
`
`
`AMPLIFIER CIRCUIT
`
`
`
`This application is a continuation of application Ser. No.
`
`
`
`
`
`
`08/393,525 filed Feb. 23, 1995, now abandoned, which was
`
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`a continuation of application Ser. No. 07/979,085 filed Nov.
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`19, 1992, now abandoned.
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`This invention concerns a type of signal transmission
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`circuit. More specifically, this invention concerns a type of
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`signal transmission circuit wherein the signal is amplified
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`and transmitted by means of the positive feedback of an
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`intermediate amplifier circuit having input/output shared
`terminals.
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`BACKGROUND OF THE INVENTION
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`10
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`15
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`Heretofore, TTL logic used to be the main type of
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`general-purpose logic. However, in the recent years, CMOS
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`logic has replaced the TTL logic as the main type.
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`The types of CMOS logic include standard CMOS logic
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`(with a chip size about 20 mm and a transmission delay time
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`about 80 nsec), high-speed CMOS logic (with the same chip
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`size as above, and a transmission delay time about 15 nsec),
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`new high-speed CMOS logic (with the same chip size and a
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`transmission delay time about 8 nsec), and advanced high-
`speed CMOS logic (with the same chip size and a transmis-
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`sion delay time about 4 nsec).
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`In a conventional LSI chip, such as a CMOS circuit
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`providing a signal transmission circuit, inverters may be
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`used as a driver circuit and a receiver circuit.
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`FIGS. 10-13 show some examples of a conventional
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`signal transmission circuit.
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`In the circuit shown in FIG. 10, driver circuit 50 using
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`inverter 52 and receiver circuit 51 using inverter 53 are
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`connected to each other by wiring 200, and the signal is
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`transmitted from driver circuit 50 to receiver circuit 51 by
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`wiring 200, so that the so-called rounding of the signal can
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`be reduced.
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`In the circuits shown in FIGS. 11-13, in the case when the
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`signal transmission time becomes longer as the signal trans-
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`mission distance is increased so that the time constant RC
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`due to parasitic resistance and capacitance of wiring 200,
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`corresponding to the delay in the signal transmission time,
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`inverter 54 (FIG. 11), inverters 55, 56 (FIG. 12), or inverters
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`57-59 (FIG. 13) are connected in series between driver
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`circuit 50 and receiver circuit 51 to improve the delay of the
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`signal transmission time. These inverters 54-59 act as an
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`intermediate amplifier circuit, respectively.
`FIG. 14 shows a diagram of characteristics illustrating the
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`relationship between the power consumption of the conven-
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`tional signal
`transmission circuit and the wiring length
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`shown in FIGS. 10-13.
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`In this figure, curve OC in the case when no inverter is
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`used as the intermediate amplifier circuit (the graph which
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`shows the characteristics of the signal transmission circuit in
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`FIG. 10) indicates that the power consumption is about 1.05
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`mW for a wiring length of 20><1000 pm (2 cm) in an LSI
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`chip. In this case, the signal cycle time is 60 nsec, the wiring
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`capacitance is 0.25 FF/1 ym, and there is a wiring resistance
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`of 0.1 S2/square.
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`Curve 2C in the case when inverter 54 is used as the
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`intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 11)
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`indicates that the power consumption is about 1.1 mW for a
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`20
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`25
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`Page 9 of 14
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`wiring length of 20><1000 ym. Curve 3C in the case when
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`inverters 55, 56 are used as the intermediate amplifier circuit
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`(the graph illustrating the characteristics of the signal trans-
`mission circuit of FIG. 12) indicates that the power con-
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`sumption is about 1.15 mW for a wiring length of 20><1000
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`ym. Curve 4C in the case when inverters 57-59 are used as
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`the intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 13)
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`indicates that the power consumption is about 1.2 mW for a
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`wiring length of 20><1000 ym.
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`That is, in the conventional signal transmission circuit,
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`when the wiring length is kept constant such as 2 cm, as
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`more inverters 54-59 are connected in series as intermediate
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`amplifiers interposed in the wiring 200 (FIGS. 10-13), the
`power consumption of the signal
`transmission circuit
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`increases. When the signal transmission circuit without an
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`inverter used as an intermediate amplifier as shown in FIG.
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`10 is compared with the signal transmission circuit shown in
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`FIG. 13 with three inverters that are used as intermediate
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`amplifiers, it can be seen that while the power consumption
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`of the signal transmission circuit in FIG. 10 is 1.05 mW, for
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`the signal transmission circuit shown in FIG. 13, the power
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`consumption is increased to 1.2 mW.
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`FIG. 15 shows the relationship between the wiring length
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`and the delay in signal transmission. FIGS. 10-13 show the
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`simulation results
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`In FIG. 15, the ordinate represents the delay, while the
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`abscissa represents the wiring length.
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`For example, when the wiring length within LSI chip is
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`20><1000 gm (2 cm), curve OC in the case when no inverter
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`is used as the intermediate amplifier circuit (the graph which
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`shows the characteristics of the signal transmission circuit in
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`FIG. 10) indicates a delay of about 5.5 nsec; curve 2C in the
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`case when inverter 54 is used as the intermediate amplifier
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`circuit (the graph illustrating the characteristics of the signal
`transmission circuit of FIG. 11) indicates a delay of about 5
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`nsec; curve 3C in the case when inverters 55, 56 are used as
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`the intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 12)
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`and curve 4C in the case when inverters 57-59 are used as
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`the intermediate amplifier circuit (the graph illustrating the
`characteristics of the signal transmission circuit of FIG. 13)
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`indicate a delay of about 4.5 nsec.
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`That is, in the conventional signal transmission circuit,
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`when the wiring length is kept constant at 2 cm, as more
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`inverters 54-59 are connected in series as intermediate
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`amplifiers interposed in the wiring 200 (FIGS. 10-13), the
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`delay time becomes shorter. When the signal transmission
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`circuit without an inverter used as an intermediate amplifier
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`as shown in FIG. 10 is compared with the signal transmis-
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`sion circuit shown in FIG. 13 with three inverters that are
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`used as intermediate amplifiers, it can be seen that while the
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`delay of the signal transmission circuit in FIG. 10 is about
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`5.5 nsec, for the signal transmission circuit shown in FIG.
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`13, the delay is shortened to 4.5 nsec.
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`As pointed out hereinbefore, in the aforementioned con-
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`ventional example, when a number of inverters are con-
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`nected as intermediate amplifiers so as to reduce the delay of
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`the signal transmission, the power consumption is increased.
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`This is a problem of contradiction. In addition, when the
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`number of the inverters used as intermediate amplifiers is
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`small, the power consumption is still high. Besides, when
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`the number of the inverters used as intermediate amplifiers
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`is increased, there is a limitation on the improvement of the
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`delay of the signal transmission.
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`FIGS. 16 and 17 show specific circuit examples of other
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`conventional signal
`transmission circuits designed for
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`Page 9 of 14
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`5,828,241
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`3
`improving the aforementioned problems of a signal trans-
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`mission circuit using inverter circuits.
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`In the signal transmission circuit shown in FIG. 16, driver
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`circuit 60 and receiver circuit 61 are connected by a pre-
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`charge circuit 62.
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`Driver circuit 60 comprises CMOS inverters 63, 64,
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`driving p-type MOS transistors 65, 67, and driving n-type
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`MOS transistors 66, 68.
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`Input terminal IN is connected to the input of inverter 63
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`and the gate of nMOS transistor 68; the output of inverter 63
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`is connected to the gate of pMOS transistor 65. The voltage
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`applied on input terminal IN is applied as the gate voltage on
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`the gate of pMOS transistor 65 and the gate of nMOS
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`transistor 68, respectively.
`The inverted input terminal N-IN is connected to the input
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`of inverter 64 and the gate of nMOS transistor 66, and the
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`output of inverter 64 is connected to the gate of pMOS
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`transistor 67. The voltage applied on inverted input terminal
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`N-IN is then applied as the gate voltage on the gate of pMOS
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`transistor 67 and the gate of nMOS transistor 66 as the gate
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`voltage.
`The drain of nMOS transistor 66 is connected to the drain
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`of pMOS transistor 65 to form a first transistor pair, while
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`the drain of nMOS transistor 68 is connected to the drain of
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`pMOS transistor 67 to form a second transistor pair.
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`On the other hand, receiver circuit 61 comprises nMOS
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`transistors 71, 72, pMOS transistors 73-76, and CMOS
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`inverters 77 and 78; nMOS transistors 71, 72 and pMOS
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`transistors 73-76 are cross—coupled to each other.
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`The source of nMOS transistor 72 and the gate of pMOS
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`transistor 74 are connected to the input side of CMOS
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`inverter 77; the source of nMOS transistor 71 and the gate
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`of pMOS transistor 75 are connected to the input side of
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`CMOS inverter 78.
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`The precharge circuit 62 comprises nMOS transistors 69,
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`70. The source of nMOS transistor 69 is connected to the
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`drain of nMOS transistor 65 of the driver circuit 60 and the
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`drain of nMOS transistor 71 of the receiver circuit 61; the
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`source of nMOS transistor 70 is connected to the drain of
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`pMOS transistor 67 and the drain of nMOS transistor 72.
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`The gate of nMOS transistor 69 is connected to the gate
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`and equalizer terminal EQ of nMOS transistor 70; the drain
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`of nMOS transistor 69 is connected to the drain and VDD/2
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`terminal of nMOS transistor 70.
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`is used in the signal
`This signal
`transmission circuit
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`circuit with a large wiring length of several cm, such as the
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`address circuit, etc., in the LSI chip. As VDD/2 precharger
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`functions, the signal is sent from the driver circuit 60 to
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`receiver circuit 61 by precharge circuit 62; by means of the
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`nMOS transistors 71, 72 of receiver circuit 61, the differ-
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`ential signal of the circuit threshold voltage VTh is derived.
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`This differential signal
`is then converted to the CMOS
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`voltage level by means of CMOS inverters 77, 78.
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`In this way, improvement can be realized with respect to
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`the signal transmission delay, and the power consumption
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`can be reduced.
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`FIG. 17 shows the circuit diagram of the intermediate
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`amplifier circuit connected between the driver circuit and
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`receiver circuit of the signal transmission circuit shown in
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`FIG. 16.
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`In this intermediate amplifier circuit, the aforementioned
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`differential signal is amplified by converting the differential
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`signal to the CMOS signal, followed by reconverting the
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`CMOS signal to the differential signal. The conversion is
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`accomplished by a receiver circuit 79 which converts the
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`Page10of14
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`4
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`differential signal of the input signal to a CMOS signal and
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`a driver circuit 80 which converts the CMOS signal to the
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`differential signal.
`Receiver circuit 79 comprises input terminal IN, inverted
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`input terminal N-IN, nMOS transistors 81, 82 for converting
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`the differential signal to the CMOS signal, pMOS transistors
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`83-86, and CMOS inverters 87, 88 for amplifying the
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`CMOS signal.
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`The nMOS transistor 81 and rLMOS transistor 82 are
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`connected to each other with their gates and drains con-
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`nected in a crossed form; the pMOS transistor 84 and pMOS
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`transistor 85 are connected to each other with their gates and
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`sources connected in a crossed form.
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`CMOS inverters 87, 88 are connected to the gates of
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`pMOS transistors 84, 85, respectively.
`Driver circuit 80 comprises CMOS inverters 89, 90,
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`pMOS transistors 91, 93 for converting the CMOS signal to
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`the differential signal, nMOS transistors 92, 94, output
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`terminal OUT and inverted output terminal N-OUT.
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`The outputs of CMOS inverters 89, 90 are connected to
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`the gates of pMOS transistors 91, 93, the inputs of CMOS
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`inverters 89, 90 are connected to the gate of nMOS transistor
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`94 and the gate of nMOS transistor 92.
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`However, as shown in FIGS. 10-13, for the conventional
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`signal transmission circuit made of CMOS inverter circuits
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`connected in series, as the chip size is increased, and the
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`parasitic capacitance and parasitic resistance are increased,
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`delay of the signal transmission time and increase in the
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`power consumption cannot be ignored anymore.
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`As a replacement of the aforementioned signal transmis-
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`sion circuit, the signal transmission circuit shown in FIG. 16
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`has been proposed. Compared with the CMOS inverter
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`circuit, the performance of this signal transmission circuit is
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`improved, with the speed increased by about 10%, and
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`power consumption decreased by about 30-40%.
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`However, in the signal transmission circuit shown in FIG.
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`16, for example, when the signal
`transmission distance
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`within the LSI chip becomes longer than about 20 mm, it is
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`impossible to make a simple serial connection of several
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`intermediate amplifiers as in the signal transmission circuit
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`shown in FIGS. 10-13. This is a disadvantage.
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`For the intermediate amplifier circuit for combining the
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`driver circuit and the receiver circuit as shown in FIG. 17,
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`as the differential signal has to be converted to a CMOS
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`signal on the input side, while the CMOS signal has to be
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`converted to a differential signal on the output side, the
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`speed characteristic is naturally poorer than that of the
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`conventional signal transmission circuit made of CMOS
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`inverter circuits (FIGS. 11-13). This is a problem.
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`The purpose of this invention is to provide a type of signal
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`transmission circuit wherein the signal transmission distance
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`can be increased, and the signals can be transmitted at a high
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`speed and with low power consumption. Another purpose of
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`this invention is to provide a type of signal transmission
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`circuit in which the signal is transmitted while being ampli-
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`fied by the positive feedback of an intermediate amplifier
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`circuit having input/output shared terminals.
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`SUMMARY OF THE INVENTION
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`transmission circuit
`This invention provides a signal
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`having a driver circuit, a receiver circuit, an equalizer circuit
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`for flattening the output of the aforementioned driver circuit,
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`and an intermediate amplifier circuit,
`the intermediate
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`amplifier circuit being connected to input/output shared
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`terminals in the wiring that connects the driver circuit and
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`Page 10 of 14
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`transmission
`In these figures, A represents the signal
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`circuit used in the case when the signal transmission dis-
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`tance is very long, such as when the wiring length is over 2
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`cm. This signal transmission circuit A comprises several
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`intermediate amplifier circuits 1, 1A, 1B with the same
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`circuit configuration, a driver circuit 2, an equalizer circuit
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`3, and a receiver circuit 4.
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`As shown in FIG. 1, in this intermediate amplifier circuit
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`1, positive line LINE which connects connecting terminal 3a
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`of equalizer circuit 3 and input terminal 4a of receiver circuit
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`4 is connected to input/output shared terminal 1a at node
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`101, and inverted line N-LINE (where N- represents the
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`negative side) which connects output terminal 3b of equal-
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`izer circuit 3 and input terminal 4b of receiver circuit 4 is
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`connected to input/output shared terminal 1b at node 102.
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`There are several intermediate amplifier circuits 1. In the
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`configuration shown in FIG. 1, there are three intermediate
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`amplifier circuits 1, 1A, and 1B connected between equal-
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`izer circuit 3 and receiver circuit 4.
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`FIG. 2 is a circuit diagram illustrating the specific con-
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`figuration of the first intermediate amplifier circuit 1.
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`6
`FIG. 17 is a circuit diagram of an intermediate amplifier
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`circuit used in the conventional signal transmission circuit
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`using the differential signal such as shown in FIG. 16.
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`REFERENCE NUMERALS AS EMPLOYED IN
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`THE DRAWINGS
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`1, intermediate amplifier circuit
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`2, driver circuit
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`3, equalizer circuit
`4, receiver circuit
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`5, driving transistor
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`6, driving transistor
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`7, driving transistor
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`8, driving transistor
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`9, precharging transistor
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`10, precharging transistor
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`11, precharging transistor
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`12, precharging transistor
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`13, precharging transistor
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`14, precharging transistor
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`15, precharging transistor
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`16, precharging transistor
`17, transistor
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`18, transistor
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`19, transistor
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`20, transistor
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`21, CMOS inverter
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`22, NAND circuit
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`23, NAND circuit
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`24, CMOS inverter
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`25, CMOS inverter
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`36, CMOS inverter
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`37, CMOS inverter
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`DESCRIPTION OF PREFERRED EMBODIMENT
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`FIG. 1 is a circuit diagram illustrating an embodiment of
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`the signal transmission circuit in accordance with the inven-
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`tion. FIG. 2 is a circuit diagram illustrating an intermediate
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`amplifier circuit as a main portion of the signal transmission
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`circuit in an embodiment of the invention. FIG. 3 shows the
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`waveforms of signals at the various nodes of the interme-
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`diate amplifier circuit in an embodiment of the invention.
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`FIGS. 4-7 are circuit diagrams illustrating connection forms
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`of signal transmission circuits in accordance with the inven-
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`tion.
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`5,828,241
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`10
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`5
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`receiver circuit. With the aid of the positive feedback of the
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`intermediate amplifier circuit,
`the signal from the driver
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`is amplified and then transmitted to the receiver
`circuit
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`circuit.
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`Before the signal transmission, the equalizer circuit flat-
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`tens the signal between the driver circuit and the receiver
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`circuit; the driver circuit converts the input level signal to a
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`differential signal, the intermediate amplifier circuit ampli-
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`fies by positive feedback the differential signal output from
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`the driver circuit and sends the amplified signal
`to the
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`receiver circuit, and the receiver circuit converts the input
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`differential signal to a level signal.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`
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`FIG. 1 is a circuit diagram of a signal transmission circuit
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`provided with an intermediate amplifier circuit
`in an
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`embodiment of the invention.
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`FIG. 2 is a circuit diagram of the intermediate amplifier
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`circuit as the main portion of a signal transmission circuit in
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`an embodiment of the invention.
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`FIG. 3 is a diagram illustrating the signal waveforms at
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`the various nodes of the intermediate amplifier circuit in an
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`embodiment of the invention.
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`FIG. 4 is a circuit diagram illustrating the connecting state
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`of the signal transmission circuit in an embodiment of the
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`invention.
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`FIG. 5 is a circuit diagram illustrating the connecting state
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`of the signal transmission circuit in an embodiment of the
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`invention.
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`FIG. 6 is a circuit diagram illustrating the connecting state
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`of the signal transmission circuit in an embodiment of the
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`invention.
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`FIG. 7 is a circuit diagram illustrating the connecting state
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`of the signal transmission circuit in an embodiment of the
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`invention.
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`FIG. 8 is a graph showing the relation between the wiring
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`length and the power consumption of the signal transmission
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`circuit for the simulation circuit configurations of FIGS.
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`4-7.
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`FIG. 9 is a graph showing the relation between the wiring
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`length and the delay of the signal transmission circuit for the
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`simulation circuit configurations of FIGS. 4-7.
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`FIG. 10 is a circuit diagram illustrating an example of the
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`transmission circuit using conventional CMOS
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`inverters.
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`FIG. 11 is a circuit diagram illustrating an example of the
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`transmission circuit using conventional CMOS
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`inverters.
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`FIG. 12 is a circuit diagram illustrating an example of the
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`transmission circuit using conventional CMOS
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`inverters.
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`FIG. 13 is a circuit diagram illustrating an example of the
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`55
`transmission circuit using conventional CMOS
`signal
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`inverters.
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`FIG. 14 is a graph showing the relationship between the
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`wiring length and power consumption of the signal trans-
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`mission circuit corresponding to the inverter connection
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`configurations of FIGS. 10-13 using the conventional
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`CMOS inverters.
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`FIG. 15 is a graph showing the relationship between the
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`wiring length and delay of the signal transmission circuit
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`corresponding to the inverter connection configurations of
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`FIGS. 10-13 using the conventional CMOS inverters.
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`FIG. 16 is a circuit diagram of a conventional signal
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`transmission circuit using the differential signal.
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`Page 11 of 14
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`intermediate amplifier circuit 1 comprises
`In FIG. 2,
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`input/output shared terminals 1a, 1b, driving pMOS tran-
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`sistors 5, 7, and nMOS transistors 6, 8, precharging pMOS
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`transistors 9-12 and nMOS transistors 13-16, as well as
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`switching nMOS transistors 17, 18 and pMOS transistors 19,
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`20.
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`Connected to input/output shared terminal 1a are the drain
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`of pMOS transistor 5, the drain of nMOS transistor 6, the
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`source of nMOS transistor 18, and the source of pMOS
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`transistor 20.
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`Connected to the gate of pMOS transistor 5 are the drains
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`of pMOS transistors 9, 10, the gate of pMOS transistor 11,
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`and the drain of nMOS transistor 17.
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`Connected to the gate of nMOS transistor 6 are the drain
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`of pMOS transistor 19, the gate of nMOS transistor 15, and
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`the drains of rMOS transistors 13, 14.
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`In addition, the drains of pMOS transistors 11, 12, the gate
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`of pMOS transistor 10 and the drain of nMOS transistor 18
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`are connected to the gate of pMOS transistor 7, and the drain
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`of pMOS transistor 20, the gate of nMOS transistor 14, and
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`the drains of nMOS transistors 15, 16 are connected to the
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`gate of nMOS transistor 8.
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`Besides, the drain of pMOS transistor 7 and the drain of
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`nMOS transistor 8 are connected to output terminal 1b.
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`When intermediate amplifier circuit 1 is in the initial
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`precharge state, pMOS transistors 5, 7 and nMOS transistors
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`6, 8 are all in OFF (nonconductive) state.
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`In this case, the voltage at nodes 101 and 102 becomes the
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