(12) United States Patent
`Podlesny et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,366,130 B1
`Apr. 2, 2002
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`US006366 l 30B]
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`(54)
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`(75)
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`HIGH SPEED LOW POWER DATA
`TRANSFER SCHEME
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`Inventors: Andrew V. Podlesny; Alexander V.
`Malshln; Alexander Y. Solomatnlkov,
`all of Moscow (RU)
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`(73)
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`Assignee: Elbrus International Limited, George
`Town Grand Cayman (KY)
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`(‘)
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`Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`Appl. No.: 09/505,656
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`Filed:
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`Feb. 17, 2000
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`(60)
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`(51)
`(52)
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`(58)
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`(56)
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`Related U.S. Application Data
`Provisional application No. 60/120,531, liled on Feb. 17,
`1999.
`
`Int. Cl.7 ..................... .. H03K 19/0185; G11C 7/06
`U.S. Cl.
`........................... .. 326/95; 326/86; 326/87;
`326790; 327/57; 32755; 327752
`Field of Search ....................... .. 326/21-23, 26-28,
`32630, 86, 87, 90, 93, 95, 98; 327/51-57
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5.894.233 A * M199‘) Yoon ......................... .. 32755
`6,028,455 A "'
`ZIZOOO Yamauchi
`327/52
`().l47_.5l4 A *
`ll.-"2(l()() Shiratake .... ..
`327755
`6,154,064 A * 1112000 Procbsting
`327,55
`0.184.722 Bl
`*
`2;'20()l Hayakawa ................. .. 32755
`
`
`
`OTHER PUBLICATIONS
`
`Article “On the Parallel Evaluation of Polynomials” in IEEE
`Transactions On Computer, vol. C-22, No. 1, Jan. 1973 by
`Kiyoshi Maruyama.
`
`* cited by examiner
`
`Prinzmjv Examirwr—Miehael Tokar
`Aswstant f.'xamr'ner—Vibol Tan
`
`(74) Attorney, Agent, or Firm—Townsend and Townsend
`and Crew LLP
`
`(57)
`
`ABSTRACT
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`A data transfer arrangement. The data transfer arrangement
`includes two active pull up/active pull down bus drivers and
`a voltage precharge source. A diflerential bus is coupled to
`the bus drivers and to the voltage preeharge source. A
`latching sense amplifier is coupled to the differential bus and
`serves as the bus receiver. The bus drivers operate in a
`precharge phase and a data transfer phase. The bus receiver
`operates in an analogous but opposite manner, i.e., when the
`bus drivers are in the precharge phase, the bus receiver is in
`the data transfer phase and when the bus drivers are in the
`data transfer phase, the bus receiver is in a preeharge phase.
`
`5.598371 A *
`5,781,028 A *
`
`365/189.05
`l,-"1997 Lee etal.
`771998 Decuir
`...................... .. 326330
`
`8 Claims, 2 Drawing Sheets
`
`Bus drivers Precharge Bus lines
`circuit
`
`Bus recievcr
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`Page 1 of 8
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`SAMSUNG EXHIBIT 1001
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`US 6,366,130 B1
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`HIGH SPEED LOW POWER DATA
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`TRANSFER SCHEME
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`This application claims priority from U.S. Provisional
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`Patent Application No. 60/120,531, filed Feb. 17, 1999, the
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`disclosure of which is incorporated herein by reference in its
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`entirety.
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to a data transfer scheme,
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`and more particularly, to a high speed and low power CMOS
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`data transfer scheme.
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`2. Description of the Prior Art
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`Today’s requirements for electronic circuits require high
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`speed. Additionally,
`the circuits should be as small and
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`simple as possible due to the ever increasing number of
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`circuits that arc crowding today’s chip devices. Furthermore,
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`circuits for data transfer should not be sensitive to circuit
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`parameter mismatches, noise, and deviations in various
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`applied voltages.
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`SUMMARY OF THE INVENTION
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`The present invention provides a high speed and low
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`power CMOS data transfer arrangement that includes two
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`active pull up/pull down bus drivers, a differential bus that
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`precharges to a specific voltage level and a latched differ-
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`ential sense amplifier that serves as a bus receiver.
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`In accordance with one embodiment of the present
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`invention, a data transfer arrangement
`includes two bus
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`drivers, a voltage precharge source, a differential bus
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`coupled to the bus drivers and to the voltage precharge
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`source, and a latching sense amplifier coupled to the differ-
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`ential bus.
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`In accordance with another embodiment of the present
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`invention, the latching sense amplifier is arranged as a cross
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`coupled latched amplifier.
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`In accordance with a further embodiment of the present
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`invention, the two bus drivers consist of active pull up/pull
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`down bus drivers.
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`invention provides a data transfer
`Thus,
`the present
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`arrangement that operates at a high speed and uses low
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`power. The data transfer arrangement is faster because the
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`bus voltage swing passes directly to high gain nodes of the
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`cross-coupled latched amplifier. Additionally, the data trans-
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`fer arrangement uses a lower number of stacked transistors
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`coupled between the Supply voltage and the high gain nodes
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`when compared to the prior art. Additionally, the arrange-
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`ment according to the present invention is less sensitive to
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`deviations in voltage sources and the deviation of threshold
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`voltage concerns of the input transistors. Additionally, the
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`arrangement
`is less sensitive to circuit parameter
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`mismatches, data bus common mode noise and power bus
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`noises.
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`Other features and advantages of the present invention
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`will be understood upon reading and understanding the
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`detailed description of the preferred embodiments below, in
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`conjunction with reference to the drawings, in which like
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`numerals represent like elements.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a schematic of a differential data transfer
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`arrangement in accordance with the present invention; and
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`FIG. 2 is a schematic of a circuit for a sense amplifying
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`latch for use in the data transfer arrangement illustrated in
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`FIG. 1.
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`DETAILED DESCRIPTION OF THE
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`PREFERRED EXEMPLARY EMBODIMENTS
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`FIG. 1 illustrates a data transfer arrangement circuit 10
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`that includes two bus drivers 11, 12, a precharge circuit 13,
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`and two complementary bus lines 14, 15. The bus lines are
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`inputs to a bus receiver 16 that is arranged as a latching sense
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`amplifier.
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`The two bus drivers are complementary and consist,
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`preferably, of two active pull up/active pull down bus
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`drivers.
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`Operation of the data transfer arrangement consists of two
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`phases: A bus precharge phase and a data transfer phase.
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`During the bus precharge phase,
`the control input PR
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`(control signal for bus precharge circuit 13) is high and
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`signal inputs DT (true phase of dual-rail data function) and
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`DC (complement phase of dual-rail data function) are low.
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`The true phase driver on transistors 20 and 21 and the
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`complement phase driver on transistors 22 and 23 are in high
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`impedance state and both bus lines are equalized and pre-
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`charged to a potential VP, (buses precharging voltage level)
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`through the turned on transistors 24, 25 and 26.
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`During the data transfer phase, the control input PR is low.
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`The signal inputs become differential: DT is high and DC is
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`low, and vise versa. One of the drivers is pulled up and
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`charges the appropriate bus line from the precharged level
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`VP, toward a more positive Vdd—V, (where V, is the thresh-
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`old voltage of the pull up NMOS transistor of the driver). At
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`the same time, the other driver is pulled down and discharges
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`the opposite bus line from the precharged level VP, towards
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`a more negative level V55 (ground). This provides a differ-
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`ential voltage: +dV and —dV from the precharging level VP,
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`between true and complement bus lines. To provide proper
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`operation of the bus receiver (the sensing amplifier), the
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`minimum voltage difference 2* dV,m-n (swing) between the
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`lines may be about 0.05—0.20V. This low voltage swing is a
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`basis to obtain high frequency of data transfer through the
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`bus.
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`FIG. 2 illustrates sensing amplifier 16. Preferably, the
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`sensing amplifier is a cross-coupled latched amplifier.
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`The sense amplifier operates in two phases, a precharge
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`phase and a data transfer phase. However,
`the sensing
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`amplifier operates opposite to analogous phases of the bus
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`driver.
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`When the control input CLK is low and the bus driver is
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`in the data transfer mode, the sensing amplifier is in the
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`precharge mode. The cross-coupled latched amplifier is
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`isolated from the power buses (transistors 30 and 31 arc
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`turned off).
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`Transistors 32 and 33 are turned on and thus, the bus
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`voltage swing passes to the internal nodes IT (positive
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`binary single-rail internal point of the sensing amplifier) and
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`IC (negative binary single-rail data input phase internal
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`point of the sensing amplifier) of the latched amplifier. The
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`output nodes of both dynamic gates are precharged to Vdd
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`and the complementary outputs QT (true phase of dual-rail
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`data output signal) and QC (complement phase of dual-rail
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`output data signal) of the sensing amplifier become high.
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`When the control input CLK is high and the bus driver is
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`in the precharge mode, the sensing amplifier is in the data
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`transfer mode. Transistors 32 and 33 are turned of and
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`isolate the internal nodes IT and IC of the latched amplifier
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`from the bus lines. The cross-coupled latched amplifier is
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`connected to power buses (transistors 30 and 31 are turned
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`on) and it begins to amplify the low voltage swings of the
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`internal nodes IT and IC to full logic levels. The output node
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`US 6,366,130 B1
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`3
`of one of the dynamic gates is discharged to ground and the
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`appropriate output QT or QC of the sensing amplifier
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`becomes low.
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`The use of domino output stages in accordance with the
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`present invention instead of static inverters is necessary to
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`avoid leakage currents and output glitches, which may
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`appear because potentials of nodes IT and IC are approxi-
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`mately equal to VP, during the operating cycle of the bus
`driver. Weak PMOS transistors 34 and 35 are preferably
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`included in the sensing amplifier to help prevent output
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`glitches.
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`The data transfer arrangement in accordance with the
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`present invention provides an increase in speed due to the
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`differential low voltage swing bus driver in combination
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`with the use of the latched differential sense amplifier as the
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`bus receiver.
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`A further increase in speed is attained with the data
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`transfer arrangement due to the pull up/pull down bus
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`drivers, which provide equal low differential voltage swings
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`+dV/ —dV in both bus lines. This allows both bus lines to be
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`active during the data transfer phase, eliminates the neces-
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`sity to use special circuits for holding the precharged level
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`and leads to a reduction in the capacitance load of the driver.
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`The buses precharging to the specific level between
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`ground and Vd(Vp,=K*Vdd, where K=‘/3 for the ideal MOS
`model) also provides: equal charge and discharge driver
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`currents ICh=IdCh, provided by the NMOS pull up follower
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`and the NMOS pull down switch,
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`therefore, equal differential voltage swings dV in both
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`charged and discharged bus during the data transfer phase
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`Pdtf:+dV=ICh*Ddfl/CLOAD; and —dV=IdCh*Td,7JCLOAD.
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`the CLOAD charging from Vpr up to Vdd); Idch represents the
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`charging from Vpr up to V55); CLOAD represents the bus
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`up from VP, during data transfer phase; —dV represents the
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`bus voltage change down from Vpr during data transfer
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`phase; and Tdtf represents the data transfer phase duration.
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`The buses precharging to the specific level between ground
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`and Vdd also provides high noise immunity due to active
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`mode for both buses that equal low output resistances of the
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`drivers in pull up and pull down mode and; low total power
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`consumed by drivers during the cycle of operation (transfer
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`plus precharge).
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`The latched sense amplifier is faster due to the bus voltage
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`swing passing directly to the high-gain nodes IT and IC of
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`the cross- coupled latched amplifier, the lower number of
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`stacked transistors that are connected between the supply
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`voltage Vdd (or VCC) and nodes IT and IC, the fact that during
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`latching of the IT and IC nodes, the nodes are charged by
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`K*Vdd and (1—K)*Vdd instead of simply Vdd. Additionally,
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`the speed of the latched sensing amplifier is effected little by
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`the deviation of voltage VP, and the deviation of the thresh-
`old voltage of the input transistors.
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`In addition to the higher speed and low power consump-
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`tion of the data transfer arrangement in accordance with the
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`present invention, the arrangement is also less sensitive to
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`circuit parameters mismatching, data bus common mode
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`noise and power buses’ noises since both drivers are active
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`during data transfer phase. During the appropriate bus
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`precharge phase, the bus receiver is isolated from the bus
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`lines.
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`Although the invention has been described with reference
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`to specific exemplary embodiments, it will be appreciated
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`that it is intended to cover all modifications and equivalents
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`within the scope of the appended claims.
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`Page 5 of 8
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`What is claimed is:
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`1. A data transfer arrangement comprising:
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`two bus drivers;
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`a voltage precharge source;
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`a differential bus coupled to the bus drivers and to the
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`voltage precharge source; aid
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`a latching sense amplifier coupled to the differential bus;
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`wherein the latching sense amplifier comprises:
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`a first stage including a cross-coupled latch coupled to a
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`differential data bus; and
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`an output stage coupled to an output of said first stage;
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`wherein the output of the first stage is coupled to an
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`input of the output stage;
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`wherein the differential bus and the differential data bus
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`are precharge to a voltage Vpr between Vdd and
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`ground, where Vpr=K*Vdd, and K is a precharging
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`voltage factor.
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`2. The data transfer arrangement in accordance with claim
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`1 wherein the bus drivers comprise active pull-up and active
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`pull-down bus drivers.
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`3. The data transfer arrangement in accordance with claim
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`1, wherein the first stage of the latching sense amplifier
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`comprises:
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`a plurality of input pass transistors each having a gate, a
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`source terminal, and a drain; and
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`a plurality of NMOS and PMOS transistors each having
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`a gate, a source terminal, and a drain;
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`wherein the drains of the input pass transistors are
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`coupled to the drains of the cross-coupled latch ampli-
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`fier NMOS and PMOS transistors, each source terminal
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`of the input pass transistors is coupled to an input, the
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`sources of the cross-coupled latch amplifier NMOS
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`transistors are coupled to the drain of the NMOS
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`transistor coupled to a clock signal
`input, and the
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`sources of the PMOS transistors are coupled to the
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`drain of the PMOS transistor having a gate coupled to
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`an inverted clock signal input.
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`4. The data transfer arrangement in accordance with claim
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`1, wherein the output stage of the latching sense amplifier
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`comprises:
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`a plurality of input transistors each having a gate, a source
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`terminal, and a drain; and
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`a pair of cross-coupled PMOS transistors each having a
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`gate, a source terminal, and a drain;
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`a first PMOS transistor having a gate, a source terminal,
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`and a drain, the gate being coupled to a clock signal
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`input; the source being coupled to the source of the first
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`of the cross-coupled PMOS transistors; and the drain
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`being coupled to the drain of the first of the input
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`transistors; and
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`a second PMOS transistor having a gate, a source
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`terminal, and a drain, the gate being coupled to a clock
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`signal input; the source being coupled to the source of
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`a second of the cross-coupled PMOS transistors; and
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`the drain being coupled to the drain of the second of the
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`input transistors;
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`wherein the sources of the input transistors are coupled to
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`a source of an NMOS transistor having a gate coupled
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`to a clock signal input;
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`wherein the sources of the cross-coupled PMOS transis-
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`tors are coupled to a voltage supply, the drains of the
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`cross-coupled PMOS transistors are coupled to the
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`drains of the input transistors; and
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`wherein the drains of the cross-coupled transistors pro-
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`vide a true and a complement phase of a data output
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`signal.
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`Page 5 of 8
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`US 6,366,130 B1
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`6
`isolating the cross-coupled latch amplifier from a plu-
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`rality of power buses by turning off an NMOS
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`transistor coupled to the clock signal input and a
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`PMOS transistor coupled to the inverted clock signal
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`input;
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`passing a bus voltage swing to a plurality of internal
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`nodes IT and IC of the latched amplifier;
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`precharging both dynamic gates to Vdd; and
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`providing a high true phase and a high complement
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`phase of a data output signal; and
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`wherein the data transfer phase operates when a control
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`input clock signal is high, said phase comprising the
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`steps of:
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`isolating the internal nodes of the latched amplifier
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`from the bus lines by turning off the pass input
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`transistors;
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`connecting the cross-coupled latched amplifier to
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`power buses by turning on an NMOS transistor
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`coupled to the clock signal
`input and a PMOS
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`transistor coupled to an inverted clock signal input;
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`amplifying each low voltage swing of the internal
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`nodes to full logic levels;
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`discharging an output node of one of the dynamic gates
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`to ground; and
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`providing a low true phase and a low complement
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`phase of the data output signal.
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`*
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`5
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`5. The data transfer arrangement in accordance with claim
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`1, wherein the voltage precharge source is configured to
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`precharge the differential bus to a predetermined voltage that
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`is less than a logic high voltage and greater than a logic low
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`voltage.
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`6. The data transfer arrangement in accordance with claim
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`1 further comprising a precharge circuit coupled between the
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`precharge source and the differential bus.
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`7. The data transfer arrangement in accordance with claim
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`2 wherein the active pull up and pull down bus drivers are
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`NMOS transistors.
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`8. A method of operation of a data transfer arrangement
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`comprising:
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`two bus drivers;
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`a voltage precharge source;
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`a differential bus coupled to the bus drivers and to the
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`voltage precharge source; and
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`a latching sense amplifier coupled to the differential bus;
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`wherein the latching sense amplifier comprises:
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`a first stage including a cross-coupled latch coupled to
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`a differential data bus; and
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`an output stage coupled to an output of said first stage;
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`wherein the output of the first stage is coupled to an
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`input, and
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`wherein the sense amplifier operates in two phases:
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`a precharge phase and a data transfer phase;
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`wherein the precharge phase operates when a control
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`input clock signal is low, said phase comprising the
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`steps of:
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`Page 6 of 8
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`Page 6 of 8
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`

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`US 6,366,130 C1
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`1
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`INTER PARTES
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`REEXAMINATION CERTIFICATE
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`ISSUED UNDER 35 U.S.C. 316
`THE PATENT IS HEREBY AMENDED AS
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`INDICATED BELOW.
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`Matter enclosed in heavy brackets [ ] appeared in the
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`patent, but has been deleted and is no longer a part of the 10
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`patent; matter printed in italics indicates additions made
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`to the patent.
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`AS A RESULT OF REEXAMINATION, IT HAS BEEN
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`DETERMINED THAT:
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`15
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`The patentability of claims 1-2 and 5-7 is confirmed.
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`New claim 9 is added and determined to be patentable.
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`Claims 3-4 and 8 were not reexamined.
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`9. The data transfer arrangement ofclaim I wherein the 20
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`output stage includes cross-coupledfeedback.
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`*
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`Page 8 of 8
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`Page 8 of 8