`STANDARD
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`
`
`JEDEC Dictionary of Terms for
`Solid-State Technology — 6th Edition
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`
`
`JESD88E
`
`(Revision of JESD88D, December 2009)
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`
`
`JUNE 2013
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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`NOTICE
`
`JEDEC standards and publications contain material that has been prepared, reviewed, and
`approved through the JEDEC Board of Directors level and subsequently reviewed and approved
`by the JEDEC legal counsel.
`
`JEDEC standards and publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchasers, facilitating interchangeability and
`improvement of products, and assisting the purchaser in selecting and obtaining with minimum
`delay the proper product for use by those other than JEDEC members, whether the standard is to
`be used either domestically or internationally.
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`JEDEC standards and publications are adopted without regard to whether or not their adoption
`may involve patents or articles, materials, or processes. By such action JEDEC does not assume
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`the JEDEC standards or publications.
`
`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer
`viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
`publication may be further processed and ultimately become an ANSI standard.
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`No claims to be in conformance with this standard may be made unless all requirements stated in
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`JEDEC Standard No. 88E
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`
`
`
`Foreword
`
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`
`
`This dictionary was originally prepared and edited by a special Working Group consisting of JEDEC
`consultants Fred A. Mann and Frank S. Stein, under the direction of the JEDEC Board of Directors, and is
`periodically updated by JEDEC Committee JC-10 on Terms, Definitions, and Symbols. After the 1st edition,
`regular contribution has been made by David Sweetman. Publication of the JEDEC Dictionary was approved
`by the JEDEC Board of Directors under Ballot JCB-00-97.
`
`This Sixth Edition includes definitions from 14 standards that were not included in the Fifth Edition plus
`revised definitions from 26 additional publications and standards that have been updated. All reported errors
`and necessary rewording have been taken into account.
`
`Introduction
`
`As new or revised JEDEC and EIA publications* are issued, their definitions are considered for inclusion in
`this dictionary. All publications with definitions in this edition of the dictionary are listed in Annex A. The
`following are often not included: (1) terms having a specialized meaning only within the context of a particular
`publication (usually a test method), e.g., “brush: A toothbrush with a handle made up of nonreactive material
`…”; and (2) concepts where the publication gives only a symbol and a term but no definition. This dictionary,
`like any dictionary, is primarily intended to define concepts. For an extensive list of symbols and abbreviations
`with the corresponding terms for many variations (dc, peak, rms, small signal, large signal, etc.), see JEP104,
`Reference Guide to Letter Symbols for Semiconductor Devices.
`
`All entries are reviewed for punctuation, grammar, and clarity, as well as for accuracy, and reworded if such is
`considered warranted. If a definition is substantially recast, the date of the source publication is followed by a
`pound sign (#). The editors have made every effort to ensure that the intent of the original definition is retained
`in all cases. When the same term is defined in more than one source publication in substantially different
`words having essentially equivalent meanings, the formulation is selected that, in the opinion of the editors, is
`the most completely and clearly stated, and the pound sign is applied to the references to the other
`publications. If the same term is defined with different meanings in two or more publications, all forms are
`given in alphanumeric order by publication reference. The definitions are numbered (1), (2), … , but no order
`of preference is intended.
`
`While most of the conventions used in this dictionary are self-explanatory, two may need further explanation:
`(1) Terms separated by semicolons (;) are synonyms. (2) Square brackets [ ] enclosing a part of a term and
`possibly parts of its definition indicate that the words placed between them may replace all or some of the
`preceding words. Selection of the bracketed part of the term requires the selection of the bracketed parts of the
`definition. This convention is used to show at first sight the construction of terms having parallel definitions.
`
`
`* As used in this dictionary, the word “publication” is a generic term that includes standards.
`
`- i -
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`
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`Scope
`
`Each term and definition in this dictionary has been included strictly for application within the solid-state
`industry. Many of the terms and definitions in this dictionary may have applicability beyond the scope of the
`JEDEC Solid State Technology Association; however, an assumption of such extended applicability is the
`responsibility of the user. The goal is to include the appropriate terms and definitions from all JEDEC
`publications and standards. At the present time, only terms and definitions from the publications listed in
`Annex A are included.
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`
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`- ii -
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`JEDEC DICTIONARY OF TERMS FOR SOLID-STATE TECHNOLOGY
`
`Terms, abbreviations, letter symbols, and definitions
`A
`
`A: See “port A; port B”.
`
`A; a: See “anode terminal”.
`
`abbreviation: A shortened form of a word or expression.
`
`ABD: See “avalanche breakdown diode”.
`
`JEDEC Standard No. 88E
`Page 1
`
`
`References
`
`JESD77D, 8/12
`JESD99C, 12/12
`
`ABD array: A device having three or more terminals and containing multiple diodes within a
`single package, with at least one of the diodes being an ABD.
`
`JESD77D, 8/12
`JESD210, 12/07
`
`NOTE ABD arrays can be classified as 1) devices with multiple discrete semiconductor chips; and 2)
`devices with multiple diode junctions diffused into a single semiconductor chip.
`
`above-passivation layer (APL): A low-impedance metal plane, built on the surface of a die
`above the passivation layer, that connects a group of bumps or pins (typically power or ground).
`NOTE This structure is sometimes referred to as a redistribution layer (RDL). There may be multiple APLs
`(sometimes referred to as islands) for a power or ground group.
`
`JS-001-2012, 4/12
`
`absolute accuracy error: Synonym for “total error”.
`
`absolute maximum rated junction temperature: The maximum junction temperature of an
`operating device, as listed in its data sheet and beyond which damage (latent or otherwise) may
`occur; it is frequently specified by device manufacturers for a specific device and/or technology.
`
`NOTE Manufacturers may also specify maximum case temperatures for specific packages.
`
`JESD99C, 12/12
`
`JESD22-A108D, 11/10#
`
`absolute maximum rated temperature: The maximum junction or ambient temperature of an
`operating device, as listed in its data sheet and beyond which damage (latent or otherwise) may
`occur.
`
`JESD89-1A, 10/07
`JESD89-3A, 11/07
`
`NOTE Manufacturers may also specify maximum case temperatures for specific packages.
`
`absolute maximum rated voltage: The maximum voltage that may be applied to a device, as
`listed in its data sheet and beyond which damage (latent or otherwise) may occur; it is frequently
`specified by device manufacturers for a specific device and/or technology.
`
`JESD22-A108D, 11/10#
`JESD89-1A, 10/07#
`JESD89-2A, 10/07#
`JESD89-3A, 11/07#
`
`absolute maximum rating: Synonym for “maximum rating”.
`
`ABTXXXXXX series: A BiCMOS series that includes devices whose input logic levels are
`TTL-compatible and whose outputs are specified at TTL levels.
`
`accelerated ELF test time (tA): The duration of the accelerated ELF test.
`
`accelerated equivalent soak: A soak at a higher temperature for a shorter time (compared to the
`standard soak) to provide roughly the same amount of moisture absorption.
`
`JESD77D, 8/12
`
`JESD54, 2/96
`
`JESD74A, 2/07
`
`J-STD-020D.1, 3/08
`
`____________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`References
`
`JESD89, 8/01
`
`JEP122G, 10/11
`JEP143C, 7/12
`JESD74A, 2/07#
`JESD85, 7/01#
`JESD91A, 8/01#
`JESD94A, 7/08
`
`
`
`JEDEC Standard No. 88E
`Page 2
`
`Terms, abbreviations, letter symbols, and definitions
`
`accelerated soft error rate (ASER): A soft error rate in the presence of an intense ionizing
`radiation source.
`
`acceleration factor (A, AF): For a given failure mechanism, the ratio of the time it takes for a
`certain fraction of the population to fail, following application of one stress or use condition, to
`the corresponding time at a more severe stress or use condition.
`
`NOTE 1 Times are generally derived from modeled time-to-failure distributions (lognormal, Weibull,
`exponential, etc.).
`
`NOTE 2 Acceleration factors can be calculated for temperature, electrical, mechanical, environmental, or
`other stresses that can affect the reliability of a device.
`
`NOTE 3 Acceleration factors are a function of one or more of the basic stresses that can cause one or more
`failure mechanisms. For example, a plot of the natural log of the time-to-failure for a cumulative constant
`percentage failed (e.g., 50%) at multiple stress temperatures as a function of 1/kT, the reciprocal of the
`product of Boltzmann’s constant in electronvolts per kelvin and the absolute temperature in kelvins, is linear
`if one and only one failure mechanism is involved. The best-fit linear slope is equal to the apparent activation
`energy in electronvolts.
`
`NOTE 4 The abbreviation AF is often used in place of the symbol A.
`
`acceleration factor, stress (Af): The acceleration factor due to the presence of some stress (e.g.,
`current density, electric field, humidity, temperature cycling).
`
`acceleration factor, temperature (AT): The acceleration factor due to changes in temperature.
`
`NOTE 1 This is the acceleration factor most often referenced. The Arrhenius equation for reliability is
`commonly used to calculate the acceleration factor that applies to the acceleration of time-to-failure
`distributions for microcircuits and other semiconductor devices:
`
`JEP122G, 10/11
`JEP143C, 7/12
`
`JEP122G, 10/11
`JEP143C, 7/12
`JESD74A, 2/07#
`
`AT = λT1/λT2 = exp[(–Eaa/k)(1/T1 – 1/T2)]
`
`where
`
`Eaa is the apparent activation energy (eV);
`k is Boltzmann’s constant (8.62 × 10–5 eV/K);
`T1 is the absolute temperature of test 1 (K);
`T2 is the absolute temperature of test 2 (K);
`λT1 is the observed failure rate at test temperature T1 (h-1);
`λT2 is the observed failure rate at test temperature T2 (h-1).
`
`NOTE 2 The best-fit linear slope of a plot of the natural log of the time-to-failure as a function of 1/kT, the
`reciprocal of the product of Boltzmann’s constant in electronvolts per kelvin and the absolute temperature in
`kelvins, is equal to the apparent activation energy in electronvolts.
`
`NOTE 3 λq = λo · AT, where λq is the quoted (predicted) system failure rate at some system temperature Ts,
`λo is the observed failure rate at some test temperature Tt, and AT is the temperature acceleration factor from
`Tt to Ts.
`
`acceleration factor, voltage (AV): The acceleration factor due to changes in voltage.
`
`JEP143C, 7/12
`JESD74A, 2/07
`
`________________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
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`JEDEC Standard No. 88E
`Page 3
`
`References
`
`JEP143C, 7/12
`JEP148A, 12/08
`
`JESD16-A, 4/95
`
`JESD16-A, 4/95
`
`JESD100-B, 12/99
`
`JESD14, 11/86#
`
`JESD100-B, 12/99
`
`EIA-557-B, 2/06
`JEP132, 7/98
`
`RS-390-A, 2/81
`
`J-STD-035, 5/99
`
`
`
`Terms, abbreviations, letter symbols, and definitions
`
`acceleration model: A mathematical formulation of the relationship between (1) the rate (speed)
`of a degradation mechanism or the time-to-failure and (2) the conditions or stresses that caused
`the degradation.
`
`acceptance inspection: A sampling inspection or series of sampling inspections used to
`determine the suitability of a lot of material for shipment.
`
`accept number: The maximum number of nonconforming components in the sample for which
`acceptance of the lot is allowed under the sampling plan.
`
`access time: The time interval between the application of a specific input pulse and the
`availability of valid signals at an output.
`
`ac controller: A circuit that produces, from an ac input, an ac output that is proportional to a
`control input.
`
`accumulator: A register in which one operand of an operation can be stored and subsequently
`replaced by the result of another operation. (Ref. IEC 824.)
`
`accuracy: The difference between the sample estimate and the population parameter being
`estimated.
`
`ac noise margin: The maximum transient or pulse voltage amplitude of extraneous signal that
`can be algebraically added to the noise-free worst-case input level without causing the output
`voltage to deviate from the allowable logic voltage level.
`
`acoustic data, A-mode: Acoustic data collected at the smallest X-Y-Z region defined by the
`limitations of the given acoustic microscope. An A-mode display contains amplitude and
`phase/polarity information as a function of time of flight at a single point in the X-Y plane.
`
`Example of A-mode display
`
`
`
`____________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`References
`
`J-STD-035, 5/99
`
`
`
`JEDEC Standard No. 88E
`Page 4
`
`Terms, abbreviations, letter symbols, and definitions
`
`acoustic data, B-mode: Acoustic data collected along an X-Z or Y-Z plane versus depth (Z)
`using a reflective acoustic microscope. A B-mode scan contains amplitude and phase/polarity
`information as a function of time of flight at each point along the scan line. A B-mode scan
`furnishes a two-dimensional (cross-sectional) description along a scan line (X or Y)..
`
`Example of B-mode display (bottom half of picture on left)
`
`
`
`acoustic data, C-mode: Acoustic data collected in an X-Y plane at depth Z using a reflective
`acoustic microscope. A C-mode scan contains amplitude and phase/polarity information at each
`point in the scan plane. A C-mode scan furnishes a two-dimensional (area) image of echoes
`arising from reflections at a particular depth (Z).
`
`J-STD-035, 5/99
`
`Example of C-mode display
`
`
`
`________________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`JEDEC Standard No. 88E
`Page 5
`
`References
`
`J-STD-035, 5/99
`
`
`
`Terms, abbreviations, letter symbols, and definitions
`
`acoustic data, through-transmission mode: Acoustic data collected in an X-Y plane throughout
`the depth (Z) using a through-transmission acoustic microscope. A through-transmission mode
`scan contains only amplitude information at each point in the scan plane. A through-transmission
`scan furnishes a two-dimensional (area) image of transmitted ultrasound through the complete
`thickness/depth (Z) of the sample or component.
`
`Example of through-transmission display
`
`
`
`acoustic microscope: Equipment that creates an image using ultrasound to view a specimen’s
`surface or subsurface features,
`
`J-STD-020D.1, 3/08
`
`ac terminal: A terminal that is to be connected to the ac circuit.
`
`ac test: The process of verifying the specified timing of a device.
`
`NOTE Testing of propagation delays, minimum setup and hold times, minimum pulse durations, etc., can
`be performed by using test vectors applied at the specified operating frequency of the device. Propagation
`delays of critical logic paths for system operation can be measured individually.
`
`activation energy (Ea): The excess free energy over the ground state that must be acquired by an
`atomic or molecular system in order that a particular process can occur.
`
`NOTE The activation energy is used in the Arrhenius equation for the thermal acceleration of physical
`reactions. The term “activation energy” is not applicable when describing thermal acceleration of time-to-
`failure distributions, e.g., in the Arrhenius equation for reliability; hence the need for the term “apparent
`activation energy”.
`
`active circuit element: See “circuit element, active”.
`
`JESD14, 11/86
`
`JESD12-1B, 8/93
`JESD99C, 12/12
`
`JEP122G, 10/11
`JEP143C, 7/12
`JESD85, 7/01
`JESD91A, 8/01
`
`active desiccant: Desiccant that is either fresh (new) or has been baked according to the
`manufacturer’s recommendations to renew it to original specifications.
`
`J-STD-033C, 2/12
`
`____________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`References
`
`JESD99C, 12/12
`
`JESD99C, 12/12
`
`JESD99C, 12/12
`
`JESD99C, 12/12
`
`
`
`JEDEC Standard No. 88E
`Page 6
`
`Terms, abbreviations, letter symbols, and definitions
`
`active device: A device in which at least one circuit element is an active circuit element.
`
`active element: See “circuit element, active”.
`
`active-pulldown output: A bipolar (three-state or totem-pole) output whose source-current
`capability significantly exceeds its sink-current capability.
`
`active-pullup output: A bipolar (three-state or totem-pole) output whose sink-current capability
`significantly exceeds its source-current capability.
`
`ac unbalanced voltage: The difference between the peak values of the ac voltages at the two
`outputs when the circuit is operating in the maximum-output-voltage-swing condition.
`
`ADC: See “analog-to-digital [A/D] converter”.
`
`address: (1) A character or group of characters that identifies a register, a particular part of
`storage, or some other data source or destination. (Ref. ANSI X3.172.)
`
`JESD100-B, 12/99
`
`(2) To refer to a device or a data item by its address. (Ref. ANSI X3.172.)
`
`address data input/output [ADQ(n)]: The pins that are multiplexed three ways to serve as
`address input, data input, and data output pins. When the address data input/output numbering is
`significant for device operation, the addresses are numbered beginning with 0.
`
`address inputs [A(n)]: Those inputs that select (address) a particular cell or set of cells within a
`memory array for presentation on the device outputs. The integer (n) serves to differentiate the
`address inputs, one from another. When the address number is significant for device operation, the
`addresses are numbered beginning with 0.
`
`address latch enable (AL): An input that, when true, allows the input address to be entered into
`a register and, when false, causes the address state previously entered to be latched.
`
`address register: A register that is used to hold an address. (Ref. IEC 824.)
`
`ADQ(n): See “address data input/output”.
`air ionizer: A source of charged air molecules (ions).
`
`AL: See “address latch enable”.
`
`alignment mark: Synonym for “registration mark”.
`
`“A” limit: The more positive (less negative) limit of a range of some quantity.
`
`alpha activity (of a source): The number of alpha particles produced by the decay of the alpha
`source per unit time.
`
`NOTE The preferred SI unit is the becquerel (Bq); to convert curies to becquerels, multiply the number of
`curies by 3.7 1010 Bq (exactly).
`
`JESD21-C, 1/97
`
`JESD21-C, 1/97
`
`JESD21-C, 1/97
`
`JESD100-B, 12/99
`
`JESD625B, 1/12
`
`JESD99C, 12/12
`
`JESD99C, 12/12
`
`JESD89-2A, 10/07
`
`________________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`JEDEC Standard No. 88E
`Page 7
`
`References
`
`JESD93, 9/05
`
`
`
`Terms, abbreviations, letter symbols, and definitions
`
`alternative method: For a device requirement that has a prescribed method to verify compliance,
`another method that has been verified through test and analysis to adequately verify compliance of
`the device with that requirement.
`
`ALU: See “arithmetic and logic unit”.
`
`ambient temperature; free-air temperature (TA ): The air temperature measured below a
`device, in an environment of substantially uniform temperature, cooled only by natural air
`convection and not materially affected by reflective and radiant surfaces.
`
`JESD10, 1/76
`JESD77D, 8/12
`RS-323, 3/66
`
`A-mode: See “acoustic data, A-mode”.
`
`A(n): See “address inputs”.
`
`analog gate: A gate whose output signal is a linear function of one or more input signals.
`
`analog-to-digital [A/D] converter (ADC): A converter that uniquely represents all analog input
`values within a specified total input range by a limited number of digital output codes, each of
`which exclusively represents a fractional part of the total analog input range.
`
`JESD99C, 12/12
`
`JESD99C, 12/12
`
`NOTE This quantization procedure introduces inherent errors of ½ LSB (least significant bit) in the
`representation because, within this fractional range, only one analog value can be represented free of error by
`a single digital output code.
`
`analog-to-digital processor: An integrated circuit providing the analog part of an analog-to-
`digital converter.
`
`JESD99C, 12/12
`
`NOTE Provision of external timing, counting, and arithmetic operations is necessary for implementing a
`full analog-to-digital converter.
`
`analysis of variance (ANOVA): A statistical tool that allows for the comparison of more than
`two groups of data and provides valid assumptions. Computations of ANOVA involve
`partitioning total variation into two components: the variation from differences among group
`“means”, and random variations within the groups known as “error”. ANOVA provides for
`reliable results even when certain assumptions are violated.
`
`annular ring: The metallization pad area around the top or bottom of a castellation hole.
`
`anode: (1) The p-type region from which the forward current flows within a semiconductor
`diode.
`
`NOTE In Schottky diodes, usually the barrier metal replaces the p-type semiconductor region and the
`remaining semiconductor region is n-type; however, some Schottky diodes have been made with the barrier
`metal replacing the n-type semiconductor region, in which case the remaining semiconductor region is
`p-type.
`
`(2) A circuit element to which positive bias is applied.
`
`NOTE For the purpose of JEP154, when the die is the anode the electron flow is from the substrate through
`the solder bump to the die.
`
`JEP132, 7/98
`
`JESD9B, 5/11
`
`JESD77D, 8/12
`JESD282-B, 4/00
`
`JEP154, 1/08
`
`____________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`References
`
`JESD77D, 8/12
`
`JESD77D, 8/12
`
`JESD77D, 8/12
`JESD210, 12/07
`JESD211, 12/09
`JESD282-B, 4/00
`
`JESD77D, 8/12
`
`JESD77D, 8/12
`
`JESD77D, 8/12
`
`
`
`JEDEC Standard No. 88E
`Page 8
`
`Terms, abbreviations, letter symbols, and definitions
`
`anode-cathode voltage; anode voltage (of a unidirectional thyristor): The voltage between the
`anode and cathode terminals.
`
`NOTE The anode-cathode voltage is called “positive” when the anode potential is higher than the cathode
`potential and called “negative” when the anode potential is lower than the cathode potential.
`
`anode current: Synonym for “forward current”.
`
`anode terminal (A, a) (1) (general): The terminal connected to the p-type region of the p-n
`junction or, when two or more p-n junctions are connected in series and have the same polarity, to
`the extreme p-type region.
`
`NOTE 1 See note to “anode”.
`
`NOTE 2 This definition does not apply to current-regulator diodes.
`
`NOTE 3 For voltage-reference diodes, any temperature-compensation diodes that may be included shall be
`ignored in the determination of the anode terminal.
`
`NOTE 4 For unidirectional blocking or low-capacitance ABDs, any rectifier diode(s) that may be included
`are ignored in the determination of the anode terminal.
`
`anode
`
`cathode
`
`forward
`current
`
`
`
`(2) (of a current-regulator diode): The terminal to which current flows from the external circuit
`when the diode is biased to operate as a current regulator.
`
`(3) (of a unidirectional diode thyristor): The terminal to which the current flows from the
`external circuit when the thyristor is in the on state.
`
`(4) (of a unidirectional triode thyristor): The main terminal to which the principal current flows
`from the circuit being controlled when the thyristor is in the on state.
`
`NOTE A second anode terminal may be provided for connecting to the control circuit of an n-gate
`thyristor.
`
`ANOVA: See “analysis of variance”. See also “variance components analysis”.
`
`antistatic material: Material that inhibits triboelectric charging.
`
`JESD625B, 1/12
`
`NOTE The antistatic property of a material does not necessarily correlate with the resistivity or resistance
`of the material. Unlike the dissipative and conductive properties, antistatic is not defined by a measurable
`resistance range.
`
`AOQ: See “average outgoing quality”.
`
`APL: See “above passivation layer”.
`
`________________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`JEDEC Standard No. 88E
`Page 9
`
`References
`
`JEP122G, 10/11
`JEP143C, 7/12
`JESD74A, 2/07
`JESD85, 7/01#
`
`JEP148A, 12/08
`
`JESD99C, 12/12
`
`JESD99C, 12/12
`
`JEP149, 11/04
`
`JESD22-B118, 3/11
`
`J-STD-020D.1, 3/08
`
`JESD100-B, 12/99
`
`
`
`Terms, abbreviations, letter symbols, and definitions
`
`apparent activation energy (Eaa): An energy value, analogous to activation energy, that can be
`inserted in the Arrhenius equation for reliability to calculate an acceleration factor applicable to
`changes with temperature of time-to-failure distributions.
`
`NOTE 1 An apparent activation energy should be associated with a specific failure mechanism and an
`observed time-to-failure distribution to calculate the acceleration factor for converting the observed failure
`rate to the quoted failure rate at a different temperature.
`
`NOTE 2 An activation energy is a measure of the heat energy needed to establish the rate of reaction for a
`specific failure mechanism. The reaction rate and other contributing factors, e.g., radiation, voltage,
`humidity, magnetic fields, determine the unique time-to-failure distribution for the modeled failure
`mechanism.
`
`NOTE 3 The apparent activation energy is empirically determined from the change in an observed time-to-
`failure distribution with temperature.
`
`application requirements for quality and reliability: The quality and reliability properties of
`the product required for the specified use conditions.
`
`application-specific integrated circuit (ASIC): An integrated circuit developed and produced
`for a specific application or function and for a single customer.
`
`NOTE ASICs generally use standard cell or gate array design methodology.
`
`application-specific standard product (ASSP): An integrated circuit developed and produced
`for a specific application or function but made available for multiple customers.
`
`application use conditions: The full environmental and/or operating ranges that the application
`is specified to function within.
`
`arc: A visual anomaly that is a curved scratch.
`
`area array package: A package that has terminations arranged in a grid on the bottom of the
`package and contained within the package outline.
`
`arithmetic and logic unit (ALU): The part of a processor that performs arithmetic operations
`and logic operations. (Ref. IEC 824.)
`
`arithmetic unit: The part of a processor that performs arithmetic operations. (Ref. IEC 824.)
`
`JESD100-B, 12/99
`
`NOTE This term is sometimes used for a unit that performs both arithmetic and logic operations.
`
`array density (of a gate array): The number of available gates divided by the entire chip area.
`
`NOTE Units are gates per unit area.
`
`array, logic: Synonym for “gate array integrated circuit”.
`
`JESD12-1B, 8/93
`JESD99C, 12/12
`
`JESD99C, 12/12
`
`____________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`References
`
`JEP143C, 7/12
`JESD91A, 8/01
`
`JEDEC Standard No. 88E
`Page 10
`
`
`
`Terms, abbreviations, letter symbols, and definitions
`
`Arrhenius equation (for reliability): An equation used to calculate thermal acceleration factors
`for semiconductor device time-to-failure distributions:
`
`AT = λT1/λT2 = exp [(-Eaa/k) (1/T1 – 1/T2)]
`
`where
`
`AT is the acceleration factor due to changes in temperature;
`λT1 is the observed failure rate at test temperature T1 (h-1);
`λT2 is the observed failure rate at test temperature T2 (h-1);
`Eaa is the apparent activation energy (eV);
`k is Boltzmann’s constant (8.62 × 10–5 eV/K);
`T1 is the absolute temperature of test 1 (K);
`T2 is the absolute temperature of test 2 (K).
`
`NOTE 1 The original Arrhenius equation (for atomic or molecular processes and chemical reactions) used
`the gas constant, not an activation energy, in the exponent. The “Arrhenius equation (for reliability)”, used to
`calculate a thermal acceleration factor for a given observed time-to-failure distribution and Eaa, is in the form
`of the quotient of two Arrhenius equations, so that the acceleration factor from one temperature to another
`can be calculated.
`
`NOTE 2 λq = λo · AT, where λq is the quoted (predicted) system failure rate at some system temperature Ts,
`λo is the observed failure rate at some test temperature Tt, and AT is the temperature acceleration factor from
`Tt to Ts.
`
`ART: See “auto-load read transfer”.
`
`artwork: The original, accurately scaled, oversize drawings and plastic overlays of the
`microcircuit topological layout that are used to produce the master mask plates.
`
`JESD99C, 12/12
`
`NOTE Artwork has largely been supplanted by computer-produced drawings and masks.
`
`ASER: See “accelerated soft error rate”.
`
`ASIC: See “application-specific integrated circuit”.
`
`assembled state (of a component): The state of a component that has been attached to a second-
`level assembly.
`
`JEP150, 5/05
`JEP156, 3/09
`JEP158, 11/09
`
`assembly, microelectronic: See “microelectronic assembly”.
`
`assignable cause: Synonym for “special cause”.
`
`associative memory: Synonym for “content-addressable memory”. (Ref. IEC 748-2.)
`
`JESD100-B, 12/99
`
`ASSP: See “application-specific standard product”.
`
`asymmetry, full-scale (of a digital-to-analog converter with a bipolar analog range) (IFSS or
`VFSS): The difference between the absolute values of the two full-scale analog values.
`
`JESD99C, 12/12
`
`________________________________
`# The definition in this referenced publication has been reworded in this dictionary for clarity or consistency.
`
`
`
`
`JEDEC Standard No. 88E
`Page 11
`
`References
`
`JESD12-1B, 8/93
`JESD99C, 12/12
`
`JESD89A, 10/06
`
`JESD22-B101B, 8/09
`
`EIA-557-B, 2/06
`
`
`
`Terms, abbreviations, letter symbols, and definitions
`
`asynchronous circuit: A circuit whose changes of state are not controlled by a single clock.
`
`ATE: Automated test equipment.
`
`attachment (noun): A capacitor, substrate cap, heat sink, etc. that is glued, soldered, or
`mechanically affixed to a device.
`
`attribute data: Data that result from counting items or classifying items into distinct
`nonoverlapping ca