I-l>UJ[\.)|—‘
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Page 1
`
`SAMSUNG ELECTRONICS CO.,
`
`LTD.,
`
`Petitioner,
`
`VS.
`
`ELBRUS INTERNATIONAL LIMITED,
`
`Patent Owner.
`
`\’\¢\¢\¢\¢\¢\¢\¢\¢\¢\/\/
`
`CASE NO.
`
`IPR2015-01524
`
`ATTORNEY DOCKET NO.
`
`ELBRUS—IPR2
`
`A.M. SESSION
`
`DEPOSITION OF R.
`
`JACOB BAKER, PH.D.
`
`LAS VEGAS, NEVADA
`
`APRIL 1, 2016
`
`REPORTED BY:
`
`KRISTY L. CLARK, RPR, NV CCR #708,
`
`CA CSR #13529
`
`www.Veritext.com
`
`888-391-3376
`
`Veritext Legal Solutions
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Page 1
`
`SAMSUNG ELECTRONICS CO.,
`
`LTD.,
`
`Petitioner,
`
`VS.
`
`ELBRUS INTERNATIONAL LIMITED,
`
`Patent Owner.
`
`\’\¢\¢\¢\¢\¢\¢\¢\¢\¢\/\/
`
`CASE NO.
`
`IPR2015-01524
`
`ATTORNEY DOCKET NO.
`
`ELBRUS—IPR2
`
`A.M. SESSION
`
`DEPOSITION OF R.
`
`JACOB BAKER, PH.D.
`
`LAS VEGAS, NEVADA
`
`APRIL 1, 2016
`
`REPORTED BY:
`
`KRISTY L. CLARK, RPR, NV CCR #708,
`
`CA CSR #13529
`
`www.Veritext.com
`
`888-391-3376
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`
`
`
`Page 2
`
`DEPOSITION OF R.
`
`JACOB BAKER,
`
`PH.D.,
`
`taken at 10080
`
`West Alta Drive, Suite 200,
`
`Las Vegas,
`
`Nevada,
`
`on Friday,
`
`April 1, 2016,
`
`at 9:01 a.m.,
`
`before
`
`Kristy L.
`
`Clark,
`
`Certified Court Reporter,
`
`in and for
`
`the State of Nevada.
`
`APPEARANCES:
`
`For the Petitioner:
`
`LAW OFFICE OF JOSEPH N. HOSTENY
`
`BY:
`
`JOSEPH N. HOSTENY, ESQ.
`
`181 West Madison Street
`
`Suite 4600
`
`Chicago, Illinois 60602
`
`(312) 278-3778
`
`jhosteny@hosteny.com
`
`For the Patent
`
`Owner:
`
`PAUL HASTINGS,
`
`LLP
`
`BY:
`
`STEVEN L.
`
`PARK,
`
`ESQ.
`
`BY:
`
`JOEL LIN,
`
`ESQ.
`
`1170 Peachtree
`
`Street,
`
`N.E.
`
`Suite100
`
`Atlanta, Georgia 30309
`
`(404) 815-2223
`
`stevenpark@paulhastings.com
`
`Also Present:
`
`William R. Huber, D.Sc., P.E.
`
`\'lO‘\U‘||-l>bx)|.\)|—‘
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`
`Page 3
`
`I N D E X
`
`WITNESS:
`
`R.
`
`JACOB BAKER,
`
`PH.D.
`
`EXAMINATION
`
`PAGE
`
`By Mr. Hosteny
`
`INDEX TO EXHIBITS
`
`(None marked.)
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`LAS
`
`VEGAS, NEVADA, FRIDAY,
`
`APRIL 1,
`
`2016;
`
`Page 4
`
`9:01 A.M.
`
`—oOo—
`
`Thereupon——
`
`R.
`
`JACOB BAKER, PH.D.
`
`I
`
`was called as a witness,
`
`and having been first duly
`
`sworn,
`
`was examined and testified as follows:
`
`BY MR. HOSTENY:
`
`EXAMINATION
`
`Q.
`
`A.
`
`Q.
`
`A.
`
`Will you tell us your name,
`
`please.
`
`Russell Jacob Baker.
`
`And what's your present occupation?
`
`I'm a professor of electrical and computer
`
`engineering at UNLV.
`
`Q.
`
`A
`
`Q.
`
`A.
`
`Q
`
`Okay.
`
`Do you have a PhD?
`
`Yes.
`
`Okay.
`
`You prefer Doctor or...
`
`Doctor is fine.
`
`Doctor is fine. Good.
`
`All right. Dr. Baker,
`
`when were you retained
`
`to assist
`
`Samsung in this matter?
`
`A.
`
`Q.
`
`Sometime last year.
`
`Okay.
`
`Sometime in 2015?
`
`www.Veritext.com
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`A.
`
`Q.
`
`YES .
`
`All
`
`right.
`
`And were you provided materials,
`
`Page 5
`
`or did you gather materials on your own?
`
`MR.
`
`PARK:
`
`Objection to form.
`
`THE WITNESS:
`
`I don't remember.
`
`BY MR. HOSTENY:
`
`Q.
`
`Right.
`
`Were you given the Podlesny patent,
`
`which is Exhibit 1001?
`
`There's a stack for you.
`
`MR.
`
`PARK:
`
`Is this mine?
`
`MR.
`
`HOSTENY:
`
`Actually,
`
`that one is
`
`mine.
`
`MR.
`
`PARK:
`
`Is there another?
`
`MR.
`
`REMMEL:
`
`Actually, we might not
`
`have one.
`
`MR.
`
`HOSTENY:
`
`I apologize.
`
`I didn't --
`
`MR.
`
`PARK:
`
`No.
`
`No worries.
`
`MR.
`
`HOSTENY:
`
`I didn't make four copies;
`
`I
`
`made three.
`
`MR.
`
`PARK:
`
`We can just share.
`
`MR.
`
`HUBER:
`
`Joe,
`
`I have got,
`
`I
`
`think, a full
`
`set .
`
`MR.
`
`HOSTENY:
`
`You do too.
`
`MR.
`
`HUBER:
`
`So I can give you --
`
`MR.
`
`HOSTENY:
`
`All right. All right. Yeah.
`
`Here, you
`
`can
`
`take that one.
`
`MR.
`
`PARK:
`
`Okay.
`
`Thank you.
`
`MR.
`
`HOSTENY:
`
`Okay.
`
`www.Veritext.com
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`888-391-3376
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`Veritext Legal Solutions
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`BY MR. HOSTENY:
`
`Q.
`
`All righty.
`
`Page 6
`
`Were you given the Podlesny patent exhibit,
`
`what's been marked as Exhibit 1001 in the proceeding?
`
`A.
`
`I don't recall if I was given the patent or I
`
`downloaded it from some place on the Internet.
`
`Q.
`
`All right.
`
`In any event, you obtained it
`
`from somewhere?
`
`A.
`
`Yes.
`
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`Q.
`
`Okay. Okay. At Exhibit —— wait a minute.
`
`Would you take a look at Exhibit 1005, please.
`
`A.
`
`Q.
`
`(Witness complies.)
`
`That's the Sukegawa patent; right?
`
`MR. PARK:
`
`You guys have one for me?
`
`MR. HOSTENY:
`
`I keep --
`
`MR. PARK: We may have some other copies.
`
`MR. HOSTENY: Wait a minute. No.
`
`I'm
`
`looking at the wrong stack here, Steve. Hold on just a
`
`second.
`
`MR. PARK:
`
`Thanks.
`
`MR. HOSTENY:
`
`In fact, why don't you just
`
`take —— you didn't mark this up or anything, did you?
`
`MR. HUBER:
`
`I did not.
`
`MR. HOSTENY: Why don't you just take that
`
`stack?
`
`wnNwLVerfiexLcon1
`
`888-391-3376
`
`Veritext Legal Solutions
`
`
`
`MR. PARK: Fantastic.
`
`MR. HOSTENY:
`
`That was Bill's, and we can --
`
`Page 7
`
`we'll use
`
`this one here.
`
`MR. PARK: Okay.
`
`MR. HOSTENY: All right? Okay.
`
`Yeah,
`
`this is separate. That's just for the
`
`reporter.
`
`BY MR. HOSTENY:
`
`Q.
`
`All right. Have you had a chance to look at
`
`1005,
`
`the
`
`Sukegawa patent?
`
`A.
`
`(Witness reviewing document.)
`
`YES .
`
`Q.
`
`And did you obtain that patent sometime last
`
`summer or last year?
`
`A.
`
`Q.
`
`Yes.
`
`How did you identify the Sukegawa patent?
`
`Did someone tell you,
`
`or did you find it on your own?
`
`A.
`
`Q.
`
`A.
`
`Q.
`
`I don't recall.
`
`Okay.
`
`In any event, you got it.
`
`Take a look at 1006,
`
`the Watanabe patent.
`
`Okay.
`
`Did you obtain a copy of that from some
`
`source,
`
`either the Internet or someone else?
`
`A.
`
`Q.
`
`YES .
`
`All right. This would have been last year?
`
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`A.
`
`Q.
`
`Yes.
`
`All right.
`
`Take a look at Exhibit 1007,
`
`the
`
`Page 8
`
`Hardee patent.
`
`A.
`
`Q.
`
`Okay.
`
`Is that a patent that you also obtained
`
`sometime last year?
`
`A.
`
`Q.
`
`paper.
`
`YES .
`
`And lastly,
`
`Exhibit 1008, which is an IEEE
`
`MR. PARK:
`
`Seem to be missing one.
`
`MR. HOSTENY: Not there?
`
`MR. PARK:
`
`NO.
`
`MR. HOSTENY: Got one? Okay. Let me see if
`
`I have an
`
`extra.
`
`MR. PARK: Has this been marked?
`
`MR. HOSTENY: Hold on a second.
`
`MR. PARK:
`
`Oh, here it is.
`
`MR. HOSTENY:
`
`You got it?
`
`MR. PARK: Yeah.
`
`It's here.
`
`Sorry.
`
`MR. HOSTENY: Okay.
`
`Problem solved.
`
`BY MR. HOSTENY:
`
`Q.
`
`A.
`
`Q.
`
`Okay. Dr. Baker, have you looked at 1008?
`
`Yes.
`
`And is that a document that you received
`
`sometime last
`
`last year?
`
`www.Veritext.com
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`888-391-3376
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`Veritext Legal Solutions
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`A.
`
`I don't recall if I received it or I
`
`downloaded it myself.
`
`Q.
`
`Okay. Either way, you had it last year,
`
`Page 9
`
`though; correct?
`
`A.
`
`Yes.
`
`Q.
`
`Okay. Did you do any independent searching
`
`to find any references, patents, or documents that you
`
`thought might be pertinent to the work you were asked
`
`to do?
`
`MR. PARK:
`
`I'm going to object and instruct
`
`the witness to answer that question but not reveal any
`
`privileged communications in the answer.
`
`THE WITNESS:
`
`Can you repeat
`
`the question,
`
`please.
`
`MR. HOSTENY: Why don't you read it back.
`
`(Record read by the reporter.)
`
`THE WITNESS:
`
`I believe I did, yes.
`
`BY MR. HOSTENY:
`
`Q.
`
`Did any of those documents become references
`
`that you relied on in your report?
`
`A.
`
`Q.
`
`I don't recall.
`
`All right.
`
`And your report, by the way,
`
`is
`
`Exhibit 1002, or your declaration,
`
`I suppose I should
`
`say?
`
`A.
`
`Yes.
`
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`Page 10
`
`Q.
`
`Okay. Going back to Exhibit 1008,
`
`take a
`
`look at Figure 4.
`
`A.
`
`Q.
`
`(Witness complies.) Okay.
`
`Do you see the horizontal lines connected to
`
`the right side by something called QEQ?
`
`A.
`
`Q.
`
`A.
`
`Yes.
`
`That is a transistor?
`
`If what you're referring to is the same thing
`
`that I
`
`think you're referring to, yes.
`
`A transistor is
`
`connected with its gate to a signal on the far right,
`
`which is a vertical line labeled fee 3.
`
`Q.
`
`All right. What kind of transistor is that?
`
`Is that a PMOS or an NMOS,
`
`if you're familiar with that
`
`terminology?
`
`A.
`
`Q.
`
`It is an NMOS.
`
`Okay. And if fee 3 —— if there's a signal on
`
`fee 3, what happens with the transistor?
`
`MR. PARK: Objection to form.
`
`BY MR. HOSTENY:
`
`Does anything happen with the transistor?
`
`A.
`
`If the signal
`
`is 0 volts on fee 3,
`
`the
`
`transistor's off. And if the signal on fee 3 is, say,
`
`Vdd,
`
`the transistor's on.
`
`Q. What's the value of Vdd?
`
`MR. PARK: Objection to form.
`
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`Page 11
`
`BY MR. HOSTENY:
`
`Let me clarify. Vdd is a voltage; correct?
`
`A.
`
`Yes. Vdd is a power supply voltage. And on
`
`the first page of Exhibit 1008,
`
`in the left—hand
`
`column, one value for Vdd that's listed there, about
`
`the tenth line from the bottom in that left column,
`
`is
`
`5 volts for Vdd.
`
`Q.
`
`Okay. Okay.
`
`So if fee 3
`
`in Figure 4
`
`is
`
`zero, correct me if I'm wrong,
`
`the transistor is turned
`
`off?
`
`A.
`
`Yes.
`
`Q.
`
`And if fee 3
`
`is Vdd or 5 volts,
`
`then the
`
`transistor would be turned on?
`
`A.
`
`Yes.
`
`Q.
`
`Okay.
`
`Can the transistor be turned on with a
`
`value of other than 5 volts, something less, for
`
`example?
`
`If so, how much?
`
`MR. PARK: Objection to form.
`
`THE WITNESS: When you say "turned on," can
`
`you be a little bit more specific what that means?
`
`BY MR. HOSTENY:
`
`Q.
`
`I was trying to use your terminology.
`
`Suppose that there's a signal on fee 3, but it's not 5
`
`volts.
`
`Suppose it's 4.5 volts.
`
`Or 4.
`
`Let's just say
`
`4 or above. Will that transistor turn on?
`
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`
`MR. PARK: Objection to form.
`
`THE WITNESS:
`
`It will turn on,
`
`just not as
`
`Page 12
`
`much as when there's 5 volts on the gate of the
`
`transistor.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay.
`
`Is there a point between 5 volts and
`
`zero where it will not turn on?
`
`MR. PARK:
`
`Same objection.
`
`THE WITNESS: Assuming that the only voltages
`
`on the chip are zero —— between zero and Vdd, meaning
`
`there are no negative voltages --
`
`BY MR. HOSTENY:
`
`Uh—huh.
`
`A.
`
`—— then, when fee 3 reaches the threshold
`
`voltage of the transistor, say,
`
`.8 volts, and assuming
`
`one of the lines connected to the transistor is at 0
`
`volts,
`
`the transistor will shut off or start to
`
`shutoff.
`
`Q.
`
`Okay. What's —— what is the "threshold"?
`
`What do you mean by that?
`
`A.
`
`Loosely speaking,
`
`that's the voltage between
`
`the gate and the source where the transistor starts to
`
`conduct current.
`
`Now, below the threshold voltage,
`
`the
`
`transistor still can leak current,
`
`so it's not totally
`
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`Page 13
`
`off. But,
`
`in general
`
`terms, when one of skill in the
`
`art says threshold voltage,
`
`they're referring to when
`
`the transistor tllI‘I1S On.
`
`Q.
`
`Okay. All right.
`
`So it's possible for this
`
`transistor to have a threshold voltage of 0.8 volts, as
`
`low as that?
`
`MR. PARK: Objection to form.
`
`BY MR. HOSTENY:
`
`Q.
`
`You may have been giving me an example,
`
`so
`
`I —— I —— I may not be correct when I say that.
`
`A.
`
`I don't recall in the paper what value of
`
`threshold voltage they actually specified.
`
`Q.
`
`Okay. Okay. And the voltage —— the
`
`threshold voltage you mentioned is measured between,
`
`I
`
`think you said,
`
`the gate and the source?
`
`A.
`
`The threshold voltage is measured between the
`
`gate and the source, and it assumes there's a potential
`
`between the drain of the transistor and a source so
`
`that current can flow.
`
`Q.
`
`Okay. When you say "potential," what do you
`
`mean?
`
`A.
`
`Q.
`
`Voltage.
`
`Okay.
`
`Now,
`
`if this transistor in Figure 4,
`
`QEQ —— I don't think I gave you that one on the list
`
`but I'll have to.
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`Page 14
`
`If QEQ is above its threshold voltage, and
`
`there is a potential difference between the drain —— by
`
`the way, which is the drain in this diagram?
`
`MR. PARK: Objection to form.
`
`BY MR. HOSTENY:
`
`Q.
`
`Is it above or below the —— the small arrow
`
`pointing to the right?
`
`A.
`
`I talked a little bit about this in my
`
`declaration.
`
`So, for example,
`
`footnote 1 on page 43 of my
`
`declaration, which is page 45 of 83 in the exhibit.
`
`Q.
`
`A.
`
`Yes. Okay.
`
`So one of ordinary skill in the art would
`
`understand that identification of the sources and
`
`drains transistor are dependent on the voltages
`
`provided by the transistors.
`
`This particular footnote is specific to the
`
`circuit I'm looking at
`
`in the declaration, but
`
`the
`
`same —— same answer applies to your question in
`
`Figure 4 of Lu.
`
`The source and drain depend on the
`
`potential supply to the transistor.
`
`Q.
`
`Okay.
`
`Can you tell me,
`
`in Figure 4,
`
`then,
`
`which is the source and which is the drain, or do you
`
`need to know what
`
`the potential is that's applied?
`
`MR. PARK: Objection to form.
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`THE WITNESS:
`
`Looking at the transistor
`
`Page 15
`
`QEQ --
`
`BY MR. HOSTENY:
`
`Q.
`
`A.
`
`Uh—huh.
`
`—— the labeling of the source and drain,
`
`since those terminals are interchangeable in a
`
`transistor, would depend on what
`
`the voltages are on
`
`the lines 1 and 2 that are labeled in that figure.
`
`Q.
`
`Okay. Did you discuss this Figure 4
`
`somewhere in your declaration?
`
`I
`
`think you did.
`
`You
`
`want
`
`to find the location?
`
`I'm looking at page 31,
`
`if that helps.
`
`A.
`
`What was the question?
`
`MR. HOSTENY: Why don't you read it back.
`
`(Record read by the reporter.)
`
`THE WITNESS:
`
`On page 31 of the declaration,
`
`the Lu, bottom,
`
`I reference sensing and bitline
`
`precharge and half Vdd sensing and some other text.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay.
`
`If I gather correctly,
`
`the point you
`
`were trying to make with respect to Lu is that it shows
`
`a way to get a voltage that you call Vdd divided by
`
`two?
`
`MR. PARK: Objection to form.
`
`THE WITNESS: Also in Lu, for example,
`
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`Page 16
`
`Figure 1 and the associated discussion on the first
`
`page of Lu discusses precharging half Vdd the bitlines.
`
`BY MR. HOSTENY:
`
`Q.
`
`In Figure 4, can you identify the bitlines
`
`for me.
`
`A.
`
`Yes.
`
`Q.
`
`Is —— and do you see the note,
`
`the reference
`
`in Figure 4?
`
`It refers to fee 3 --
`
`the fee 3 clock
`
`controls the equalization device.
`
`See that?
`
`MR. PARK:
`
`Where are you reading?
`
`MR. HOSTENY:
`
`The description of Figure 4,
`
`just below the drawing.
`
`THE WITNESS:
`
`YES.
`
`I see where it says fee 3
`
`clock controls the equalization device.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay.
`
`So the line --
`
`the horizontal line --
`
`well,
`
`let me back up.
`
`What are the two horizontal lines in the
`
`drawing that are connected at the equalization device
`
`on the right—hand side?
`
`A.
`
`Those lines --
`
`1 and 2 are the labels --
`
`are
`
`the bitlines.
`
`Q.
`
`Bitlines.
`
`Okay.
`
`And the 1 and 2 you're
`
`referring to —— oh,
`
`I see them. Yes.
`
`Thank you.
`
`Okay.
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`Page 17
`
`So am I right that Lu,
`
`the author of the
`
`article,
`
`is —— is describing how one of the bitlines
`
`would be at Vdd?
`
`MR. PARK: Objection to form.
`
`THE WITNESS: Yes. And the text below
`
`Figure 4, ninth line from the bottom, at the end of the
`
`previous active cycle, one bitline half is at Vdd.
`
`BY MR. HOSTENY:
`
`Q.
`
`A.
`
`O.
`
`A.
`
`Q.
`
`I'm still looking. Which column are you in?
`
`Right below Figure 4.
`
`Got it.
`
`Ninth line from the bottom.
`
`I see. Okay. Okay.
`
`So it's one bitline half is at Vdd,
`
`the other
`
`is at zero. And then the equalization device is turned
`
`on?
`
`MR. PARK: Objection to form.
`
`BY MR. HOSTENY:
`
`Q.
`
`Fee 3,
`
`that is,
`
`is used to turn on the
`
`equalization device?
`
`A.
`
`So before sensing, precharge of the bitline
`
`is initiated by switching on fee 3
`
`to turn on the
`
`equalization device QEO.
`
`Q.
`
`Okay.
`
`And --
`
`and Lu says that shorts the two
`
`bitline halves together?
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`Page 18
`
`A.
`
`Q.
`
`YES .
`
`And what he refers to as the precharge level
`
`he says is at nearly half Vdd?
`
`A.
`
`Q.
`
`Yes. That's what Lu says.
`
`And you're relying on what
`
`the Lu article
`
`says as part of your conclusion that Claim 1 of the
`
`Podlesny patent is obvious,
`
`based on Sukegawa and Lu?
`
`MR. PARK: Objection to form.
`
`THE WITNESS:
`
`Can you read back the first
`
`part of the question?
`
`MR. HOSTENY: She'll read the whole thing if
`
`you want.
`
`THE WITNESS: Okay.
`
`MR. PARK:
`
`If that doesn't work,
`
`then I'll
`
`restate it.
`
`THE WITNESS: Okay.
`
`(Record read by the reporter.)
`
`THE WITNESS:
`
`So yes,
`
`the Lu article, not
`
`just Figure 4,
`
`but
`
`the entire article in combination
`
`with Sukegawa,
`
`yields the Podlesny patent.
`
`The 130
`
`patent,
`
`obvious.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay. And —— and in Lu, you are relying on
`
`the fact that he shows a way to derive a —— what you
`
`call a precharge voltage,
`
`that is, Vdd divided by two?
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`Page 19
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`A.
`
`Yes. Again,
`
`for example,
`
`in Figure 1 of Lu,
`
`there's a voltage called Vref, and in Column 1 or the
`
`first column of Lu, on the same page,
`
`the left—hand
`
`side,
`
`the discussion of precharging to half Vdd, Vdd
`
`over two is another example precharging in Lu.
`
`Q.
`
`Okay. Okay. Claim 1 of the Podlesny patent
`
`requires a constant called K, does it not?
`
`A.
`
`Q.
`
`A.
`
`Yes.
`
`All right.
`
`In column —— or in Claim 1,
`
`the last element
`
`K is a precharging voltage factor.
`
`Q.
`
`Okay. And —— and the claim there refers to
`
`two buses.
`
`One is a differential bus, and the other is
`
`a differential data bus?
`
`A.
`
`Yes.
`
`The claim talks about a differential
`
`bus and a differential data bus.
`
`Q.
`
`And they both have to be precharged,
`
`according to Claim 1?
`
`A.
`
`The last element of Claim 1 says,
`
`"Wherein
`
`the differential bus and the differential data bus are
`
`precharged to a voltage.”
`
`O.
`
`Okay. Does --
`
`does Lu disclose K?
`
`MR. PARK: Objection to form.
`
`BY MR. HOSTENY:
`
`Q.
`
`Specifically, what —— what Claim 1 calls the
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`Page 20
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`precharging voltage factor.
`
`MR. PARK:
`
`Same objection.
`
`THE WITNESS:
`
`So the last element of Claim 1,
`
`says,
`
`"a voltage Vpr between Vdd and ground,
`
`where Vpr
`
`equals K times Vdd,
`
`and K is a precharging voltage
`
`factor,
`
`Lu discloses K being between Vdd and ground.
`
`So yes, Lu discloses this.
`
`BY MR. HOSTENY:
`
`Q. Where, specifically?
`
`MR. PARK: Objection.
`
`Form.
`
`THE WITNESS:
`
`For example,
`
`on Column 1 of Lu,
`
`the fourth --
`
`fifth line from the top of the second
`
`paragraph,
`
`the bitlines are precharged to a reference
`
`voltage approximately equal
`
`to Vdd over two,
`
`which I
`
`would take to mean a voltage between Vdd and ground,
`
`where that voltage would be K times Vdd or where K is a
`
`precharging voltage factor.
`
`BY MR. HOSTENY:
`
`Q.
`
`I'm sorry.
`
`I'm not seeing voltage factor in
`
`there.
`
`Can you be more specific?
`
`MR. PARK:
`
`Objection to form.
`
`BY MR. HOSTENY:
`
`Q. Well,
`
`let me be specific.
`
`I'll read the
`
`sentence. First column,
`
`"The bitlines are precharged
`
`to a reference voltage approximately equal
`
`to Vdd
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`
`divided by two, which can be obtained from a voltage
`
`regulator, as suggested by Foss and Harland, or by
`
`shorting two bitline halves after restoring the
`
`Page 21
`
`signal."
`
`correct?
`
`So he refers to two ways of precharging;
`
`A.
`
`In the sentence you just read, yes,
`
`the
`
`bitlines can be precharged to a voltage of
`
`approximately Vdd over two from a regulated voltage
`
`source or by shorting two bitlines together.
`
`Q.
`
`Okay. And the technique shown in Figure 4
`
`is
`
`the shorting of two bitlines together;
`
`is that right?
`
`MR. PARK: Objection to form.
`
`THE WITNESS:
`
`I believe so. Yes.
`
`BY MR. HOSTENY:
`
`O.
`
`Other than referring to the voltage regulator
`
`as suggested by Foss and Harland, and I
`
`think —— and I
`
`think he refers to a —— does he refer to a Note 3?
`
`Yes, he does.
`
`Other than referring to using a voltage
`
`regulator by —— suggested by Foss and Harland, does he
`
`otherwise describe a voltage regulator?
`
`MR. PARK: Objection to form.
`
`THE WITNESS:
`
`I don't recall if voltage
`
`regulator's mentioned in any other place in the paper.
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`Page 22
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`BY MR. HOSTENY:
`
`Q.
`
`How do you know that —— well, let's back up.
`
`In the manner shown in Figure 4,
`
`the shorting
`
`of the bitlines,
`
`is there a K, a precharged voltage --
`
`precharging voltage factor in Figure 4?
`
`MR. PARK:
`
`I'm going to object to form.
`
`THE WITNESS:
`
`In Figure 4,
`
`the bitlines are
`
`precharged is nearly half Vdd, which I would take to
`
`mean K is nearly half of Vdd.
`
`BY MR. HOSTENY:
`
`Q.
`
`Are you saying,
`
`then,
`
`that there is a
`
`precharging voltage factor in both of the two methods
`
`suggested by Lu —— that is Foss and Harland —— and by
`
`shorting?
`
`MR. PARK: Objection to form.
`
`THE WITNESS:
`
`So I'm saying that Figure 1,
`
`which, as discussed in Column 1,
`
`in the first column,
`
`in the second paragraph, under the introduction and
`
`second sentence was one of the most widely used
`
`variants to precharge the bitlines.
`
`And then it goes on to discuss pre charging
`
`the bitlines to approximately Vdd over two. And then
`
`with regard to Figure 4,
`
`the precharging is also to a
`
`voltage of nearly Vdd over two as discussed in the text
`
`underneath Figure 4 on the second page of Lu.
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`Page 23
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`BY MR. HOSTENY:
`
`Q.
`
`You used the words "nearly half Vdd."
`
`Is
`
`that correct?
`
`A.
`
`The paper uses the words "nearly half Vdd"
`
`in
`
`the third sentence from the bottom there, underneath
`
`Figure 4.
`
`Q.
`
`Do you see in Claim 1 of the Podlesny patent
`
`that there is a reference in line 16, Column 4 --
`
`there's a little typo there —— where it says the two
`
`buses are precharged to a voltage Vpr?
`
`A.
`
`I see wherein the differential bus and the
`
`differential data bus are precharged —— precharged to a
`
`voltage, Vpr. Yes.
`
`Q.
`
`Okay.
`
`Do you see a Vpr
`
`in Figure 4 of Lu?
`
`MR. PARK: Objection to form.
`
`THE WITNESS:
`
`I do not see Vpr
`
`in Figure 4.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay.
`
`Go back to Figure 1 of Lu. Does that
`
`graph show Vdd?
`
`A.
`
`It looks like —— and I'm unsure, but Vdd in
`
`Figure 1
`
`is either 10 volts or 12 volts, but
`
`the
`
`specific value of Vdd isn't listed in Figure 1.
`
`Q.
`
`Okay.
`
`Is —— is there a line which represents
`
`its value? One of those lines?
`
`A.
`
`Vdd isn't plotted in Figure 1.
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`Q.
`
`Okay. Because those are all —— those lines
`
`all repre
`
`sent voltages varying over a very short period
`
`Page 24
`
`of time;
`
`correct?
`
`MR. PARK: Objection to form.
`
`BY MR. HO
`
`STENY:
`
`Q.
`
`Well,
`
`in my world, 100 nanoseconds is pretty
`
`short.
`
`P
`
`erhaps not
`
`in yours.
`
`Sorry.
`
`Those —— that's a graph of —— of —— of
`
`voltages
`
`—— various voltages over time; right?
`
`A.
`
`Q.
`
`Yes.
`
`Okay. What's bitline floating?
`
`MR. PARK: Objection to form. And relevance.
`
`THE WITNESS:
`
`Is that term mentioned in the
`
`Lu paper
`
`some place?
`
`BY MR. HO
`
`STENY:
`
`Q.
`
`Might be. Let me back up before we answer
`
`that ques
`
`tion.
`
`When —— when you were working on your
`
`analysis,
`
`you had available to you the Podlesny patent,
`
`the Sukegawa patent,
`
`the Watanabe patent,
`
`the Lu
`
`article,
`
`and Hardee; correct?
`
`A.
`
`Q.
`
`Yes.
`
`Therefore, you were able to look, for
`
`example,
`
`at Claim 1 of the Podlesny patent and then
`
`study the
`
`other references to see if they disclosed
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`
`elements of Claim 1;
`
`correct?
`
`MR. PARK:
`
`Objection to form.
`
`Relevance.
`
`THE WITNESS:
`
`YES.
`
`I
`
`looked at those
`
`Page 25
`
`references when doing my analysis.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay. And,
`
`I mean,
`
`did you have them side by
`
`side on the same table,
`
`all available to you at the
`
`same time,
`
`in other words?
`
`A.
`
`Yes.
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`Q.
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`Okay.
`
`So you could look at Claim 1 of
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`Podlesny and see,
`
`for example,
`
`the first element,
`
`two
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`bus drivers.
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`And then could you go look at Sukegawa
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`and say,
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`Sukegawa's got
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`two bus drivers.
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`A.
`
`Yes.
`
`I identified the two bus drivers on
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`page 18 of 83 of my declaration,
`
`Exhibit 1002.
`
`Q.
`
`Okay.
`
`Why do we have four digit numbers,
`
`but
`
`whatever.
`
`Okay. And
`
`similarly,
`
`you could work your
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`way
`
`through each of the other subparagraphs of —
`
`of
`
`Claim 1 and then look at the other references --
`
`Watanabe, Sukegawa,
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`Lu,
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`or Hardee --
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`to see whether
`
`they disclosed each of those limitations as well?
`
`A.
`
`In my declaration,
`
`I have a table that
`
`discusses the disclosure of Claim 1.
`
`Q.
`
`Okay.
`
`So Claim 1 was essentially the
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`guideline of what you had to look for in the other
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`references?
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`Page 26
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`MR. PARK: Objection to form.
`
`THE WITNESS:
`
`I don't know if I would use the
`
`term "guideline," but yes,
`
`I
`
`looked at Claim 1.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay. All right.
`
`Sukegawa —— that's --
`
`well, let's go back. We didn't finish up something on
`
`Lu.
`
`I had asked you what bitline floating was,
`
`and I said it might be mentioned in Lu. And,
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`in fact,
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`it is.
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`MR. PARK:
`
`I'm sorry. Was that a question?
`
`Can I have that read back?
`
`MR. HOSTENY:
`
`I will give you the question
`
`again.
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`BY MR. HOSTENY:
`
`Q.
`
`Take your time to look at Lu, but my question
`
`is: What is bitline floating?
`
`MR. PARK: Objection. Relevance. And
`
`foundation.
`
`I'll also add scope. Outside the scope of
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`direct.
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`THE WITNESS:
`
`(Witness reviewing document.)
`
`So I see the term on the top of the last page
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`in the left—hand column.
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`So just with a very cursory
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`review of the paper related to that term,
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`I would take
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`it to mean that the sense amplifier is turned off so
`
`that the bitlines are not actively driven to Vdd and
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`Page 27
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`ground.
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`BY MR. HOSTENY:
`
`Q.
`
`Okay.
`
`In the upper bitline in Figure 4, what
`
`will make Vdd remain constant?
`
`MR. PARK:
`
`Same objections.
`
`MR. HOSTENY:
`
`Let me rephrase that.
`
`It could
`
`be better.
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`BY MR. HOSTENY:
`
`Q.
`
`Is there anything shown in Figure 4 that
`
`ensures that Vdd on the upper bitline will remain
`
`constant?
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`MR. PARK:
`
`Same objections.
`
`THE WITNESS:
`
`If the upper bitline, which is
`
`labeled "1" in the figure,
`
`is at Vdd, and the lower
`
`bitline, which is labeled "2" in the figure is at
`
`ground,
`
`then the sense amplifier consisting of
`
`transistors Q1, Q2, Q3, and Q4 will actively pull those
`
`lines 1 and 2
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`to Vdd and ground as long as the sense
`
`amplifier is active and the fee 2 switches are on.
`
`BY MR. HOSTENY:
`
`Q.
`
`A.
`
`Fee 2?
`
`I'm looking for it.
`
`Pardon me.
`
`Those switches --
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`Q.
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`I see it.
`
`I got
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`them. Okay.
`
`So the sense amplifier needs to be active and
`
`the fee 2 switches,
`
`those are Q7 and Q8,
`
`is that what
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`Page 28
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`you're saying, need to be on?
`
`A.
`
`Yes.
`
`Q.
`
`If they are not on and the sense amplifier is
`
`not active,
`
`is there anything that maintains the value
`
`of Vdd —— of the bitline above at Vdd 2 —— I'm sorry.
`
`Let me rephrase that. That's terrible.
`
`If the —— if fee 2,
`
`that is, Q7 and Q8, are
`
`not on, and the sense amplifier is not active,
`
`is there
`
`anything maintaining the value of the upper bitline at
`
`Vdd?
`
`scope.
`
`MR. PARK: Objection to form. Outside the
`
`THE WITNESS:
`
`If the bitline isn't actively
`
`driven, it will be floating.
`
`BY MR. HOSTENY:
`
`Q.
`
`How much can it float?
`
`MR. PARK: Objection to form. Outside the
`
`scope.
`
`THE WITNESS:
`
`I don't know how to answer that
`
`question.
`
`BY MR. HOSTENY:
`
`Q.
`
`Okay.
`
`How about —— how about a quality of
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`Page 29
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`life answer instead of a quantity?
`
`Is there some rough approximation you can
`
`make or is it simply not possible to tell?
`
`MR. PARK:
`
`Same objections.
`
`THE WITNESS:
`
`So in the operation of the
`
`DRAM,
`
`the bitlines are actively driven to Vdd and
`
`ground so that the data can be read out.
`
`BY MR. HOSTENY:
`
`Q.
`
`A.
`
`Uh—huh.
`
`After the data is read out,
`
`they remain --
`
`the data remains there until the next read.
`
`In other
`
`words,
`
`they remain precharged to Vdd and ground.
`
`As described in Lu, before you do another
`
`read, you shut off the sense amp,
`
`and you short the two
`
`bitlines together to precharge to Vdd over two.
`
`Then
`
`you read the data out.
`
`So long periods of time where the bitlines
`
`are floating or they change value really are not a
`
`concern in a practical circuit.
`
`Q.
`
`Can you tell me whether you agree or disagree
`
`with Lu's comment at the top of page 454 about a longer
`
`period of bitline floating being a drawback?
`
`MR. PARK: Objection to form. Outside the
`
`scope.
`
`THE WITNESS:
`
`I do agree that a longer period
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`Page 30
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`of bitline floating can be troublesome.
`
`I'll take a
`
`look on the previous page to see what specific
`
`situations where they would, perhaps, float the
`
`bitlines.
`
`I believe, again, after a cursory review,
`
`that during this time frame, which is the early to
`
`mid—80s,
`
`that NMOS DRAMs —— so NMOS means only
`
`end—channel transistors are used —— were still common.
`
`And in that situation, a lot of this discussion is
`
`geared towards NMOS DRAMs, which don't have the PMOS
`
`transistor to actively pull up the bitline to Vdd, and
`
`it's —— it clearly says in the second from the last
`
`page of Lu in the second —— third paragraph down, "In
`
`CMOS DRAMs,
`
`therefore, half Vdd bitline sensing has
`
`none of the disadvantages" --
`
`Q.
`
`Let me interrupt. Where are you reading?
`
`I'll follow you.
`
`A.
`
`Q.
`
`It's the --
`
`Oh,
`
`I see.
`
`I'm with you now.
`
`I see the
`
`paragraph.
`
`Continue.
`
`A.
`
`—— "which it has when used in NMOS DRAMs."
`
`And I believe that the disadvantages are discussed
`
`below. And, again, after a cursory review of this
`
`material,
`
`I believe that's likely related to the fact
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`Page 31
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`that in NMOS DRAMs,
`
`there isn't a PMOS device to
`
`actively drive one of the bitlines to Vdd.
`
`Q.
`
`Okay. Taking a look back at Figure 4 for a
`
`moment, let's —— let me ask you to assume the signal
`
`is
`
`present on fee 3, and the two bitlines have been
`
`shorted together; so there's a voltage which Lu says is
`
`nearly half Vdd.
`
`Under those circumstances, are those bitlines
`
`floating?
`
`MR.
`
`PARK: Objection to form.
`
`Outside the
`
`scope. And relevance.
`
`THE WITNESS:
`
`I believe what
`
`the author, Lu,
`
`is talking about when he refers to bitline floating is
`
`the time prior to a read or prior to doing a precharge
`
`where the bitlines aren't actively driven by the sense
`
`amp. We only do the precharge and short the two lines
`
`together to precharge to Vdd over two or nearly Vdd
`
`over two immediately prior to reading or sensing the
`
`DRAM memory.
`
`BY MR. HOSTENY:
`
`Q.
`
`Is there —— is there a period of time in
`
`there where the bitlines are floating --
`
`MR. PARK:
`
`Same --
`
`MR. HOSTENY:
`
`—— at nearly half Vdd?
`
`MR. PARK:
`
`Same objections.
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`THE WITNESS:
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`I wouldn't use the term
`
`Page 32
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`"floating."
`
`I would use the term,
`
`they're shorted
`
`together to precharge the bitlines to nearly half Vdd
`
`over two.
`
`So one bitline is shorted to the second
`
`bitline, and they're tied together, not floating, as
`
`what is indicated in the text where one bitline isn't
`
`tied to anything.
`
`BY MR. HOSTENY:
`
`Q.
`
`Once they are tied together and they are at
`
`nearly half Vdd,
`
`is there anything preventing a
`
`variation in nearly half Vdd?
`
`Can it vary?
`
`MR. PARK:
`
`Same objections.
`
`THE WITNESS:
`
`Immediately after precharging
`
`the bitlines,
`
`the sense amplifier is fired —— well,
`
`prior to that,
`
`the DRAM memory row is opened,
`
`information is placed on the bitlines, and the DRAM
`
`sense amps are fired to read the memory.
`
`BY MR. HOSTENY:
`
`Q.
`
`You said immediately —— I
`
`think you said
`
`immediately after they're precharged,
`
`the sense amp is
`
`activated?
`
`A.
`
`Immediately after the bits have been
`
`precharged --
`
`Q.
`
`Okay.
`
`1O
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`11
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