Case No. IPR2015-01523
`U.S. Patent No. 6,366,130
`
`Attorney Docket No.
`ELBRUS-IPR1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`______________
`
`SAMSUNG ELECTRONICS CO., LTD.
`
`Petitioner
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED
`
`Patent Owner
`
`_______________
`
`Case: IPR2015-01523
`
`U.S. Patent No. 6,366,130
`
`PATENT OWNER'S PRELIMINARY RESPONSE
`
`
`U.S. Patent No. 6,366,130
`
`Attorney Docket No.
`ELBRUS-IPR1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`______________
`
`SAMSUNG ELECTRONICS CO., LTD.
`
`Petitioner
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED
`
`Patent Owner
`
`_______________
`
`Case: IPR2015-01523
`
`U.S. Patent No. 6,366,130
`
`PATENT OWNER'S PRELIMINARY RESPONSE
`
`
`
`TABLE OF CONTENTS
`
`I. INTRODUCTION ...................................................................................
`
`A. Problem Solved by the `130 Patent ..............................................
`
`1
`
`1
`
`B. Petitioner(cid:8217)s First Count ................................................................. 3
`
`C. Petitioner(cid:8217)s Second Count ............................................................ 4
`
`D. Petitioner(cid:8217)s Third Count ...............................................................
`
`5
`
`II. BROADEST REASONABLE CLAIM CONSTRUCTION .................. 5
`
`III. THE CLAIMS OF THE `130 PATENT ARE NOT
`ANTICIPATED BY
`TERNULLO.................................................................................................
`
`A. The Prior Art Reference ..............................................................
`
`8
`
`8
`
`B. What the Prior Art Does Not Disclose .......................................
`
`10
`
`C. CLAIMS 1, 2, 3, 5 AND 6 ARE NOT ANTICIPATED BY
`TERNULLO ...........................................................................
`
`a. Claim 1 ...............................................................................
`
`11
`
`11
`
`1. Ternullo Fails to Teach "a first stage including a cross-
`coupled latch"......................................................
`
`12
`
`2. Ternullo fails to teach pre-charging two separate
`buses ...................................................................
`
`3. Ternullo fails to teach pre-charging to
`Vpr = K*Vdd .....................................................
`
`b. Claim 2 ...............................................................................
`
`c. Claim 3 ...............................................................................
`
`17
`
`24
`
`25
`
`26
`
`i
`
`
`
`d. Claim 5 .............................................................................
`
`e. Claim 6 .............................................................................
`
`D. CLAIMS 7 AND 9 OF THE `130 PATENT ARE NOT
`OBVIOUS OVER THE COMBINATION OF TERNULLO
`AND HARDEE OR TERNULLO AND SUKEGAWA .......
`
`a. Claim 7, Ternullo Combined with Hardee ........................
`
`b.. Claim 9, Ternullo Combined with Sukegawa ...................
`
`28
`
`28
`
`29
`
`29
`
`31
`
`IV. CONCLUSION .....................................................................................
`
`32
`
`ii
`
`
`
`LIST OF EXHIBITS
`
`Exhibit 2001 - Action Closing Prosecution - Reexamination Control No.
`
`95/000,657.
`
`iii
`
`
`
`I. INTRODUCTION
`
`The Petitioner Samsung has requested Inter-Partes Review of claims 1,
`
`2, 3, 5, 6, 7 and 9 of United States Patent No. 6,366,130 (the (cid:8220)`130 Patent(cid:8221)).
`
`The Petitioner asserts that Claims 1, 2, 3, 5 and 7 are anticipated under 35
`
`U.S.C. § 102 by Ternullo (U.S. Patent No. 6,052,328); that claim 7 is
`
`unpatentable under 35 U.S.C. § 103(a) over Ternullo in view of Hardee (U.S.
`
`Patent No. 6,249,469); and that claim 9 is unpatentable over Ternullo in view of
`
`Sukegawa (U.S. Patent No. 5,828,241).
`
`A. PROBLEM SOLVED BY THE `130 PATENT
`
`The `130 patent relates to a data transfer arrangement such as might be
`
`used to read a semiconductor memory device. The arrangement includes a
`
`sense amplifier with two separate pre-charged buses, a differential bus and a
`
`differential data bus. These buses operate on alternate clock phases: one bus is
`
`being pre-charged while the other is transferring data and vice versa.
`
`The data transfer arrangement operates at high speed and uses low power.
`
`This arrangement is less sensitive to deviations in voltage sources and deviation
`
`of the threshold voltages of the input transistors. This invention leads to
`
`increased transfer speed and results in circuits that are not sensitive to circuit
`
`1
`
`
`
`parameter mismatches, noise and deviations in various applied voltages. (See
`
``130 abstract and col. 1:10-55).
`
`Claim 1 of the `130 patent illustrates the invention:
`
`1. A data transfer arrangement comprising :
`two bus drivers;
`a voltage precharge source;
`a differential bus coupled to the bus drivers and to the voltage
`precharge source;
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein that output of the first stage is coupled to an input of the
`output stage;
`wherein the differential bus and the differential data bus are
`precharged to a voltage Vpr between Vdd and ground, where
`Vpr=K*Vdd, and K is a precharging voltage factor.
`(emphasis added).
`
`Emphasis has been added to the claim to show that there are two
`
`different buses named 1) the differential bus, and 2) the differential data
`
`bus; and that both of them must be pre-charged.
`
`2
`
`
`
`B. PETITIONER'S FIRST COUNT
`
`
`
`The petitioner first contends that claims 1, 2, 3, 5 and 6 are anticipated by
`
`the Ternullo reference. However this contention is fatally flawed. The
`
`Petitioner (more precisely, the Petitioner's expert) admittedly changed the
`
`wiring diagram of Ternullo Fig. 5 to produce the claim limitation of "a first
`
`stage including a cross-coupled latch" (claim 1), stating that the original Fig. 5
`
`diagram was drawn incorrectly, and that a person of ordinary skill in the art at
`
`the time of the invention would recognize this. The Petitioner re-draws the
`
`diagram according to the expert's own opinion of how it should be wired in
`
`order to create the needed claim limitation.
`
`This is not permissible. A prior art reference cannot be changed by a
`
`Petitioner to suit its particular needs. A reference stands as it is. The Petitioner
`
`states that a person of ordinary skill would recognize it is wrong, but gives no
`
`analysis of how the circuit works or fails to work if not changed, or of how a
`
`person of ordinary skill would know that it is wrong. The Petitioner also gives
`
`no explanation as to why there was no Certificate of Correction if indeed Fig. 5
`
`is wrong.
`
`The Petitioner also provides no evidence to show that its change is the
`
`correct one, or why the person of ordinary skill would have re-wired the circuit
`
`the way the Petitioner did. In fact the re-wiring was according to the
`
`3
`
`
`
`Petitioner's expert's opinion of how he believes it should be wired, a way that
`
`conveniently creates a cross-coupled latch needed for anticipation.
`
`Ternullo fails to anticipate claims 1, 2, 3, 5 and 6 at least for the reason
`
`that the limitation of a cross-coupled latch is missing.
`
`In addition, Ternullo also fails to teach or suggest that two separate buses
`
`are pre-charged. The elements the Petitioner identifies in Ternullo as buses are
`
`separated by an isolation circuit. The Petitioner(cid:8217)s references do not state or
`
`suggest that this isolation circuit connects the two buses during pre-charging.
`
`Ternullo fails to anticipate claims 1, 2, 3, 5 and 6 for the foregoing
`
`reasons.
`
`C. PETITIONER'S SECOND COUNT
`
`The Petitioner combines Ternullo with Hardee in an attempt to render
`
`claim 7 obvious. Hardee is invoked only to provide the required NMOS
`
`transistors of claim 7 since Ternullo uses PFETS and NFETS, which are a
`
`different type of transistor. Regardless of this, there can be no prima facie case
`
`of obviousness since neither Ternullo nor Hardee teaches or suggests "a first
`
`stage including a cross-coupled latch" or pre-charging two separate buses.
`
`Indeed, in a re-examination of the (cid:8216)130 patent filed on January 19, 2012
`
`(Control Number 95/000,657), the examiner considered Hardee as an
`
`4
`
`
`
`anticipatory reference and confirmed claims 1-2, 5-7 over it and found claim 12
`
`patentable over it. The examiner found that Hardee did not disclose pre-
`
`charging the differential bus and the differential data bus. A copy of the final
`
`action with the examiner(cid:8217)s decision is included with this response and
`
`incorporated by reference (Action Closing Prosecution - Inter-Partes
`
`Reexamination control no. 95/000,657, p. 5, line 5 to p. 6, line 5, Exhibit
`
`2001).
`
`D. PETITIONER'S THIRD COUNT
`
`The Petitioner combines Ternullo with Sukegawa in an attempt to render
`
`claim 9 obvious. Sukegawa is invoked to provide the limitation "where the
`
`output stage includes cross-coupled feedback". Again, there is no prima facie
`
`case of obviousness since neither Ternullo nor Sukegawa teaches or suggests "a
`
`first stage including a cross-coupled latch" or pre-charging two separate buses.
`
`II. BROADEST REASONABLE CLAIM CONSTRUCTION
`
`(cid:8220)During patent examination, the pending claims must be (cid:8216)given their
`
`broadest reasonable interpretation consistent with the specification(cid:8217) (cid:8221). M.P.E.P.
`
`§ 2111 referring to Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005). The
`
`statement has two parts: 1) broadest reasonable interpretation, and 2) consistent
`
`5
`
`
`
`with the specification. The M.P.E.P. also requires the use of the ordinary
`
`meaning of a word to a person of ordinary skill in the art unless it is otherwise
`
`defined by the specification. See M.P.E.P. § 2111.01(III). Strange or unusual
`
`meanings are not allowed unless specifically elucidated in the specification. In
`
`an inter partes review, the Board applies the same standard. Office Practice
`
`Trial Practice Guide, 77 Fed. Reg. 48,756 48, 764 (Aug. 14, 2012).
`
`The Petitioner proposes that two claim terms be construed by the Board:
`
`1) (cid:8220)latching sense amplifier(cid:8221), and 2) (cid:8220)stage(cid:8221).
`
`For (cid:8220)latching sense amplifier(cid:8221), the Petitioner wants the term to be
`
`construed to mean: (cid:8220)a circuit, including a latch, that detects and amplifies
`
`signals(cid:8221). The Petitioner has introduced two new words 1) (cid:8220)circuit(cid:8221) and 2)
`
`(cid:8220)detects(cid:8221) for no reason. There is absolutely no reason to introduce new and
`
`undefined terms. The term (cid:8220)latching sense amplifier(cid:8221) is self-explanatory to the
`
`person of ordinary skill, namely it is a sense amplifier that can latch data. Sense
`
`amplifiers are well-known in the art, and have been used since at least the late
`
`nineteen-fifties to sense low level read signals from computer memories. The
`
`function and use of sense amplifiers has not changed, merely their size, and the
`
`components used to realize them, as well as the types of memory cells they are
`
`reading.
`
`6
`
`
`
`The word (cid:8220)latching(cid:8221) itself is also well-known in the art. A person of
`
`ordinary skill in the art knows that electrical circuits that handle digital data can
`
`either pass data (unlatched), or hold data that was present when the circuit is
`
`activated or clocked (latched). For these reasons, the term (cid:8220)latching sense
`
`amplifier(cid:8221) needs no further definition and should be given its ordinary meaning.
`
`The Petitioner also states that the construction of this term should
`
`implicitly include a cross-coupled latch (Petition p. 10). However, that
`
`limitation is explicitly called for in the claims. The inclusion of implicit
`
`meanings is not allowed in claim construction. If the Petitioner thought that the
`
`term cross-coupled latch should be construed by the Board, it should have
`
`included an argument as to why.
`
`The Petitioner proposes construing the word (cid:8220)stage(cid:8221) as (cid:8220)a portion of a
`
`circuit(cid:8221). This word also has been in extremely common use in circuit design for
`
`many years. However, the Petitioner(cid:8217)s proposed construction is broader than a
`
`person of ordinary skill in the art would understand the term. A portion of a
`
`circuit could be anything from a single transistor to something with thousands
`
`of components. On the other hand, the person of ordinary skill will understand
`
`that a (cid:8220)stage(cid:8221) is a portion of a circuit that has an input, an output and some
`
`functionality. In other words, that a stage is a functional unit in a circuit and
`
`usually can be given a name such as an oscillator, a register, a latch or the like.
`
`7
`
`
`
`This term is so well understood in the art that it does not need a new
`
`definition. The term (cid:8220)stage(cid:8221) should be given its ordinary meaning.
`
`III. THE CLAIMS OF THE `130 PATENT ARE NOT ANTICIPATED BY
`TERNULLO.
`
`A. THE PRIOR ART REFERENCE
`
`The Ternullo reference is a bit sense amplifier that has both read and
`
`write capability for SDRAM memory chips. It includes a bank of Y-selected
`
`amplifiers (10-18) that are coupled into a data bus DL1, DL2 through Y-
`
`connected switches (20-28). This data bus terminates in a data line sense
`
`amplifier (32). The data line sense amplifier is coupled to a second sense
`
`amplifier (36) which is ultimately coupled to a device external pin. The two
`
`sense amplifiers are connected together with a second bus DLL1, DLL2.
`
`8
`
`
`
`During a read operation, data flows from the bit inputs on the left of Fig.
`
`1 up to the input/output pad 42 on the right of Fig. 1. During a write operation,
`
`data flows in the opposite direction.
`
`9
`
`
`
`B. WHAT THE PRIOR ART DOES NOT DISCLOSE
`
`Ternullo fails to teach pre-charging two separate buses. Dr. Baker cites
`
`Col. 8:34-42 to allegedly support such charging; however, this paragraph does
`
`not support the contention.
`
`This paragraph simply states that the bus DLL1, DLL2 can be coupled to
`
`the input/output latch lines IOLAT1, IOLAT2. What Dr. Baker misses, is that
`
`this connection occurs only on reads. It totally fails to teach or suggest that
`
`these buses are brought to a pre-charge level of Vpr = K*Vdd as required by the
`
`claims. In fact, nowhere in Ternullo can any teaching of this sort be found. As
`
`explained above, the examiner in the re-examination of the (cid:8216)130 patent
`
`confirmed claims over another prior art reference (Hardee) because it also did
`
`not disclose pre-charging of two separate buses.
`
`As to claim 3, Ternullo fails to teach or suggest PMOS and NMOS
`
`transistors. Rather, Ternullo discloses PFETs and NFETs. A person of
`
`10
`
`
`
`ordinary skill in the art knows that FET stands for Field Effect Transistor,
`
`where MOS stands for Metal Oxide Semiconductor. As will be explained,
`
`Ternullo invents entirely new types of transistors that do not exist in the real
`
`world.
`
`C. CLAIMS 1, 2, 3, 5 AND 6 ARE NOT ANTICIPATED BY
`TERNULLO.
`
`a. Claim 1
`
`Claim 1 is not anticipated by Ternullo at least because:
`
`1) Ternullo fails to teach "a first stage including a cross-coupled latch coupled
`
`to a differential data bus". The Petitioner arbitrarily changed Fig. 5 of Ternullo
`
`to create this limitation.
`
`2) Ternullo fails to teach pre-charging two separate buses: "wherein the
`
`differential bus and the differential data bus are precharge (sic) to a voltage".
`
`3) Ternullo fails to teach pre-charging to Vpr = K*Vdd. Ternullo only teaches
`
`pre-charging to some midpoint. K is a multiplier that places Vpr anywhere
`
`11
`
`
`
`between Vdd and Vss. Ternullo pre-charges to VBLR, a mid-level voltage;
`
`however, this mid-level voltage is unspecified in the Ternullo disclosure.
`
`1. Ternullo Fails to Teach "a first stage including a cross-coupled latch".
`
`The Petitioner Arbitrarily Changed The Prior Art Reference Figure to
`
`Create the Particular Claim Limitation.
`
`Dr. Baker, the Petitioner's expert, states the following on p. 28 of his
`
`expert declaration:
`
`12
`
`
`
`(Baker Declaration p. 28).
`
`13
`
`
`
`(Baker Declaration p. 29).
`
`Dr. Baker first states that a person of ordinary skill in the art at the time
`
`of the invention "would have understood" that Fig. 5 is wrong. However, he
`
`provides no analysis of why or how the person of ordinary skill in the art would
`
`have known this. He performs no analysis of how the circuit would perform as
`
`drawn, or what experiments the person of ordinary skill could have run to
`
`determine that the figure was in error. He also does not explain why there is no
`
`Certificate of Correction if indeed Fig. 5 is wrong.
`
`Dr. Baker next arbitrarily "corrects" Fig. 5 by removing the wires marked
`
`green in his page 29 figure shown above. Again, he makes no analysis of how
`
`14
`
`
`
`the person of ordinary skill in the art would have chosen those two wires and
`
`not some other wires. He states:
`
`However, Fig. 5 is a circuit diagram of a Line Latch Sense Amplifier and
`
`Supporting Circuitry (Ref. 36 in Fig. 1), while Fig. 3 is a circuit diagram of a
`
`totally different circuit, namely a Data Line Sense Amp and Supporting
`
`Circuitry (Ref. 32 in Fig. 1). The Petitioner makes no explanation of how a
`
`person of ordinary skill can use a part of Fig. 3 to determine a circuit change in
`
`Fig. 5 since Fig 5 and Fig 3 represent totally different circuits. Just because
`
`two circuits might operate "similarly to" each other does not mean they are
`
`wired the same.
`
`In any case, a prior art reference must stand on its own in an anticipation
`
`analysis. If it is wrong, it is wrong (and it is not clear that Ternullo Fig. 5 as
`
`drawn is wrong). It cannot be changed by an examiner or by a Petitioner to
`
`15
`
`
`
`make it what it is not, or to force it to teach what it does not teach. This is
`
`simply not allowed.
`
`"Anticipation requires that each and every element of the claimed
`
`invention be disclosed in a single prior art reference or embodied in a single
`
`prior art device or practice." Robert L. Harmon, Patents and the Federal
`
`Circuit, Eighth Edition, BNA Books, Washington DC., §3.2(a) citing inter alia
`
`In re Paulsen, 30 F. 3d 1475 (Fed. Cir. 1994) and In re Spada, 911 F.2d 705
`
`(Fed. Cir. 1990), emphasis added. "The corollary of the rule is that absence
`
`from the reference of any claimed element negates anticipation. id. citing
`
`Kloster Speedsteel AB v. Crucible Inc., 793 F.2d 1565 (Fed. Cir. 1986). "The
`
`identical invention must be shown in as complete detail as is contained in the
`
`patent claim." id. See, e.g., Richardson v. Suszuki Motor Co., 868 F.2d 1226
`
`(Fed. Cir. 1989).
`
`Most important, an anticipating reference must enable a person of
`
`ordinary skill in the art to make and use the claimed invention. See, Merck &
`
`Co. v. Teva Pharm. USA Inc., 347 F.3d 1367 (Fed. Cir. 2003).
`
`From this it follows that a prior art reference with a diagram or figure that
`
`is incorrect does not enable a person of ordinary skill in the art to make or used
`
`the claimed invention. The Petitioner makes the contention that Fig. 5 is
`
`incorrect as drawn (implying that it will not work, or at least that it is not a
`
`16
`
`
`
`latch). By making this contention, and stating that a change in the diagram is
`
`necessary, the Petitioner is admitting that the reference is non-enabling. Since
`
`the reference is non-enabling as to this element ("a first stage including a cross-
`
`coupled latch"), Ternullo cannot anticipate claims 1, 2, 3, 5 or 6.
`
`The Board cannot allow the Petitioner to change what is available to the
`
`public and to a person or ordinary skill in the art to suit its needs in a particular
`
`case.
`
`2. Ternullo fails to teach pre-charging two separate buses.
`
`Claim 1 requires "wherein, the differential bus and the differential data
`
`bus are precharge[d] to a voltage Vpr between Vdd and ground..."
`
`Dr. Baker, on p. 34 of his declaration presents the following figure:
`
`17
`
`
`
`According to the Petitioner, the green lines are a differential bus, the
`
`violet lines are a differential data bus, and the red box represents a voltage pre-
`
`charge source. There is a problem with this diagram: the voltage pre-charge
`
`source is only connected to what the Petitioner calls the differential bus. It is
`
`NOT connected to what the Petitioner calls the differential data bus.
`
`The following is a close up of the relevant region of this diagram:
`
`18
`
`
`
`(Part of Ternullo Fig. 5).
`
`The Petitioner states that the IOLAT1 and IOLAT2 bus, which it is
`
`calling the differential data bus, is also charged by VBLR through the isolation
`
`circuit (170). The Petitioner cites Ternullo 5:24-27, 6:21-51, 8: 34-42 and 8:45-
`
`55 to support this. However, none of these paragraphs teach that the IOLAT
`
`bus is ever pre-charged.
`
`19
`
`
`
`For example: 5:24-27 reads:
`
`This passage only states that the isolation circuit 70 (which is in a
`
`different part of the device) allows signals to pass. There is nothing about pre-
`
`charging.
`
`6:21-51 reads:
`
`20
`
`
`
`Again, there is no teaching of pre-charging the IOLAT bus.
`
`As stated above, 8:34-42 reads:
`
`21
`
`
`
`This passage is at least discussing the correct part of the circuit.
`
`However, it describes high and low signals on the IOLAT bus, but not pre-
`
`charging.
`
`Finally, 8:45-55 reads:
`
`22
`
`
`
`Again, a high or low signal transfer to the IOLAT bus is discussed, but
`
`again, no pre-charging.
`
`Furthermore, Ternullo actually describes that IOLAT1 and IOLAT2 are
`
`not pre-charged. Instead, (cid:8220)IOLAT1 and IOLAT2 were previously set by signals
`
`from the data latch lines DLL1 and DLL2(cid:8221). See 10:46-49:
`
`In short, none of the paragraphs cited by the Petitioner support the
`
`contention that both buses are pre-charged. Therefore, the Petitioner has failed
`
`to show that Ternullo anticipates claim 1 since it only teaches pre-charging one
`
`bus. For this reason, Ternullo cannot anticipate claims 1, 2, 3, 5 or 6 (i.e. it fails
`
`to anticipate independent claim 1, and cannot by law therefore anticipate any
`
`claim dependent on claim 1).
`
`23
`
`
`
`3. Ternullo fails to teach pre-charging to Vpr = K*Vdd.
`
`The `130 patent teaches that the pre-charge voltage Vpr is equal to Vdd
`
`(the rail voltage) multiplied by a constant K. It also teaches that Vpr is between
`
`ground (0 volts) and Vdd (Claim 1 and 3: 24-44). In addition, it teaches that the
`
`preferred K is 1/3 for MOS transistors (3:25). The Petitioner states that Ternullo
`
`pre-charges to a mid voltage (where K = 1/2). However, this is not supported
`
`by the Ternullo disclosure.
`
`Ternullo pre-charges to some value, called VBLR, (for example, see the
`
`dotted box 60 on the top right of Fig. 8 which shows that when it is time to pre-
`
`charge, both DL1 and DL2 are driven to the value, VBLR). However, what this
`
`voltage might be is unspecified by the disclosure. Since no specific value for
`
`VBLR is taught, it could be anything including Vdd or Vss. Moreover, a
`
`person of ordinary skill in the art knows that the desired level is not necessarily
`
`mid-level between Vdd and Vss. Rather, it is a voltage that takes an equal
`
`amount of "effort" or energy to move between the high and low voltages of the
`
`amplified SRAM voltage during a read. This, in turn, depends on the specifics
`
`of the design (it might or might not be mid-way between Vdd and Vss).
`
`Ternullo is non-enabling on this point. The disclosure simply does not
`
`teach anything about what value VBLR has.
`
`24
`
`
`
`Claim 1 requires a variable pre-charge voltage of anything between 0
`
`volts and Vdd as determined by the designer choosing a different K for a
`
`particular transistor type. Using a design variable K is not the same as saying
`
`the pre-charge voltage has a range from 0 to Vdd. Rather, the designer can
`
`choose an optimum K for a particular type of transistor.
`
`Ternullo only teaches the special case of a fixed voltage that the
`
`Petitioner says is the mid-point, and hence there is no design choice taught or
`
`suggested. As stated, Ternullo fails to teach or even suggest that the pre-charge
`
`voltage can be anything different from mid range. Ternullo fails to supply the
`
`claim limitation "Vpr = K*Vdd where K is a precharging factor". Ternullo is
`
`totally silent as to pre-charging factors.
`
`For this reason, Ternullo cannot anticipate claims 1, 2, 3, 5 or 6.
`
`b. Claim 2
`
`Claim 2 cannot be anticipated by the Ternullo reference because its
`
`parent claim 1 is not anticipated.
`
`25
`
`
`
`c. Claim 3
`Claim 3 cannot be anticipated by the Ternullo reference because its
`
`parent claim 1 is not anticipated. In addition, claim 3 calls for NMOS and
`
`PMOS transistors. Ternullo only teaches NFET and PFET transistors. The
`
`Petitioner has failed to carry its burden to show that NFET and PFET transistors
`
`anticipate NMOS and PMOS transistors. FET stands for Field Effect
`
`Transistor, while MOS stands for Metal Oxide Semiconductor or MOSFET
`
`Metal Oxide Semiconductor Field Effect Transistor. Dr. Baker's act of labeling
`
`his diagram NMOS and PMOS when the reference calls out NFETs and PFETs
`
`is insufficient since it is simply his opinion. Dr. Baker states: "One of ordinary
`
`skill in the art at the time of the alleged invention of the `130 Patent would have
`
`understood that a p-channel MOSFET was often referred to as PFET or PMOS
`
`and that an n-channel MOSFET was often referred to as NFET or NMOS.(cid:8221)
`
`However, the Petitioner has failed to provide any evidence that this is
`
`true. Therefore, this simply represents the Petitioner's expert's personal opinion,
`
`and as such, fails to carry the Petitioner's burden.
`
`More interesting is that the body connection arrows are different in the
`
`pass transistors. For example, transistors 174 and 172 have the body
`
`connection arrows going the wrong way for N transistors. The P transistors
`
`26
`
`
`
`164 and 163 have arrows backwards from transistors 178 and 176 as can be
`
`seen in the following diagram from Ternullo.
`
`(Part of Ternullo Fig. 5).
`
`It is impossible for a person of ordinary skill in the art to determine what
`
`kind of transistors these are; the transistors with backward body contact arrows
`
`are definitely not NMOS/PMOS. In fact, these are not transistors that could
`
`actually exist. So, it is impossible to know what the Ternullo reference teaches
`
`(cid:8211) The whole drawing (Fig. 5) is non-enabling. (or, alternatively, it is so full of
`
`(cid:8220)mistakes(cid:8221) that a person of ordinary skill in the art would be unsure how to
`
`correct it before actually trying to use the invention). How would the person of
`
`27
`
`
`
`ordinary skill in the art know for any particular impossible-to-build transistor
`
`whether it is the arrow that is backward and not a bubble that is superfluous or
`
`missing. In other words, there is no way for the person of ordinary skill in the
`
`art to know whether these transistors should be of type N, type P or something
`
`else without undue experimentation.
`
`d. Claim 5
`
`Claim 5 cannot be anticipated by the Ternullo reference because its
`
`parent claim 1 is not anticipated.
`
`Claim 5 requires the differential bus to be pre-charged to a voltage that is
`
`between Vdd and Vss. Ternullo's VBLR is undefined. Therefore, there is no
`
`pre-charging in the Ternullo reference according to the `130 invention.
`
`e. Claim 6
`
`Claim 6 cannot be anticipated by the Ternullo reference because its
`
`parent claim 1 is not anticipated.
`
`28
`
`
`
`D. CLAIMS 7 AND 9 OF THE `130 PATENT ARE NOT OBVIOUS
`OVER THE COMBINATION OF TERNULLO AND HARDEE OR
`TERNULLO AND SUKEGAWA.
`
`a. Claim 7, Ternullo Combined with Hardee
`
`Claim 7 requires only NMOS pull up and pull down bus drivers (no PMOS).
`
`Claim 7. The data transfer arrangement in accordance with claim 2
`wherein the active pull up and pull down bus drivers are NMOS
`transistors.
`However, claim 7 depends on claim 2 and claim 1, and to be obvious, all
`
`the limitations of these claims must be found in the cited references.
`
`In order to make out a prima facie case of obviousness, the combination
`
`of references must teach or suggest each claim element. In this case, the
`
`combination of Ternullo and Hardee fails to teach pre-charging both a
`
`differential bus and a differential data bus. The Patent Owner proved to the
`
`satisfaction of the Reexamination examiner that Hardee fails to teach or suggest
`
`this limitation . The Patent Owner has shown in this document that Ternullo
`
`also fails to teach or suggest this limitation (Action Closing Prosecution - Inter-
`
`Partes Reexamination control no. 95/000,657, p. 5, line 5 to p. 6, line 5, Exhibit
`
`2001). The Petitioner only relies on the Hardee reference for NMOS pull-up
`
`and pull-down bus drivers. Therefore, the combination of Ternullo and Hardee
`
`fails to make out a prima facie case of obviousness.
`
`29
`
`
`
`Also, the Petitioner has failed to point out why a person of ordinary skill
`
`in the art would combine Ternullo and Hardee. See KSR at 550; In re Kahn,
`
`441, F.3d 977,988 (Fed. Cir. 2006) ((cid:8220)Rejections on obviousness grounds cannot
`
`be sustained by mere conclusory statements; instead, there must be some
`
`articulated reasoning with some rational underpinning to support the legal
`
`conclusion of obviousness.(cid:8221)).
`
`The Petitioner has made no effort to show why a person of ordinary skill
`
`in the art would combine these references.
`
`The Petitioner's expert Dr. Baker states:
`40. Further, in my opinion, implementing pull up and pull down bus
`drivers using solely NMOS transistors in Ternullo is simply a design
`choice that one of ordinary skill in the art at the time of the alleged
`invention of the (cid:8217)130 Patent would have certainly understood. This
`follows from the fact that there were a small finite number of MOSFET
`configurations for implementing pull up and pull down bus drivers (e.g.,
`NMOS, PMOS, or CMOS (cid:8211) both NMOS and PMOS). In fact, this
`change would have amounted to nothing more than applying known
`techniques to improve similar devices in the same way to yield
`predictable results.
`
`Dr. Baker has given his opinion that a person of ordinary skill would only
`
`have a small finite number of choices. Dr. Baker cites MOSFET transistors, but
`
`Ternullo does not even mention MOSFETs (PMOS or NMOS) transistors.
`
`30
`
`
`
`Ternullo only discusses NFET and PFET transistors with ambiguous arrows
`
`pointing in different directions. As previously discussed, the Petitioner has not
`
`shown that these are equivalent, or that Ternullo is even enabling.
`
`b. Claim 9, Ternullo Combined with Sukegawa
`
`Claim 9 requires the output stage to include cross-coupled feedback:
`
`A data transfer arrangement of claim 1 wherein the output stage includes
`
`cross-coupled feedback.
`
`However, claim 9 depends on claim 1, and to be obvious, all the
`
`limitations of these claims must be found in the cited references.
`
`Ternullo combined with Sukegawa fails to make out a prima facie case of
`
`obviousness for the same reasons given for claim 7. The combination of
`
`references must teach or suggest each claim element. In this case, the
`
`combination of Ternullo and Sukegawa fails to teach pre-charging both a
`
`differential bus and a differential data bus. The Petitioner only cites Sukegawa
`
`to find the limitation of cross-coupled feedback. It makes no attempt to show
`
`that either reference teaches or suggests pre-charging two separate buses.
`
` Also simply "cherry picking" cross-coupled feedback from a second
`
`reference is insufficient.
`
`(cid:8220)Most inventions arise from a combination of old elements and each
`
`element may often be found in the prior art(cid:8230). However mere identification in
`
`31
`
`
`
`the prior art of each element is insufficient to defeat the patentability of the
`
`combined subject matter as a whole.(cid:8221) Kahn at 986.
`
` (Fed. Cir. 2004).
`
`IV. CONCLUSION
`
`The Ternullo reference fails to anticipate claims 1, 2, 3, 5 and 6 of the
`
``130 patent because Ternullo, as published, does not show "a first stage
`
`including a cross-coupled latch coupled to a differential data bus". A petitioner
`
`is not allowed to change a reference to suit its needs. In addition, Ternullo fails
`
`to teach pre-charging two separate buses. Finally, Ternullo is non-enabling
`
`since it creates undefined and ambiguous new transistor types with no
`
`explanation or disclosure as to their nature.
`
`The Petitioner(cid:8217)s combinations of Ternullo with Hardee (claim 7) and
`
`Ternullo with Sukegawa (claim 9) both fail to support a prima facie case of
`
`obviousness.
`
`For these reasons, the Patent Owner respectfully requests that the Board
`
`refuse to institute inter partes review of the `130 Patent.
`
`32
`
`
`
`Date: Oct. 21, 2015
`
`/clifford kraft/
`Clifford H. Kraft, Reg. No. 35,229
`320 Robin Hill Dr.
`Naperville, IL 60540
`T: 708 528-9092
`F: 630 428-0104
`
`/joseph hosteny/
`Joseph Hosteny, Reg. No. 28,020
`181 W. Madison St.
`Suite 4600
`Chicago, IL 60602
`T: 312 236-0733
`F: 312 236-3137
`
`IPR2015-001523
`
`Attorneys for the Patent Owner
`
`33
`
`
`
`CERTIFICATE OF SERVICE
`
`IPR 2015-01523
`The undersigned hereby certifies that the foregoing Patent Owner's
`
`Preliminary Statement for Inter Par
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