Paper No. ____
`Filed: June 26, 2015
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`Filed on behalf of: Samsung Electronics Co., Ltd.
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`By: Steven L. Park (stevenpark@paulhastings.com)
`Naveen Modi (naveenmodi@paulhastings.com)
`Paul Hastings LLP
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
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`
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`U.S. Patent No. 6,366,130
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`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,366,130
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`

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` Petition for Inter Partes Review – Patent No. 6,366,130
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`TABLE OF CONTENTS
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`V.
`
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 .................................. 1
`III.
`PAYMENT OF FEES UNDER 37 C.F.R. §§ 42.15 AND 42.103 ................ 2
`IV. GROUNDS FOR STANDING AND IDENTIFICATION OF
`CHALLENGE ................................................................................................ 2
`BACKGROUND ............................................................................................ 4
`A.
`The ’130 Patent .................................................................................... 4
`B.
`Prosecution History of the ’130 Patent ................................................ 6
`C.
`Reexamination History of the ’130 Patent ........................................... 7
`D.
`Prior Art Raised in This Petition .......................................................... 7
`VI. CLAIM CONSTRUCTION ........................................................................... 8
`A.
`Latching Sense Amplifier (Claims 1, 3) .............................................. 9
`B.
`Stage (Claims 1, 3, 9) ......................................................................... 10
`VII. DETAILED EXPLANATION OF UNPATENTABILITY ......................... 11
`A.
`Brief Description of the Prior Art ...................................................... 11
`Ground 1: Ternullo Anticipates Claims 1, 3, 5, and 6 ....................... 13
`B.
`1.
`Claim 1 ..................................................................................... 13
`2.
`Claim 2 ..................................................................................... 28
`3.
`Claim 3 ..................................................................................... 29
`4.
`Claim 5 ..................................................................................... 41
`5.
`Claim 6 ..................................................................................... 42
`Ground 2: Ternullo and Hardee Render Claim 7 Obvious ................ 44
`C.
`D. Ground 3: Ternullo and Sukegawa Render Claim 9 Obvious ............ 46
`VIII. STATEMENT REGARDING OTHER PETITION .................................... 49
`IX. CONCLUSION ............................................................................................. 50
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`i
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`

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` Petition for Inter Partes Review – Patent No. 6,366,130
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`TABLE OF AUTHORITIES
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` Page(s)
`
`Cases
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 46, 49
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ............................................................ 8
`
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................ 8
`
`In re Yamamoto,
`740 F.2d 1569 (Fed. Cir. 1984) ............................................................................ 8
`
`Statutes
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`35 U.S.C. §§ 102 ........................................................................................................ 1
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`35 U.S.C. § 102(a) ..................................................................................................... 3
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`35 U.S.C. §102(e) ...................................................................................................... 3
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`35 U.S.C. § 103(a) ................................................................................................. 3, 4
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`35 U.S.C. § 112 ...................................................................................................... 3, 7
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`Other Authorities
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`37 C.F.R. § 42.1(b) .................................................................................................. 50
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`37 C.F.R. § 42.8(b)(1) ................................................................................................ 1
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`37 C.F.R. § 42.8(b)(2) ................................................................................................ 1
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`77 Fed. Reg. 48,756 (Aug. 14, 2012)......................................................................... 8
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`77 Fed. Reg. 48,764 (Aug. 14, 2012)......................................................................... 8
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`Modern Dictionary of Electronics (7th ed. 1999) .................................................... 11
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`
`
`ii
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`

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`Petition for Inter Partes Review — Patent No. 6,366,130
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`Exhibit
`No.
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`LIST OF EXHIBITS
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`Description
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`U.S. Patent No. 6,366,130 (“the ’130 Patent”) to Podlesny et al.
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`1002
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`Declaration of Dr. R. Jacob Baker
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`1003
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`File History of the ’ 130 Patent
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`Excerpts from File History of the Inter Partes Reexamination of the
`’ 130 Patent
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`1005
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`U.S_ Patent No. 6,052,328 to Temullo et al.
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`1006
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`U.S. Patent No. 5,828,241 to Sukegawa
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`1007
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`U.S. Patent No. 6,249,469 to Hardee
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`1008
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`Excerpts from the Modern Dictionary of Electronics (7th ed. 1999)
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`iii
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`

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`
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`I.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner”) requests inter partes review of
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`claims 1-3, 5-7, and 9 of U.S. Patent No. 6,366,130 (“the ’130 Patent”) (Ex. 1001),
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`which Petitioner understands is assigned to Elbrus International Limited (“Patent
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`Owner”).1 This Petition shows that there is a reasonable likelihood that Petitioner
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`will prevail with respect to at least one of the challenged claims, and thus a trial
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`should be instituted. This Petition also establishes by a preponderance of the
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`evidence that the challenged claims are unpatentable under 35 U.S.C. §§ 102
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`and/or 103. These claims should be canceled.
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`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Party-in-Interest: Pursuant to 37 C.F.R. § 42.8(b)(1), Petitioner
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`identifies Samsung Electronics Co., Ltd. as the real party-in-interest.
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`Related Matters: In accordance with 37 C.F.R. § 42.8(b)(2), Petitioner
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`identifies the following related matters. Patent Owner asserted the ’130 Patent
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`against Petitioner in a patent litigation filed on July 24, 2014, in the Northern
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`District of Illinois (case no. 1:14-cv-05691), which remains pending. Patent Owner
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`also asserted the ’130 Patent against Hynix Semiconductor, Inc. and SK Hynix Inc.
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`1 Petitioner understands that the ’130 Patent is exclusively licensed to Cascades
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`Computer Innovation, LLC.
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`1
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`on June 27, 2011 in the Northern District of Illinois (case no. 1-11:cv-04356), but
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`this case was dismissed on February 6, 2014. Hynix Semiconductor Inc. sought
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`inter partes reexamination (control no. 95/000,657) on January 19, 2012, but that
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`proceeding resulted in a reexamination certificate that issued on August 4, 2014.
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`Petitioner is concurrently filing a second petition for inter partes review also
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`challenging claims 1-3, 5-7, and 9.
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`Counsel and Service Information: Lead counsel is Steven L. Park (Reg. No.
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`47,842), Paul Hastings LLP, 1170 Peachtree Street, NE, Suite 100, Atlanta, GA
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`30309, Telephone:
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`(404)
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`815-2223, Fax:
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`(404)
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`685-2223, E-mail:
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`stevenpark@paulhastings.com. Back-up counsel is Naveen Modi (Reg. No.
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`46,224), Paul Hastings LLP, 875 15th St. N.W., Washington, D.C., 20005,
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`Telephone:
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`202.551.1700,
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`Fax:
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`202.551.1705,
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`E-mail:
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`naveenmodi@paulhastings.com. Petitioner consents to electronic service
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`III. PAYMENT OF FEES UNDER 37 C.F.R. §§ 42.15 AND 42.103
`Petitioner submits the required fees with this petition. Please charge any
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`additional fees required for this proceeding to Deposit Account No. 50-2613.
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`IV. GROUNDS FOR STANDING AND IDENTIFICATION OF
`CHALLENGE
`Petitioner certifies that the ’130 Patent is available for inter partes review,
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`and that Petitioner is not barred or estopped from requesting such review of the
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`’130 Patent on the grounds identified below.
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`2
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`

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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Petitioner challenges claims 1-3, 5-7, and 9 of the ’130 Patent and requests
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`that these claims be found unpatentable and canceled in view of the following prior
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`art references: U.S. Patent No. 6,052,328 to Ternullo et al. (“Ternullo”) (Ex. 1005);
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`U.S. Patent No. 5,828,241 to Sukegawa (“Sukegawa”) (Ex. 1006); and U.S. Patent
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`No. 6,249,469 to Hardee (“Hardee”) (Ex. 1007).
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`The ’130 Patent attempts to claim priority to provisional application no.
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`60/120,531 (“the ’531 provisional application”), filed February 17, 1999. For
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`purposes of this proceeding, Petitioner has assumed that the ’130 Patent is entitled
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`to the February 17, 1999 date.2 Sukegawa issued on October 27, 1998 and is thus
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`prior art under pre-AIA 35 U.S.C. § 102(a). Ternullo and Hardee were both filed
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`prior to February 17, 1999 and issued after that date, and are therefore prior art
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`under pre-AIA 35 U.S.C. §102(e).
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`Petitioner requests cancellation of the challenged claims on the following
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`grounds:
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`Ground 1: Claims 1-3 and 5-6 are unpatentable under pre-AIA 35 U.S.C.
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`§ 102(e) as anticipated by Ternullo.
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`2 Petitioner does not concede that the ’130 Patent claims comply with 35 U.S.C.
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`§ 112 or that they are entitled to the assumed priority date. Petitioner reserves the
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`right to raise these and other issues in a district court or another forum.
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`3
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Ground 2: Claim 7 is unpatentable under pre-AIA 35 U.S.C. § 103(a) as
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`obvious over Ternullo in view of Hardee.
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`Ground 3: Claim 9 is unpatentable under pre-AIA 35 U.S.C. § 103(a) as
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`obvious over Ternullo in view of Sukegawa.
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`V. BACKGROUND
`The ’130 Patent issued from U.S. Patent Application No. 09/505,656 (“the
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`’656 application”), filed February 17, 2000, and attempts to claim priority to the
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`’531 provisional application. Ex. 1001 Title Page.
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`A. The ’130 Patent
`The ’130 Patent is purportedly directed to a data transfer scheme that
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`includes two bus drivers, a precharge circuit, two complementary bus lines, and a
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`latching sense amplifier. Ex. 1001 2:1-8; Ex. 1002, ¶ 17. Fig. 1 of the ’130 Patent
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`illustrates two bus drivers 11, 12 (consisting of transistors 20, 21, 22, and 23) and
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`two complementary bus lines 14, 15 as inputs to a latching sense amplifier 16:
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`4
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`See also, e.g., Ex. 1002, ¶ 17. According to the patent, the data transfer scheme
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`operates in two phases: a precharge phase and a data transfer phase (Ex. 1001 2:12-
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`13; Ex. 1002, ¶ 18), with the bus drivers and complementary bus lines operating in
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`opposite phases to the latching sense amplifier (Ex. 1001 2:43-44; Ex. 1002 ¶ 18).
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`In other words, when the complementary bus lines and the bus drivers are in the
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`precharge phase, the sense amplifier is in data transfer phase and vice versa. Ex.
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`1002, ¶ 18.
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`
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`The ’130 Patent includes 9 claims with claims 1 and 8 being independent
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`and claims 2-7 and 9 being dependent from claim 1. Claim 9 was added during
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`reexamination. Independent claim 1 is reproduced below:
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`1. A data transfer arrangement comprising:
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`two bus drivers;
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`a voltage precharge source;
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`a differential bus coupled to the bus drivers and to the voltage precharge
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`source; aid [sic]
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`a latching sense amplifier coupled to the differential bus;
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`wherein the latching sense amplifier comprises:
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`a first stage including a cross-coupled latch coupled to a differential
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`data bus; and
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`an output stage coupled to an output of said first stage;
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`5
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`wherein the output of the first stage is coupled to an input of the
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`output stage;
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`wherein the differential bus and the differential data bus are precharge to a
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`voltage Vpr between Vdd and ground, where Vpr = K*Vdd, and K is a
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`precharging voltage factor.
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`Prosecution History of the ’130 Patent
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`B.
`During prosecution, all claims of the ’656 application that eventually issued
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`as the ’130 Patent were initially rejected as unpatentable over prior art. Ex. 1003,
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`pp. 43-44. In response, claim 1 of the application was amended to clarify that the
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`“latching sense amplifier” comprises of a “first stage including a cross-coupled
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`latch coupled to a differential data bus” and an “output stage” coupled to the output
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`of the “first stage.” Id., p. 53. Applicants explained that the latching sense
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`amplifier disclosed by the prior art did not include two stages, whereas amended
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`claim 1 now included both a “first stage” and an “output stage” of a latching sense
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`amplifier. Id., p. 50-51. Applicants also distinguished the purported invention over
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`the cited prior art by noting the purported invention “teaches precharging the buses
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`to a specific level between ground and Vdd (Vpr = K*Vdd, where K is precharging
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`voltage factor),” rather than Vdd as taught by the prior art. Id., p. 50 (emphasis
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`added). Applicants later submitted a supplemental amendment to claim 1 to recite
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`6
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`the intermediate precharge voltage Vpr (id., p. 60-62), and a notice of allowance
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`was issued shortly thereafter (id., pp. 64-68).
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`
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`C. Reexamination History of the ’130 Patent
`As noted above, Hynix filed an inter partes reexamination, i.e., control no.
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`95/000,657 (“the ’657 proceeding”). See Ex. 1004 (excerpts from the ’657
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`proceeding). During inter partes reexamination, claims 1-3 and 5-7 were
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`confirmed. Patent Owner also submitted new claims, but all but one were rejected
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`under 35 U.S.C. § 112. Id., pp. 134-44. This one claim eventually issued as claim
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`9. Ex. 1001 Reexam Cert. 1:20-21.
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`Prior Art Raised in This Petition
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`D.
`This Petition relies on prior art that the U.S. Patent and Trademark Office
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`(“PTO”) did not have before it or did not fully consider during prosecution and
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`reexamination. None of the prior art references relied on in this Petition were cited
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`during prosecution or reexamination.3 As explained below, the prior art discussed
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`3 Hynix relied on European patent publication no. EP 0 597 231 during
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`reexamination. This European publication is related to Hardee. Hardee was,
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`however, never considered as presented herein, especially in light of the
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`accompanying expert testimony.
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`7
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`in this Petition anticipates or renders obvious the claims of the ’130 Patent,
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`especially when considered in light of the declaration of Dr. R. Jacob Baker (Ex.
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`1002).
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`VI. CLAIM CONSTRUCTION
`In an inter partes review, the Board applies the broadest reasonable
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`interpretation (“BRI”) standard to construe claim terms.4 Under the BRI standard,
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`claim terms are given their “broadest reasonable interpretation, consistent with the
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`specification.” In re Ya amoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); Office Patent
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`Trial Practice Guide, 77 Fed. Reg. 48,756, 48,764 (Aug. 14, 2012). Claim terms
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`are also “generally given their ordinary and customary meaning,” which is the
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`meaning that the term would have to a person of ordinary skill in the art.5 See In re
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`Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (quoting Phillips v.
`
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`4 Petitioner notes that the district courts apply a different claim construction
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`standard and reserves its rights to make arguments based on that standard in the
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`district court.
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`5 A person of ordinary skill in the art at the time of the alleged invention of the
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`’130 Patent would have had an undergraduate degree in Electrical Engineering or
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`equivalent and at least two to three years of experience in the design and/or
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`analysis of data transfer circuits or the equivalent. Ex. 1002, ¶ 15.
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`8
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`AWH Corp., 415 F.3d 1303, 1312, 1313 (Fed. Cir. 2005) (en banc)). Petitioner
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`proposes a construction for a few of the claim terms below and submits that the
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`remaining terms in the ’130 Patent should be given their plain and ordinary
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`meaning under the BRI standard.
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`A. Latching Sense Amplifier (Claims 1, 3)
`Claims 1 and 3 recite the term “latching sense amplifier.” For purposes of
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`this proceeding, “latching sense amplifier” should be construed to mean “a circuit,
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`including a latch, that detects and amplifies signals.” This construction is
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`consistent with the use of the term in the claims and specification of the ’130
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`Patent. Ex. 1002, ¶ 22
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`Neither the claims nor the specification explicitly define “latching sense
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`amplifier.” The ’130 Patent’s specification describes its latching sense amplifier to
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`include a latch (see, e.g., Ex. 1001 2:39-40, 2:48-50) for detecting (see, e.g., Ex.
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`1001 2:33-38, 2:64-67) and amplifying received signals (see, e.g., Ex. 1001 2:64-
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`67). See also Ex. 1002, ¶ 22. Also, latching sense amplifiers were well known at
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`the time of the alleged invention of the ’130 Patent by those skilled in the art, and
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`such individuals would have understood the term to be consistent with the
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`Petitioner’s proposed construction. Ex. 1002, ¶ 22. Indeed, Petitioner’s
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`construction is consistent with dictionary definitions of similar terms. See, e.g., Ex.
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`1008 at 679 (defining “sense amplifier” as “[a] circuit used to sense low-level
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`9
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`voltages … and to amplify these signals to the logic voltage levels of the system”);
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`see also Ex. 1002, ¶ 22.
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`The claims additionally specify what a “latching sense amplifier” has to
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`include. Ex. 1002, ¶ 22. For example, claim 1 requires that the “latching sense
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`amplifier” include both a first stage with a cross-coupled latch and an output stage.
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`See, e.g., Ex. 1001 4:8-13; Ex. 1002, ¶ 22. Accordingly, in the context of the ’130
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`Patent, the broadest reasonable interpretation of “latching sense amplifier” is “a
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`circuit, including a latch, that detects and amplifies signals,” wherein the claims
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`further define what that circuit includes. Ex. 1002, ¶ 22.
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`Stage (Claims 1, 3, 9)
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`B.
`Claims 1, 3, and 9 recite the term “stage.” For purposes of this proceeding,
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`“stage” should be construed to mean “portion of a circuit.” This construction is
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`consistent with the use of the term in the claims and specification of the ’130
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`Patent as well as dictionary definitions for the term. Ex. 1002, ¶ 23.
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`Neither the claims nor the specification explicitly define “stage.” However,
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`independent claim 1 uses the term to indicate that a latching sense amplifier
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`comprises of a “first stage” and an “output stage” and dependent claims 3 and 9
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`use the terms in context of particular circuitry found within a “first stage” and
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`“output stage” of a latching sense amplifier. See, e.g., Ex.1001 4:8-13, 4:21-23,
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`Reexam Cert. 1:20-21; Ex. 1002, ¶ 23. Claim 1 notes that the “first stage” of the
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`latching sense amplifier must include cross-coupled latch circuitry. See, e.g., Ex.
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`1001 4:8-13; Ex. 1002, ¶ 23. In claim 3, the “first stage” is described to include
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`specific transistor circuitry and clock signals. See, e.g., Ex. 1001 4:8-13; Ex. 1002,
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`¶ 23. The “output stage” of claim 9 includes circuitry for cross-coupled feedback.
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`See, e.g., Ex. 1001 Reexam Cert. 1:20-21; Ex. 1002, ¶ 23. The specification uses
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`the term “stages” once (Ex. 1001 3:4-5) and that usage is consistent with the
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`definition proposed here. Ex. 1002, ¶ 23. In addition, the Modern Dictionary of
`
`Electronics (7th ed. 1999) defines “stage” as “[a] single section of a multisection
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`circuit or device.” Ex. 1008 at 728. Accordingly, in the context of the ’130 Patent,
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`the broadest reasonable interpretation of “stage” is “portion of a circuit.”
`
`VII. DETAILED EXPLANATION OF UNPATENTABILITY
`A. Brief Description of the Prior Art
`As explained in detail below, the prior art identified and applied in this
`
`Petition discloses and/or suggests the limitations of claims 1-3, 5-7, and 9. Ex.
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`1002, ¶¶ 16, 24, 29-45. For example, Ternullo describes “a method and apparatus
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`that accomplishes a high performance, random read/write SDRAM design by
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`synchronizing the read and write operation at the data line sense amplifier.”
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`Ternullo Abstract; see also, e.g., Ex. 1002, ¶ 25. As such, Ternullo generally
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`relates to the transmission of signals in an electronic circuit. Ex. 1002, ¶ 25.
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`Ternullo sought to overcome the challenges of using the same set of lines for
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`efficient read and write operations (see, e.g., Ternullo 2:9-35), and in doing so,
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`teaches, inter alia, a “high performance write process without impacting the
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`critical read path” (id. 1:9-10). See also, e.g., Ex. 1002, ¶ 25.
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`Sukegawa describes “a type of signal transmission circuit wherein the signal
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`is amplified and transmitted by means of the positive feedback of an intermediate
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`amplifier circuit having input/output shared terminals.” Sukegawa 1:11-15; see
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`also, e.g., Ex. 1002, ¶ 26. The signal transmission circuit disclosed sought to
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`increase the signal transmission distance as well as increase the speed and lower
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`the power consumption of a transmission. Sukegawa 4:52-55; see also, e.g., Ex.
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`1002, ¶ 26. Sukegawa discloses that its signal transmission circuit comprises of “a
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`driver circuit, a receiver circuit, an equalizer circuit, and an intermediate amplifier
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`circuit.” Sukegawa 4:62-65; see also, e.g., Ex. 1002, ¶ 26. The intermediate
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`amplifier circuit relies on positive feedback to amplify the signal provided by the
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`driver circuit and transmit the amplified signal to the receiver circuit. See, e.g.,
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`Sukegawa 5:1-4; see also, e.g., Ex. 1002, ¶ 26.
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`Hardee is yet another prior art reference relating to signal transmission, and
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`in particular, “integrated circuit memories” and “sense amplifiers for use therein.”
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`See, e.g., Hardee 1:8-10; Ex. 1002, ¶ 27. Hardee introduces a sense amplifier
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`highlighted by three “salient” features:
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`(1) the connection of each sense amplifier via transistors
`or other switching devices to the power supply lines
`without directly connecting together power supply lines
`for multiple sense amplifiers;
`(2) the use of local read amplifiers;
`(3) the use of local write circuitry.
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`See Hardee 5:24-32; see also, e.g., Ex. 1002, ¶ 27.
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`All the prior art references mentioned above relate to signal transmission and
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`were motivated to improve the efficiency of such transmissions. Ex. 1002, ¶ 28. As
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`such, one of ordinary skill in the art at the time of the alleged invention of the ’130
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`Patent would have been motivated to combine the teachings of these references.
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`Ex. 1002, ¶ 28.
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`B. Ground 1: Ternullo Anticipates Claims 1, 3, 5, and 6
`Claim 1
`1.
`“A data transfer arrangement comprising:”
`i.
`Ternullo discloses a data transfer arrangement. See, e.g., Ex. 1002, ¶ 31. For
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`example, Ternullo states that its “present invention provides a method and
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`apparatus that accomplishes a high performance, random read/write SDRAM
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`design by synchronizing the read and write operations at the data line sense
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`amplifier.” Ternullo Abstract; see also, e.g., Ex. 1002, ¶ 31. In particular, Ternullo
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`teaches that “[d]uring a read operation, read data is transferred from the memory
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`cells of the device across a series of consecutive pairs of data lines to an
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`input/output port of the memory device.” Ternullo Abstract (emphasis added); see
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`also, e.g., Ex. 1002, ¶ 31.
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`A data transfer arrangement is further disclosed through “a schematic
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`diagram of the read circuitry 32A that is formed in accordance with the present
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`invention as it may be implemented as part of the data sense line sense amplifier
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`and supporting circuitry 32 (FIG. 1). The read circuitry 32A is required for
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`performing a read operation.” Ternullo 4:63-67, Figs. 1-2; see also, e.g., Ex. 1002,
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`¶ 31.
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`“two bus drivers6;”
`ii.
`Ternullo discloses two bus drivers. See, e.g., Ex. 1002, ¶ 31. For example, as
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`shown below in annotated Fig. 3 of Ternullo, transistors 91-94 and transistors 95-
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`98 serve as bus drivers:
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`6 Petitioner has used color and annotated figures throughout this Petition to
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`illustrate how the prior art discloses the various claimed features.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`See also, e.g., Ex. 1002, ¶ 31. Ternullo discloses: “read driver coupled to latch line
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`LAT2 includes PFET transistors 91 and 92 and NFET transistors 93 and 94. The
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`read driver coupled to latch line LAT1 includes PFET transistors 95 and 96 and
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`NFET transistors 97 and 98.” Ternullo 7:15-18; see also, e.g., Ex. 1002, ¶ 31. The
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`two bus drivers drive the outputs of Fig. 3 on lines DLL1 and DLL2. See, e.g.,
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`Ternullo 7:31-37 (“The read driver operates such that when the signal on the latch
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`line LAT2 is low, PFET transistor 91 is biased on, and if the signal READBM is
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`also low at that time, a high signal will be passed to the line DLL1. If the latch line
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`LAT2 is high, then the NFET transistor 94 will be biased on, and if the signal
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`READM is high, then a low signal will be passed to the line DLL1.”), 7:18-22
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`(same for LAT1); Ex. 1002, ¶ 31.
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`Petition for Inter Partes Review — Patent No. 6,366,130
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`“a voltage precharge source;”
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`Ternullo discloses a voltage precharge source. See, e.g., Ex. 1002, 1] 31. For
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`example, Fig. 5 of Ternullo, annotated below, discloses a voltage precharge source
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`VBLR:
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`See also, e.g., Ex. 1002, 1[ 31. VBLR acts as a voltage precharge source to DLLI
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`and DLL2 because prior to receiving data on lines DLLI and DLL2, these lines are
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`precharged to the midlevel voltage VBLR. See, e.g., Ternullo 8:28-32 (stating that
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`“when control signal DCLKD is high and signal DCLKN is low, NFET transistor
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`16] and PFET transistor 162 couple line DLLI to line DLL2, while NFET
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`transistors 163 and 164 and PFET transistors 165 and 166 couple the lines DLLI
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`and DLL2 to the midlevel voltage source VBL ”) (emphasis added), 10:35-40; see
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`also, e.g., Ex. 1002, 1] 31.
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`Petition for Inter Partes Review — Patent No. 6,366,130
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`iv.
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`“a differential bus coupled to the bus drivers and to
`the voltage precharge source; aid [sic]”
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`Ternullo teaches a differential bus coupled to the bus drivers and to the
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`voltage precharge source. See, e.g., Ex. 1002, 1] 31. For example, as shown below
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`in annotated Figs. 3 and 5 of Ternullo, the differential bus (i.e., lines DLL1 and
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`DLL2) is coupled to the bus drivers (transistors 91-94 and 95-98) and the voltage
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`precharge source VBLR:
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`.____
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`Bus drivers
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`Petition for Inter Partes Review — Patent No. 6,366,130
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`Voltage precharge
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`IOEQN
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`See also, e.g., Ex. 1002, 1] 31. One of ordinary skill
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`in the art would have
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`recognized at the time of the alleged invention of the ’l30 Patent that DLL1 and
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`DLL2 represent
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`the “differential bus” because a voltage differential
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`(i.e., a
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`difference in voltages between the two bus lines) can develop on these two bus
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`lines. See, e.g., Temullo 10:35-43; Ex. 1002, 1] 31. Moreover, as discussed below,
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`differential bus DLLl and DLL2 precede the isolation circuit 170 within
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`Temullo’s latching sense amplifier (see, e.g., Temullo Figs. 4-5; Ex. 1002, 1] 31),
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`and is consistent with Patent Owner’s mapping of the “differential bus” in the ’657
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`proceeding (Ex. 1002, 1] 31):
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`Ex. 1004, p. 68 (declaration of Dr. Philip Koopman submitted by Patent Owner;
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`alleged differential bus LT and LC precedes sense amplifier 16).
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`The bus drivers are coupled to the differential bus (i.e., lines DLL1 and
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`DLL2), shown in annotated Fig. 3 above, as the outputs of that figure. See, e.g.,
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`Ex. 1002, ¶ 31; Ternullo 7:13-18. The differential bus (i.e., lines DLL1 and DLL2)
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`is also coupled to the voltage precharge source VBLR because “when control
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`signal DCLKD is high and signal DCLKN is low, NFET transistor 161 and PFET
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`transistor 162 couple line DLL1 to line DLL2, while NFET transistors 163 and 164
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`and PFET transistors 165 and 166 couple the lines DLL1 and DLL2 to the
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`midlevel voltage source VBLR.” Ternullo 8:28-32 (emphasis added), 10:35-40; see
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`also, e.g., Ex. 1002, ¶ 31. The DLL1 and DLL2 indicated in Fig. 3 is the same
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`DLL1 and DLL2 indicated in Fig. 5 respectively. See, e.g., Ex. 1002, ¶ 31;
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`Ternullo Figs. 1-5.
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`v.
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`“a latching sense amplifier coupled to the differential
`bus;”
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`Temullo discloses a latching sense amplifier (shown below in purple)
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`coupled to the differential bus DLLl and DLL2. See, e.g., Ex. 1002, 1] 31; Temullo
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`Fig. 5 (annotated below).
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`IO!
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`
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`
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`_________
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`-5
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`I02
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`Latching sense
`amplifier
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`Consistent with Petitioner’s proposed construction of “latching sense amplifier,”
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`the circuitry identified above in annotated Fig. 5 of Temullo is a circuit, including
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`a latch, that detects and amplifies signals. See, e.g., Ex. 1002, 1[ 31. Input/output
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`latch 180 provides a latch that detects and amplifies the signal on DLLI and DLL2
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`received through isolation circuit 170. See, e.g., Ex. 1002, 1] 31; Temullo 7:58—8:3,
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`8:51-55, 10:46-49.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Regarding the operation of Ternullo’s latching sense amplifier, Ternullo
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`discloses that “[w]hen NFET transistor 186 is biased on by a high on control signal
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`IOEQN and when PFET transistor 181 is biased on by a low on control signal
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`IOEQ, the input/output latch 180 is turned on. Once the input/output latch 180 is
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`turned on, when a high or low signal appears on either of the lines IOLAT1 or
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`IOLAT2, the other line IOLAT1 or IOLAT2 is correspondingly driven to the
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`opposite state by the function of the latch.” Ternullo 8:48-55; see also, e.g., Ex.
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`1002, ¶ 31.
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`vi.
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`“wherein the latching sense amplifier comprises: a
`first stage including a cross-coupled latch coupled to a
`differential data bus; and”
`Ternullo teaches that the latching sense amplifier (shown below in purple)
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`includes a first stage (shown below in light blue) with a cross-coupled latch
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`coupled to a differential data bus (i.e., lines IOLAT1 and IOLAT2). See, e.g., Ex.
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`1002, ¶ 31; Ternullo Fig. 5 (annotated).
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`Petition for Inter Partes Review — Patent No. 6,366,130
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`Latching sense
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`amplifier
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`As indicated above, the circuitry identified as the first stage includes isolation
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`circuit 170 and input/output latch 180. Ex. 1002, 1] 31. Consistent with Petitioner’s
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`proposal that “stage” be construed to mean “portion of a circuit,” the elements
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`identified as the “first stage” are a portion of the latching sense amplifier circuit.
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`Ex. 1002, ‘II 31. In particular, isolation circuit 170 passes the differential voltage on
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`DLLI and DLL2 to input/output latch 180, which eventually latches and amplifies
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`the differential voltage. See, e.g., Temullo 7258-823, 8:48-55, 10:35-43; Ex. 1002, 1[
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`31.
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` Petition for Inter Partes Review – Patent No. 6,366,130
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`Input/output latch 180 is a cross-coupled latch because the output of a first
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`transistor is tied to the input of a second transistor, and the output of the second
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`transistor is tied to the input of the first transistor. Ex. 1002, ¶ 31. Annotated Fig. 5
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`of Ternullo below7 discloses the cross-coupling (see also, e.g., Ex. 1002, ¶ 31):
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`7 O