IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`HTC Corporation,
`HTC America, Inc.,
`LG Electronics, Inc.,
`Samsung Electronics, Co., Ltd., and
`Samsung Electronics America, Inc.
`PETITIONERS
`
`V.
`
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`Case IPR No: 2015-01502
`Patent No. 7,542,045
`Title: ELECTRONIC SYSTEM AND METHOD FOR DISPLAY USING A DECODER AND
`ARBITER TO SELECTIVELY ALLOW ACCESS TO A SHARED MEMORY
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. 37 C.F.R. §42.107
`
`
`
`
`

`
` 
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
`
`
`TABLE OF CONTENTS
`
`INTRODUCTION ............................................................................................... 1
`I.
`THE `045 PATENT ........................................................................................... 3
`II.
`THE PROPOSED GROUNDS ARE REDUNDANT .................................................. 4
`III.
`PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD THAT ANY
`IV.
`CHALLENGED CLAIM IS INVALID ................................................................................. 8
`A.  Rathnam (claims 1-2, 4-7, 9-10, 12-13 and 15-17) ................................................. 8 
`1. 
`Rathnam does not disclose a video decoder configured to receive a current
`video image to be decoded from the [main]/[system] memory .................................... 12 
`2. 
`Rathnam does not disclose the video decoder receiving data from the
`[main]/[system] memory corresponding to a previously decoded video image .... 19 
`3. 
`Rathnam’s VLIW CPU cannot be both the recited video decoder and the
`recited CPU ........................................................................................................................................ 23 
`4. 
`Rathnam does not disclose a microprocessor that stores non-image data in
`the [main]/[system] memory ...................................................................................................... 25 
`5. 
`Rathnam does not disclose an arbiter that controls access to the
`main/system memory ..................................................................................................................... 28 
`B. 
`Bowes and the MPEG Standard (claims 1, 4-5, 7, 10, 12, 16-17) .................. 31 
`1. 
`The MPEG Standard Was Considered During the Prosecution of the `045
`Patent .................................................................................................................................................... 31 
`2. 
`The Combination of Bowes and the MPEG Standard Does Not Disclose
`Every Element of the Challenged Claims. ............................................................................ 32 
`a. The proposed combination does not disclose the video decoder receiving
`an image to be decoded and a previously decoded image from the
`[main]/[system] memory ............................................................................. 32
`b. The proposed combination does not disclose an arbiter that controls access
`to the main/system memory ........................................................................ 37
`No Motivation to Combine Bowes and the MPEG Standard. .......................... 38 
`
`3. 
`
` 
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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` 
`
`Bowes, the MPEG Standard and Rathnam (claims 9, 15) ................................. 45 
`C. 
`D.  Bowes, the MPEG Standard and Stearns (claims 2, 6, 13) ................................ 45 
`V.
`CONCLUSION ................................................................................................ 46
`
`
`
`iii
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`
`TABLE OF AUTHORITIES
`
`Cases
`Amkor Tech., Inc. v. Tessera, Inc.,
`IPR2013-00242, 2013 WL 5653117, (Patent Tr. & App. Bd. Oct. 11, 2013) ...... 6
`
`
`Berk-Tek LLC v. Belden Tech. Inc.,
`IPR2013-00057, 2013 WL 5947699 (Patent Tr. & App. Bd. May 14, 2013) ........ 6
`
`
`C.R Bard, Inc. v. M3 Sys., Inc.,
`157 F.3d 1350 (Fed. Cir. 1998) ............................................................................ 38
`
`
`CONOPCP, Inc. v. The Procter & Gamble Co.,
`IPR2013-00505, 2014 WL 1253037 (Patent Tr. & App. Bd. Feb. 12, 2014) ........ 7
`
`
`Epistar, et al. v. Trustees Of Boston University,
`No. IPR2013-00298, Decision Not To Institute, Paper No. 18 (P.T.A.B.
`November 15, 2103) ............................................................................................. 42
`
`
`Ex Parte Avigdor Eldar,
`Appeal 2010-005611, 2012 WL 5387422 (P.T.A.B. Oct. 30, 2012) ................... 23
`
`
`Hopkins Mfg. Corp. v. Cequent Performance Prods., Inc.,
`IPR2015-00613, 2015 WL 4760586 (Patent Tr. & Ap. Bd. Aug. 7, 2015) ......... 23
`
`
`Illumina, Inc. v. Trustees of Columbia Univ.,
`No. IPR2012-00006, Paper 43 (P.T.A.B. May 10, 2013) ..................................4, 5
`
`
`In re Fine,
`837 F.2d 1071 (Fed. Cir. 1988) ............................................................... 43, 44, 45
`
`
`In re ICON Health & Fitness, Inc.
`496 F.3d 1374 (Fed. Cir. 2007) ............................................................................ 41
`
`
`In re Schreiber,
`128 F.3d 1473 (Fed. Cir. 1977) ............................................................................ 24
`
`
`
` 
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`iv
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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` 
`In re Skvorecz,
`580 F.3d 1262 (Fed. Cir. 2009) ............................................................................ 19
`
`
`In re Wilson,
`424 F.2d 1382 (CCPA 1970) ................................................................................ 30
`
`
`Karlin Tech., Inc. v. Surgical Dynamics, Inc.,
`177 F.3d 968 (Fed. Cir. 1999) .............................................................................. 29
`
`
`Kinetic Tech., Inc. v. Skyworks Solutions, Inc.,
`IPR2014-00530, 2014 WL 4925282 (Patent Tr. & App. Bd. Sep. 29, 2014) ...... 39
`
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) .............................................................................................. 37
`
`
`Liberty Mutual Ins. Co. v. Progressive Casualty Ins. Co.,
`No. CBM-2012-00003, Paper No. 8 (P.T.A.B. Oct. 25, 2012) .............................. 4
`
`
`Lorex Canada, Inc. v. E-Watch, Inc.,
`2014 WL 2507794, IPR2013-00521 (Patent Tr. & App. Bd. Feb. 13, 2014) ........ 6
`
`
`Oracle Corp. v. Clouding IP, LLC,
`IPR2013-00088, 2013 WL 5970180 (Patent Tr. & App. Bd. Jun. 13, 2013) ......... 7
`
`
`OSRAM Sylvania, Inc. v. Am Induction Techs., Inc.,
`701 F.3d 698 (Fed. Cir. 2012) .............................................................................. 43
`
`
`Richardson v. Suzuki Motor Co.,
`868 F.2d 1226 (Fed. Cir. 1989) ............................................................................ 29
`
`
`Teleflex, Inc. v. Ficos N. America Corp.,
`299 F.3d 1313 (Fed. Cir. 2002) ............................................................................ 38
`
`
`Therasense, Inc. v. Becton, Dickinson & Co.,
`593 F.3d 1325 (Fed. Cir. 2010) ............................................................................ 20
`
`
`Trintec Indus., Inc. v. Top- U.S.A. Corp.,
`295 F.3d 1292 (Fed. Cir. 2002) ............................................................................ 17
`
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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` 
`
`United States v. Adams,
`383 U.S. 39 (1966) ................................................................................................ 41
`
`
`Verdegaal Bros. v. Union Oil Co. of California,
`814 F.2d 628 (Fed. Cir. 1987) .............................................................................. 29
`
` 
`RULES
`35 U.S.C. § 314(a) ..................................................................................................... 1
`
`37 C.F.R § 42.1(b) ..................................................................................................... 4
`
`
`
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`vi
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`                              
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`TABLE OF EXHIBITS
`
`Exhibit Description
`
`DSP3210 Information Manual
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`
` 
` 
`
`Exhibit
`No.
`
`2001
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` 
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`vii
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`

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` 
`
`I.
`
`INTRODUCTION
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
`
`Owner”) respectfully requests that the Board deny the Petition for Inter Partes
`
`review (“Petition”) filed by HTC Corp., HTC America, Inc., LG Electronics,
`
`Inc., Samsung Electronics Co., Ltd., and Samsung Electronics America, Inc.
`
`(collectively, “Petitioner”) regarding certain claims of U.S. Patent No.
`
`7,542,045 (“`045 Patent”) because the Petition fails to demonstrate a reasonable
`
`likelihood that the Petitioner would prevail as to at least one of the challenged
`
`claims, as required under 35 U.S.C. § 314(a).
`
`The Petition proposes four grounds challenging claims 1, 2, 4-7, 9, 10, 12,
`
`13, and 15-17. Specifically, the Petitioner contends that the challenged claims
`
`are invalid as anticipated by Rathnam (Ground A). The Petitioner also contends
`
`that certain challenged claims are obvious in view of Bowes and the MPEG
`
`Standard (Ground B) and that certain challenged dependent claims are obvious
`
`in view of Bowes and the MPEG Standard, further in view of Rathnam (Ground
`
`C) or Stearns (Ground D).
`
`Ground A fails at least because Rathnam does not disclose all limitations
`
`of independent claims 1, 4, 5, and 12 and, therefore, does not anticipate those
`
`claims. By extension, the challenged dependent claims are also not anticipated
`
` 
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`1
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`
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`by Rathnam for at least the same reasons. Therefore, there is no reasonable
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`likelihood that the Petitioner would prevail with respect to any of the claims
`
`challenged in Ground A.
`
`Similarly, Grounds B-D fail at least because Bowes and the MPEG
`
`Standard do not disclose all limitations of independent claims 1, 4, 5, and 12.
`
`Moreover, one of ordinary skill in the art would not have been motivated to
`
`combine Bowes with the MPEG Standard because the combination would be
`
`inoperable. The weakness of Grounds B-D is further underscored by the fact
`
`that the MPEG Standard was before the Examiner during the original
`
`prosecution of the `045 Patent. At least for these reasons, Bowes and the MPEG
`
`Standard, alone or in combination, fail to disclose all limitations of independent
`
`claims 1, 4, 5, and 12 and do not render those claims obvious. By extension, the
`
`challenged dependent claims are also not obvious in view of Bowes and the
`
`MPEG Standard for at least the same reasons. Therefore, there is no reasonable
`
`likelihood that the Petitioner would prevail with respect to any of the claims
`
`challenged in Grounds B-D.
`
`The Petition should be denied because there is no reasonable likelihood
`
`that the Petitioner would prevail as to any of the challenged claims.
`
`
`
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`2
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`
`II. THE `045 PATENT
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`The `045 Patent is generally directed to sharing a memory interface
`
`between a video decoder and another device contained in an electronic system.
`
``045 Pat. [Ex. 1001], Abstract; independent claims 1, 4, 5, 12. Accordingly, the
`
`electronic system includes a bus coupleable to a main memory. Id. at claim 1.
`
`The main memory has stored therein data corresponding to video images to be
`
`decoded as well as decoded data corresponding to video images that have
`
`previously been decoded. Id. A video decoder is coupled to the bus for receiving
`
`encoded video images and for outputting data for displaying the decoded video
`
`images on a display device. Id. The decoder is configured to receive data from
`
`the main memory corresponding to at least one previously decoded video image
`
`and to a current video image to be decoded and output decoded data
`
`corresponding to a current video image to be displayed. Id. The current video
`
`image to be displayed is adapted to be stored in the main memory. Id.
`
`In addition to the video decoder, the electronic system includes another
`
`device configured to access the main memory. Id. An arbiter circuit is coupled
`
`to both the video decoder and the other device for controlling access to the main
`
`memory. Id.
`
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`3
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`III. THE PROPOSED GROUNDS ARE REDUNDANT
`
`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
`
`The Petitioner proposed two sets of grounds of rejection: Ground A using
`
`Rathnam for anticipation, and Grounds B, C, and D using Bowes as the primary
`
`reference for obviousness. Pet. at 13-56. The Petitioner’s proposed grounds
`
`have horizontal redundancy, which has been prohibited by the Board. Liberty
`
`Mutual Ins. Co. v. Progressive Casualty Ins. Co., No. CBM-2012-00003, Paper
`
`No. 8 (P.T.A.B. Oct. 25, 2012). Horizontal redundancy “involves a plurality of
`
`prior art references applied not in combination to complement each other but as
`
`distinct and separate alternatives.” Id. at 3. The Petition has horizontal
`
`redundancy because it includes grounds proposing the rejection of claims 1-2, 4-
`
`7, 9-10, 12-13, and 15-17 as i) anticipated by Rathnam; and ii) rendered obvious
`
`using Bowes as the primary reference. Pet. at 13-56.
`
`The Board has made clear that in order to ensure “the just, speedy, and
`
`inexpensive resolution of every proceeding,” it will not institute inter partes
`
`review proceedings on cumulative grounds. Illumina, Inc. v. Trustees of
`
`Columbia Univ., No. IPR2012-00006, Paper 43 (P.T.A.B. May 10, 2013) (citing
`
`37 C.F.R § 42.1(b)). Indeed, the Board has instructed parties that it will not
`
`“authorize inter partes review on certain unpatentability challenges . . . [where]
`
`the challenges appear to rely on the same prior art facts as other challenges for
`
` 
`
`4
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`

`
` 
`which inter partes review had been authorized.” Id. “In other words,
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`considering multiple rejections for the same unpatentability issue would
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`unnecessarily consume the time and resources of all parties involved.” Id.
`
`To avoid dismissal of a proposed ground of unpatentability, a petitioner
`
`must “provide a meaningful distinction between the different, redundant
`
`rejections.” Id. Where multiple references have been cited for the same facts, it
`
`is not enough for a petitioner to argue that the cited references are not identical,
`
`or to “speculate[] that in certain publications an element may be more clearly set
`
`forth in one publication rather than another.” Id. Rather, a petitioner must
`
`provide an adequate explanation as to the differences between the references
`
`and “how this difference would impact the unpatentability challenge.” Id.
`
`Petitioner acknowledges that Ground A and Grounds B-D both challenge
`
`the same claims. Pet. at 7. However, the petitioner contends that the proposed
`
`grounds are not redundant because: (1) Ground A and Grounds B-D challenge
`
`the claims under different statutory bases; and (2) Rathnam, the only reference
`
`in Ground A, addresses the claimed “decoder” in a different way than Bowes,
`
`the primary reference in Grounds B-D. Pet. at 7.
`
`That Ground A challenges the claims under a different statutory bases
`
`than Grounds B-D is not sufficient to show that the proposed grounds are not
`
` 
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`5
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`redundant. See, e.g., Lorex Canada, Inc. v. E-Watch, Inc., No. IPR2013-00521,
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`2014 WL 2507794, *11 (P.T.A.B. Feb. 13, 2014) (finding proposed anticipation
`
`grounds under §§ 102(b) and 102(e) redundant in view of an obviousness
`
`ground of rejection).
`
`Moreover, that Rathnam and Bowes address the decoder limitation in
`
`different ways is not sufficient to establish lack of redundancy. The Board has
`
`recognized that “absent some explanation as to why differences between a set of
`
`prior art references are relevant (e.g., why reference A is a stronger reference
`
`with respect to claim element X than reference B), the fact that references
`
`disclosed slightly different things does not demonstrate that asserted grounds are
`
`not cumulative to each other.” Amkor Tech., Inc. v. Tessera, Inc., No. IPR2013-
`
`00242, 2013 WL 5653117, *17 (P.T.A.B. Oct. 11, 2013) (emphasis added).
`
`Similarly, Petitioner’s conclusory statement that Rathnam and Bowes “address[]
`
`the claimed decoder” in different ways, is not sufficient to demonstrate that the
`
`grounds are not cumulative. Because the Petition makes “no meaningful
`
`distinction” between Ground A and Grounds B-D, the Patent Owner
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`respectfully submits that the proposed grounds are cumulative and redundant.
`
`See Berk-Tek LLC v. Belden Tech. Inc., No. IPR2013-00057, 2013 WL
`
`5947699, *3 (P.T.A.B. May 14, 2013) (“If petitioner makes no meaningful
`
` 
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`6
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`

`
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`distinction between certain grounds, the Board may exercise discretion by
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`acting on one or more grounds and regard the others as redundant”); Oracle
`
`Corp. v. Clouding IP, LLC, No. IPR2013-00088, 2013 WL 5970180, *3
`
`(P.T.A.B. Jun. 13, 2013) (“[I]n the absence of the Petitioner identifying
`
`meaningful distinctions in terms of relative strengths and weaknesses of the
`
`different prior art references, it is within the discretion of the Board to conclude
`
`that even with different facts in different grounds, multiple grounds may
`
`nevertheless be redundant”) (emphasis added); CONOPCP, Inc. v. The Procter
`
`& Gamble Co., No. IPR2013-00505, 2014 WL 1253037, *10 (P.T.A.B. Feb. 12,
`
`2014) (finding the grounds redundant where petitioner did not identify
`
`“strengths or weaknesses in the prior art disclosures as they relate to the
`
`limitations of those claims”) (emphasis added).
`
`The Petitioner failed to explain how Bowes differs from Rathnam or how
`
`any consideration of the grounds that use Bowes as the primary reference for
`
`claims 1-2, 4-7, 9-10, 12-13, and 15-17 would impact these proceedings
`
`differently than a consideration of the ground that uses Rathnam as the sole
`
`reference. See, e.g., id. The Petitioner also failed to explain why the primary
`
`reliance on Bowes for these claims may be the stronger assertion as applied in
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`7
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`certain instances and why the reliance solely on Rathnam may be the stronger
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`assertion in other instances. See Pet. at 13-56.
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`That is, nothing in the Petitioner’s analysis of the claims suggests that the
`
`grounds using Bowes and the secondary references would (or even could) be
`
`more determinative of an outcome of these proceedings than the ground using
`
`Rathnam as the sole reference. Id. Instead, all the Petitioner has done is to
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`propose redundant grounds of rejections, and request institution of a patent trial
`
`on all proposed rejections. Id. As indicated above, the Board has consistently
`
`held that such a request will not suffice to preclude dismissal of proposed
`
`challenges on grounds of redundancy.
`
`Accordingly, the Petitioner’s proposed grounds of unpatentability using
`
`Bowes with secondary references (i.e., Grounds B, C, and D) are redundant over
`
`the proposed ground of unpatentability using Rathnam as the sole reference (i.e.,
`
`Ground A). For this reason alone, the Board should deny Grounds B, C, and D
`
`as redundant.
`
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD THAT
`ANY CHALLENGED CLAIM IS INVALID
`
`
`A. Rathnam (claims 1-2, 4-7, 9-10, 12-13 and 15-17)
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`8
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`Fundamentally, Rathnam discloses nothing more than the very same
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` 
`
`system identified in the `045 Patent as prior art. In describing the background of
`
`the invention, the `045 Patent notes that a typical decoder such as an MPEG
`
`decoder (10) contained a video/audio decoding circuit (12/14), a microcontroller
`
`(16), and a memory interface (18) coupled to a dedicated memory (22). `045
`
`Pat. [Ex. 1001], 2:21-43. The `045 Patent then highlights the disadvantages of
`
`this prior art system:
`
`A typical MPEG decoder 10 requires 16 Mbits of memory to
`operate in the Main Profile at Main Level mode (MP at ML). This
`typically means that the decoder requires a 2 Mbyte memory.
`Memory 22 is dedicated to the MPEG decoder 10 and increases the
`price of adding a decoder 10 to the electronic system. In current
`technology, the cost of this additional dedicated memory 22 can be
`a significant percentage of the cost of the decoder.
`
`Id. at 2:43-51. Figure 1a of the `045 Patent depicts this prior art configuration
`
`and is reproduced below side by side with Figure 1 of Rathnam.
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`
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`Like the prior art system discussed in the `045 Patent, Figure 1 of
`
`Rathnam depicts a block diagram of the TM-1 multimedia processor which
`
`“consists of the TM-1 microprocessor itself, a block of synchronous DRAM
`
`(SDRAM), and minimal external circuitry to interface to the incoming and/or
`
`outgoing multimedia data streams.” Rathnam [Ex. 1005], at 13. In a “typical
`
`mode of operation,” the TM-1 described in Rathnam “serve[s] as a video-
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`decompression engine on a PCI card in a PC.” Id. at 14. In fact, the memory size
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`of TM-1’s SDRAM is the same as the memory size of the dedicated memory of
`
`prior art decoders disclosed in the `045 Patent. Compare Rathnam [Ex. 1005] at
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`15 (“TM-1’s DRAM memory size can range from 2Mbytes to 64 Mbytes”);
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`10
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``045 Pat. [Ex. 1001], 2:46-49 (“This typically means that the decoder requires a
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`2 Mbyte memory. Memory 22 is dedicated to the MPEG decoder …”).
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`Accordingly, Rathnam discloses the very same configuration identified in
`
`the `045 Patent as prior art and suffers from the same drawbacks. In fact, the
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``045 Patent is directed to eliminating the SDRAM of Rathnam – i.e., the
`
`decoder’s dedicated memory. See `045 Pat., 5:47-51 (“An advantage of the
`
`present invention is the significant cost reduction due to the fact that the video
`
`and/or audio decompression and/or compression device does not need its own
`
`dedicated memory but can share a memory with another device and still operate
`
`in real time”).
`
`The weakness in Petitioner’s attempt to analogize the TM-1 “multimedia
`
`processor” of Rathnam to the computer architecture claimed in the `045 Patent
`
`is further evident from a closer scrutiny of Rathnam. For instance, the Petitioner
`
`identifies Rathnam’s VLIW CPU as corresponding to the CPU of the system
`
`disclosed in the `045 Patent. See, e.g., Pet. at 19. However, Rathnam explicitly
`
`states that the VLIW CPU of the TM-1 multimedia processor cannot operate as
`
`the general purpose CPU of a computer system. Rathnam [Ex. 1005] at 15
`
`(“Although the processor core runs a tiny real-time operating system to
`
`coordinate all activities in the TM-1 system, the processor core is not intended
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`11
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`for true general-purpose use as the only CPU in a computer system. For
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`example, the processor core does not implement virtual memory address
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`translation, an essential feature in a general-purpose computer system.”).
`
`A comparison of the limitations of the challenged claims with the
`
`disclosure of Rathnam as discussed below underscores the fact that Rathnam
`
`does not disclose the improved configuration of the `045 Patent and is instead,
`
`directed to what the `045 Patent identifies as the prior art. In particular,
`
`Rathnam does not anticipate independent claims 1, 4, 5, and 12 because it fails
`
`to disclose at least five limitations of those claims.
`
`1. Rathnam does not disclose a video decoder configured to
`receive a current video image to be decoded from the
`[main]/[system] memory
`
`Independent claims 1 and 4 recite “a video decoder … configured to
`
`receive data from the main memory corresponding to … a current video image
`
`to be decoded.” Similarly, independent claim 5 recites a “video decoder
`
`configured to receive data from the system memory corresponding to … a
`
`current image to be decoded” and independent claim 12 recites a “decoder
`
`configured to receive data from the memory corresponding … to a current
`
`image to be decoded.” Accordingly, all independent claims require that the
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`12
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`decoder be configured to receive an image to be decoded from the
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`[main]/[system] memory. Rathnam does not disclose this limitation.
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`The Petitioner alleges that Rathnam’s SDRAM corresponds to the
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`“[main]/[system] memory” recited in independent claims 1, 4, 5, and 12 (Pet. at
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`14, 22, 26, 29) and that Rathnam’s VLD coprocessor and VLIW CPU, working
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`in tandem, correspond to the “video decoder” recited in those claims (Pet. at 16,
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`24, 26, 30). Even assuming that the Petitioner has correctly identified these
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`components (which the Patent Owner does not concede), the Petitioner still fails
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`to identify, and Rathnam does not disclose, that the video decoder (i.e.,
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`allegedly the “VLD coprocessor and VLIW CPU, working in tandem”) is
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`configured to receive an image to be decoded from the [main]/[system] memory
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`(i.e., allegedly the “SDRAM”).
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`At best, Rathnam only discloses a video decoder receiving an image to be
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`decoded over the PCI bus, not from the SDRAM. Although Rathnam references
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`the MPEG multimedia standards, it is silent regarding whether and how the
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`system described in Rathnam decodes images according to those standards. The
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`only passage in Rathnam that discusses the process for decompressing images is
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`the following:
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`13
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
`
`Video decompression begins when the PC operating system
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`hands the TM-1 a pointer to compressed video data in the PC’s
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`memory (the details of the communication protocol are typically
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`handled by a software driver installed in the PC’s operating
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`system).
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`The TM-1 CPU fetches data from the compressed video
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`stream via the PCI bus, decompresses frames from the video
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`stream, and places them into local SDRAM. Decompression may be
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`aided by the VLD (variable-length decoder) unit, which implements
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`Huffman decoding and is controlled by the TM-1 CPU.
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`Rathnam [Ex. 1005] at 14, Sec. 3.1 (emphasis added). According to this
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`passage, images to be decoded are received by the CPU (part of the alleged
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`video decoder) from the PCI bus, not from the SDRAM. As illustrated in the
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`figure below, the PCI bus and the SDRAM are separate, distinct components:
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`14
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
`
`
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`The images are placed in the SDRAM only after they are decompressed
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`by the VLIW CPU and the VLD Coprocessor (i.e., the alleged video decoder).
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`This is the opposite of what is claimed, namely, that an image to be decoded be
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`retrieved from the [main]/[system] memory (i.e., alleged the “SDRAM”).
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`The Petitioner’s argument to the contrary improperly conflates two
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`separate sections in Rathnam -- “Video Decompression in a PC” and “Video
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`Compression.”
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`15
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`Rathnam’s Section 3.1 -- “Video Decompression in a PC” -- specifically
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` 
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`describes that compressed images that are to be decompressed come from the
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`PC’s memory via the PCI bus, not from the SDRAM:
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`Video decompression begins when the PC operating system
`hands the TM-1 a pointer to compressed video data in the PC’s
`memory (the details of the communication protocol are typically
`handled by a software driver installed in the PC’s operating
`system).
`The TM-1 CPU fetches data from the compressed video
`stream via the PCI bus, decompresses frames from the video
`stream, and places them into local SDRAM. Decompression may be
`aided by the VLD (variable-length decoder) unit, which implements
`Huffman decoding and is controlled by the TM-1 CPU.
`When a frame is ready for display, the TM-1 CPU gives the
`ICP (image coprocessor) a display command. The ICP then
`autonomously fetches the decompressed frame data from SDRAM.
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`Rathnam [Ex. 1005] at 14, Sec. 3.1 (emphasis added). Accordingly, in
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`Rathnam’s Video Decompression, decompressed images are stored in the
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`SDRAM.
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`In contrast, Rathnam’s section 3.2 -- “Video Compression” -- does
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`describe storing compressed image data in the SDRAM, but that compressed
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`image data is never decompressed by the TM-1, much less decompressed by the
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`CPU and VLD Coprocessor (i.e., the alleged video decoder):
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`in video
`is
`for TM-1
`typical application
`Another
`compression. In this case, uncompressed video is usually supplied
`directly to the TM-1 system via the video-in-unit. … The video-in
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`16
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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` 
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`unit takes care of sampling the data from the camera chip and
`demultiplexing the raw video to SDRAM in three separate areas,
`one each for Y, U, and V.
`When a complete video frame has been read from the camera
`chip by the video-in unit, it interrupts the TM-1 CPU. The CPU
`compresses the video data (using a set of powerful data-parallel
`operations) … and writes the compressed data to a separate area of
`SDRAM.
`The compressed video data can now be disposed of in any of
`several ways. It can be sent to a host system over the PCI bus for
`archival on local mass storage, or the host can transfer the
`compressed video over a network, such as ISDN. The data can also
`be sent to a remote system using the integrated V.34 interface to
`create, for example, video phone or video conferencing system.
`Rathnam [Ex. 1005] at 14, Sec. 3.2 (emphasis added). Rathnam discloses only
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`two options for disposing of the compressed image data stored in the SDRAM:
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`(1) sending it to a host system over the PCI bus (either for archival on a local
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`mass storage, or for transfer by the host over a network, such as ISDN); and (2)
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`sending it to a remote system using the integrated V.34 interface. Neither of
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`these options decompresses the image data. In fact, the TM-1 does not use the
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`VLIW CPU or the VLD Coprocessor (i.e., alleged video decoder) at all when
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`disposing of compressed images stored in the SDRAM. As shown below, both
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`the PCI bus and the V.34 interface (in red) are separate, distinct components
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`from both the VLIW CPU and the VLD Coprocessor (in blue):
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`17
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
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`
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`Rathnam [Ex. 1005] at 12 (emphasis added).
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`Moreover, even Petitioner cannot identify any part of Rathnam that
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`directly discloses a video decoder configured to receive a current video image to
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`be decoded from the [main]/[system] memory. Rather, Petitioner argues that
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`somehow “Rathnam’s decoder must receive data via the bus from the SDRAM
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`(i.e., main memory) corresponding . . . to a current image to be decoded.” Pet.
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`at 18. To the extent such an allegation is an implied argument for inherent
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`anticipation, it is improper. Inherent anticipation “requires that the missing
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`descriptive material [be] necessarily present, not merely probably or possibly
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`present, in the prior art.” Trintec Indus., Inc. v. Top- U.S.A. Corp., 295 F.3d
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`18
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`1292, 1295 (Fed. Cir. 2002) (internal citation omitted) (emphasis added). It is
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`IPR2015-01502
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
`
`not necessary for an image to be decoded in Rathnam to be stored in the
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`SDRAM.1 In fact, the opposite is true. Rathnam specifically discloses that the
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`images to be decoded by the alleged video decoder are received from the PCI
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`bus, not from the SDRAM (i.e., alleged [main]/[system] memory). Rathnam
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`[Ex.1005] at 14.
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`Rathnam fails to disclose, expressly or inherently, a decoder that receives
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`an image to be decoded from the SDRAM (i.e., alleged [main]/[system]
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`memory).
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`2. Rathnam does not disclose the video decoder receiving data
`from
`the
`[main]/[system] memory corresponding
`to a
`previousl