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`'PCI System"
`Architecture-
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`Third Edition
`
`MINDSHARE, INC.
`
`TOM SHANLEY
`
`_
`AND
`_
`DON ANDERSON
`
`a e o e I v a D
`
`JAN-2 9 1335
`
`gasses assess
`
`A
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`YY
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`Addison-Wesley Publishing Company
`Reading, Massachusetts 0 Menlo Park, California ' New York
`
`Don Mills, Ontario 0 Wokingham, England 0 Amsterdam
`
`Bonn 0 Sydney 0 Singapore 0 Tokyo 0 Madrid - San Juan
`Paris 0 Seoul 0 Milan 0 Mexico City ' Taipei
`
`Page 1 of 235
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`HTC-LG-SAMSUNG EXHIBIT 1019
`
`

`

`Many of the designations used by manufacturers and sellers to distinguish their
`products are claimed as trademarks. Where those designations appear in this book,
`and Addison-Wesley was aware of a trademark claim, the designations have been
`printed in initial capital letters or all capital letters.
`The authors and publishers have taken care in preparation of this book, but make no
`expressed or implied warranty of any kind and assume no responsibility for errors or
`omissions. No liability is assumed for incidental or consequential: damages in
`connection with or arising out of the use of the information or programs contained
`herein.
`
`Library of Congress Cataloging-in-Publication Data
`
`ISBN: 0-201-40993-3
`
`Copyright © 1995 by MindShare, Inc.
`All rights reserved. No part of this publication may be reproduced, stored in a
`retrieval system, or transmitted, in any form or by any means, electronic, mechanical,
`photocopying, recording, or otherwise, without the prior written permission of the .
`publisher. Printed in the United States of America. Published simultaneOusly in
`Canada.
`'
`
`Sponsoring Editor: Keith Woilman
`Project Manager: Eleanor McCarthy
`Production Coordinator: Lora L. Ryan
`Cover design: Barbara T. Atkinson
`Set in 10 point Palatine by MindShare, Inc.
`
`1 2 3 4 5 6 '7 8 9 -MA- 9998979695
`First printing, February 1995
`Addison-Wesley books are available for bull: purchases by corporations, institutions,
`and other organizations. For more information please contact the CorporatE,
`Government, and Special Sales Department at (800) 238—9682.
`
`Page 2 of 235
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`

`

`To Nancy and Sheryl, two very understanding ladies.
`
`
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`Page 3 of 235
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`

`

`Contents
`
`Contents
`
`
`
` _ Aclgloivledgments ....... __ ......_xxx
`
`About This Book
`
`The MindShare Architecture Series ................................................................................ 1
`
`Organization of This Book ............................................................................................... 2
`! Who this Book is For ......................................................................................................... 2
`Prerequisite Knowledge.................................................................................................... 3
`Object Size Designations .........................................................................................I. ........ 3
`Documentation Conventions ................................ 3
`Hex Notation ................................................................................................................ 3
`
`Binary Notation ............................................................................................................ 3
`Decimal Notation ......................................................................................................... 4
`
`Signal Name Representation.
`... 4
`Identification of Bit Fields (logicalgroupsofbitsor Signals) ................................... 4
`We Want Your Feedback ................................................................................................... 4
`Bulletin Board ............................................................................................................... 5
`Mailing'Address..........; ................................................................................................ 5
`
`Part I: Introduction to the Local Bus Concept
`
`i
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`CHAPTER 1: The Problem
`Block-Oriented Devices .'................................................................................................... 9
`Graphics Interface Performance Requirements ......................................................... 9
`SCSI Performance Requirements ................................................................................ 10
`Network Adapter Performance Requirements................................................; ......... 10
`X—Bus Device Performance Constraints .....................................................................' 10
`
`Expansion Bus Transfer Rate Limitations ...................................................................... 13
`ISA Expansion Bus ....................................................................................................... 13
`EISA Expansion Bus ...................................................................'.................................. 13
`Micro Channel Architecture Expansion Bus .............................................................. 13
`Teleconferencing Performance Requirements ............................................................... 14
`—_-U_ul——m——
`
` Graphics Accelerators: Before Local Bus ........................................................................ 19
`
`CHAPTER 2: Solutions, VESA and PCI
`‘ Local Bus Concept.............................................................................................................. 20
`‘
`Buffered Approach....................................................................................................... 22
`
`‘
`
`Direct-ConnectApproach...... 20
`
`Workstation Approach ................................................................................................ 24
`
`W '
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`M V
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`ESA VL Bus Solution .................................................................-..............................
`Logic Cost ...............................................,...............................................................
`Performance ............................................................................................................
`Longev1ty
`..................
`Teleconferencing Support.....................................................................................
`Electrical—hiteg'rity.'..............;.............-............= ............................_.........
`Add-in Connectors ................................................................................................
`Auto—Configuration...............................................................................................
`Revision 2.0 VL Specification ...............................................................................
`PCI Bus Solution .........................
`..........................................
`Market Niche for PCI and VESA VL........................................................................
`PCI Device .............................................................................................................
`Specifications Book is Based'on ...........................................................................
`Obtaining PCI Bus Specification(s) ......................................................................
`Part IlziReVision 2.1 Essentials
`________/
`CHAPTER 3: Intro to PCI Bus Operation
`Burst Transfer.............................................................................................................
`Initiator, Target and Agents......................................................................................
`Single vs. Multi-Function PCI Devices ...................................................................
`PCI Bus Clock.............................................................................................................
`Address Phase ...................L........................................................................................
`Claiming theTransaction ................
`Data Phase(s) .............................................................................................................
`Transaction Duration................................................................................................
`Transaction Completion and Return of Bus to Idle State
`”Green" Machine ......................................................................................................
`CHAPTER 4: Intro to Reflected-Wave Switching
`Each Trace Is a Transmission Line .........................................................................
`Old Method: Incident-Wave Switching.................................................................
`PCI Method: Reflected-Wave Switching ..............................................................
`PCI Timing Characteristics .....................................................................................
`Introduction ........................................................................................................
`CLK Signal ......................'....................................................................................
`Output Timing....................................................................................................
`Input Timing .......................................................................................................
`RST#/ REQ64# Timing .........L.............................................................................
`Slower Clock Permits Longer Bus .........................................................................
`
`/
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`Contents
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`
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`
`CHAPTER 5: The Functional Signal Groups
`Introduction.... ...................................... ..........................
`.......................................
`
`...... 53
`
`System Signals ..... ................................... ........................................ . .................................. 56
`_.-PCIC10cl¢Signal_(CLK)m ..................".n"........m.n..n,.W,,,._.........."(.m....,5& A _
`CLKRUN# Signal ......................................................................................................... 57
`General .................. 57
`
`A
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`.7
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`Reset Signal (RST#) ...................................................................................................... 58
`Address/Data Bus.....-..... .. ......
`................ .............................................. ........................ 53
`
`62
`Preventing Excessive Current Drain............................................................................
`Transaction Control Signals .r................................. ....................................... . .................. 63
`Arbitration Signals .. ......................... ........................... . ............................................... ...... 64
`Interrupt Request Signals ..... .............. . .........
`...................................... ........................... 65
`Error Reporting Slgnals ...................................................................... . ............. 65
`Data Parity Error .......................................................................................................... 65
`System Error ................................................................................................................. 66
`Cache Support (Snoop Result) Signals .......................................................................
`6'7
`64-bit Extension Signals ...........................................
`................................................... 68
`Resource Locking ....... ........................................................................................................ 69
`JTAGfBoundary Scan Signals ..................................
`.........................._........................... '70
`Interrupt Request Lines ........
`........... . ........................................................
`..........
`71
`Sideband Signals ......
`...............‘................................................................................ '71
`Signal Types
`..............
`.......... . ...................................................................................... 71
`Central Resource Functions .............................................................................................. 72
`Subtract-ive Decode ........................................................... . .....
`............................... ....... 73
`
`Background ................................................................................................................... 73
`Tuning Subtractive Decoder........................................................................................ 74
`Reading Timing Diagrams ................................................................................................ 75
`
`
`CHAPTER 6: PCI Bus Arbitration
`Arbiter .............. . ..............
`.............................................................................................. '77
`Arbitration Algorithm..............................................
`..................................................... 79
`Example Arbiter with Fairness ................... . ..................
`............................ . ............... 80
`Master Wishes To Perform More Than One Transaction ............................................. 82
`Hidden Bus Arbitration ................
`............................................................................... 82
`
`Bus Parking......................................................................................................................... 82
`Request/Grant Timing..........................
`...................
`.......................................... 84
`Example of Arbitration Between Two Masters ............................
`.............. . ...........
`85
`3115 Access Latency ............................................................................................................ 89
`Master Latency Timer: Prevents Master From Monopolizing Bus .......................... 91
`Location and Purpose of Master Latency Timer................................................. 91
`
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`PCI System Architecture
`
`How LT Works ...................................................................................................... 91
`Is Implementation of LT Register Mandatory?................................................... 92
`Can LT Value Be Hardwired (read-only)?‘.........................
`92
`How Does Configuration Software Determine Timeslice To
`Be Allocated To Master? ..................................................................................... 92
`Treatment of Memory Write and Invalidate Command .................................... 92
`Limit on Master’s Latency .................................................................................... 93
`Preventing Target From MonopolizingBus 93
`General ................................................................................................................... 93
`Target Latency on First Data Phase ..................................................................... 95
`Options for Achieving Maximum 16 Clock Latency .......................................... 95
`Different Master Attempts Access To Device With
`Previously—Latched Request ............................................................................... 97
`Special Cycle Monitoring While Processing Request .......................,.................. 97
`Delayed Request and Delayed Completion ........................................................ 97
`Handling Multiple Data Phases ........................................................................... 97
`Master or Target Abort Handling ........................................................................ 97
`Commands That Can Use Delayed Transactions ............................................... 98
`Delayed Read Prefetch .......................................................................................... 98
`Request Queuing and Ordering Rules ................................................................. 98
`Locking, Delayed Transactions and Posted Writes ............................................ 103
`Fast Back-to-BackTransactions .................. 103
`Decision to Implement Fast Back-to-Back Capability................................. 106
`Scenario One: Master Guarantees Lack of Contention ............................................. 106
`How Collision Avoided On Signals Driven By Master...................................... 106
`How Collision Avoided On Signals Driven By Target....................................... 107
`How Targets Recognize New Transaction HasBegun 108
`Fast Back-to-Back and Master Abort ................................................................... 108
`Scenario Two: Targets Guarantee Lack of Contention.............................................. 110
`State of REQ# and GNT# During RST# .......................................................................... 111
`Pullups 0n REQ# From Add-In Connectors .................................................................. 112
`Broken Master ...................................................................................... -. ............................. 112
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`M C
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`HAPTER 7: The Commands
`Introduction ........................................................................................................................ 113
`Interrupt Acknowledge Command.................................................................................. 114
`Introduction .................................................................................................................. 114
`Background .................. 114
`Host/PCI Bridge Handling of Interrupt Acknowledge Sequence...
`...
`"115
`PCI Interrupt Acknowledge Transaction ................................................................... 116
`Special Cycle Command ................................................................................................... 119
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`General .......................................................................................................................... 119
`Special Cycle Generation ............................................................................................. 121
`Special CycleTransaction ........ 121
`Single-Data Phase Special Cycle Transaction...................................................... 121
`Multiple Data Phase Special Cycle Transaction .................................................. 122
`110 Read and Write Commands ....................................................................................... 124
`
`...........'..............124
`' AccessingMemory“ ...............'
`Reading Memory .......................................................................................................... 125
`Memory Read Command ..................................................................................... 125
`Memory Read Line Command.......................................... 125
`Memory Read Multiple Command ...................................................................... 125
`Writing Memory........................................................................................................... 126
`Memory Write Command .................................................................................... 126
`Memory Write and Invalidate Command ........................................................... 126
`Problem ........................................................................................................... 126
`Description of Memory Write and Invalidate Command ........................... 127
`More Information On Memory Transfers ................................................................... 127
`Configuration Read and Write-Commands .................................................................... 128
`DualmAddress Cycle........................................................................................................... 128
`Reserved Bus Commands ................................................................................................. 128
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`W C
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`HAPTER 8: The Read and Write Transfers
`Some Basic Rules ............................................................................................................... 129
`Parity.................................................................................................................................... 130
`Read Transaction................................................................................................................ 130
`Description.................................................................................................................... 130
`Treatment of Byte Enables During Read or Write ..................................................... 134
`Byte Enable Settings May Vary from Data Phase to Data Phase ....................... 134
`Data Phase with No Byte Enables Asserted ........................................................ 135
`Target with Limited Byte Enable Support........................................................... 136
`Rule for Sampling of Byte Enables ....................................................................... 136
`Ignore Byte Enables During Line Read................................................................ 136
`Prefetching ............................................................................................................. 137
`Performance During Read Transactions .................................................................... 137
`Write Transaction............................................................................................................... 139
`Description.................................................................................................................... 139
`Performance During Write Transactions ................................................................... 144
`Posted-Write Buffer ..................................................................................................... 146
`General ................................................................................................................... 146
`Combining.............................................................................................................. 146
`Byte Merging ........ ‘- ................................................................................................ 147
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`——-—-—
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`
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`/PCI System Architecture
`Collapsing .............................................................................................................. 147
`Cache Line Merging .............................................................................................. 147
`Addressing Sequence During Memory Burst ................................................................ 148
`Linear and Cacheline Wrap Addressing .................................................................... 148
`Target Response. to ReservedSetting on AD[1:0]................................................... 150
`Do Not Merge-Processor IIO Wntes into Single Burst.'.'.‘...._.......li.‘...’..’.....;.’.
`PCI IIO Addressing............................................................................................................
`General ..........................................................................................................................
`Situation Resulting in Target-Abort............................................................................
`I/0 Address Management .......................................................................................... 153
`When 110 Target Doesn’t Support Multi-Data Phase Transactions............'................ 153
`Addresstata Stepping ..................................................................................................... 154
`Advantages: Diminished Current Drain and Crosstalk............................................ 154
`Why Targets Don't Latch Address During Stepping Process .................................. 155
`Data Stepping ............................................................................................................... 155
`How Device Indicates Ability to Use Stepping ......................................................... 155
`Designer May Step Address, Data, PAR (and PAR64)‘ and IDSEL.......................... 156
`Continuous and Discrete Stepping ............................................................................. 156
`Disadvantages of Stepping.......................................................................................... 157
`Preemption While Stepping in Progress..................................................................... 157
`Broken Master .............................................................................................................. 158
`Stepping Example ........................................................................................................ 159
`When Not to UseSteppmg
`161
`Who Must Support Stepping? ..................................................................................... 161
`Response to Illegal Behavior............................................................................................ 161
`
`Introduction........................................................................................................................ 163
`Master-Initiated Termination........................................................................................... 163
`Master Preempted........................................................................................................ 164
`Preemption During Timeslice............................................................................... 164
`Timeslice Expiration Followedby Preemption................................................... 165
`Master Abort: Target Doesn't Claim Transaction ..................................................... 167
`Introduction ........................................................................................................... 167
`Master Abort on Single Data Phase Transaction
`167
`Master Abort on Multi-Data Phase Transaction 169
`Action Taken by Master in Response to Master Abort ...................................... 171
`General ............................................................................................................ 171
`Special Cycle and ConfigurationAccess 1'71
`Target-Initiated Termination.......................................................................................'.....1‘71
`STOP# Signal ................................................................................................................ 1'71
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`Disconnect..................................................................................................................... 1'72
`Description............................................................................................................. 172
`Reasons Target Issues Disconnect........................................................................ 173
`Target Slow to Complete Data Phase........................................................._...173
`Memory Target Doesn’t Understand Addressing Sequence ...................... 173
`Transfer Crosses Over Target’s AddressBoundary...................L......'.......... 173 7
`Burst Memory Transfer Crosses Cache Line Boundary...
`... 174
`Type ”A” Disconnect: Initiator Not Ready When Target Says STOP ............... 174
`Type ”B” Disconnect: Initiator Ready When Target Says STOP ....................... 175
`Retry (Type C) Disconnect ........................................................................................... 178
`Description ............................................................................................................. 178
`Reasons Target Issues Retry ................................................................................. 179 -
`Memory Target Doesn’t Understand Addressing Sequence ...............-....... 179
`Target Very Slow to Complete First Data Phase.......................... -. ............... 179
`Snoop Hit on Modified Cache Line............................................................... 179
`Resource Busy ................................................................................................. 180
`Memory TargetLocked .................................... 180
`Retry Example ........................................................................................ ‘............... 180
`Host Bridge Retry Counter ................................................................................... 182
`Target Abort
`....................................................................... 182
`Description ............................................................................................................. 182
`Reasons Target Issues Target Abort .................................................................... 183
`Broken Target..........................................................................................-........ 183
`I/O Addressing Error .................................................................................... 183
`Address Phase Parity Error ........................................................................... 183
`Master’s Response to Target Abort...................................................................... 183
`Target Abort Example..........................: ................................................................ 183
`How Soon Does Initiator Attempt to Re—Establish Transfer After
`Retry or Disconnect? .................................................................................................. 185
`Target-Initiated Termination Summary ..................................................................... 185
`—————__—...—__....__.____
`CHAPTER 10: Error Detection and Handling
`Introduction to PCI Parity................................................................................................. 187
`PERR# Signal...................................................................................................................... 189
`Data Parity .......................................................................................................................... 189
`Data Parity Generation and Checking on Read ......................................................... 189
`Introduction ........................................................................................................... 189
`Example Burst Read .............................................................................................. 190
`Data Parity Generation and Checking on Write ........................................................ 193
`Introduction ........................................................................................................... 193
`Example Burst Write ............................................................................................. 193
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`PCI System Architecture
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`~
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`Data ParityReportmg 196
`General 196
`Parity Error DuringRead........... 196
`Parity Error DuringWrite........................... 197
`. Data Parity Error Recovery ......................................................................................... 198
`Special CaEE: Data Parity Error During Special Cycle ....:.'........T..........z: ......'.:..... xx... 199 "
`Devices Excluded from PERR# Requirement ............................................................ 199
`Chipsets .................................................................................................................. 200
`Devices That Don’t Deal with OS/ Application Program or Data
`200
`SERR# Signal...................................................................................................................... 201
`Address Parity .................................................................................................................... 202
`Address Parity Generation and Checking.................................................................. 202
`Address Parity Error Reporting.................................................................................. 202
`System Errors ...................................................................................................................... 205
`General ........................................................................_.................................................. 205
`Address Phase ParityError 205
`Data Parity Error During Special Cycle
`205
`Target Abort Detection ................................................................................................ 205
`Other Possible Causes of SystemError 205
`Devices Excluded from SERR# Requirement ............................................................ 205
`
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`HAPTER 11: Interrupt-Related ISSues
`Single—Function