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`HTC-LG-SAMSUNG EXHIBIT 1007
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`HTC-LG-SAMSUNG EXHIBIT 1007
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`Page 2 of 24
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`Page 3 of 24
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`Page 4 of 24
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`Page 5 of 24
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`Page 6 of 24
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`Page 7 of 24
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`Page 8 of 24
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`Page 9 of 24
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`Page 10 of 24
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`Page 11 of 24
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`Page 12 of 24
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`Page 13 of 24
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`Page 14 of 24
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`Page 15 of 24
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`Page 19 of 24
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`Page 20 of 24
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`5,774,676
`
`11
`
`flip-flop (D register) 128, a two input multiplexer 132, here
`also labelled HMUX which is controlled by the signal
`RIGHT HALF, and an adder 134 here also labelled HADD
`which can accept additional operands for rounding and other
`purposes.
`Incoming data (DATA IN) from the previous portions of
`the decompression process i.e., the IDCT portion, is latched
`into the D-type flip-flop 128 and then interpolated with the
`next incoming data, DATA IN, when signal RIGHTHALF is
`active (high i.e., having a logic value of one) in order to
`perform horizontal interpolation. Thus horizontal interpola-
`tion is an averaging or digital filtering process in accordance
`with the present invention. The horizontal interpolated data
`from adder 134 is then provided to an (optional) D-type
`flip-flop 138 also labelled HREG for storing horizontal
`interpolated data HINT.
`The vertical interpolation element 122 includes a shift
`register including elements 140 and 142 where element 140
`includes in this case eight register stages and element 142
`includes one additional register stage. The multiplexer 146
`is connected to receive the outputs from both element 142
`and element 140 and is controlled by signal SHM. The
`output of multiplexer 146 is provided as a first input signal
`to the multiplexer 150 also labelled VMUX which is con-
`trolled by the signal DOWN HALF. The other input to
`multiplexer 150 is provided from the horizontal interpola-
`tion element 18 via register 138.
`The output of multiplexer 150 is then provided as one
`input to adder 154 also labelled VADD, the other input of
`which is provided from the output of multiplexer 146. Adder
`154 can accept additional operands for rounding and other
`purposes. (Other purposes would include shifting the overall
`value by a predetermined amount to provide an offset.) Thus
`the horizontally interpolated data from register 138 goes into
`the shift register including elements 140 and 142 and is
`interpolated with the signal HINT of the next line at the same
`vertical position when signal DOWN HALF is high. The
`purpose of the shift register including elements 140 and 142
`is to interpolate signal HINT with that of the next line and
`immediately below in the block. In this case, each block is
`8 pixels><8 pixels and hence an 8 pixel delay arrives at a pixel
`immediately under the previous pixel of interest. This pro-
`vides the desired vertical interpolation or averaging,
`i.e.
`digital filtering. The number of shifts for the shift register is
`N if there is no horizontal interpolation or N+1, (using
`element 42) if there is to be horizontal interpolation.
`D-type flip-flop 158, also labelled VREG, is optional for
`storing the vertically interpolated data VINT and serves the
`function described below.
`
`The selector element 124 provides post-processing of the
`output signal VINT from vertical interpolation element 122.
`Selector element 124 includes two multiplexers respectively
`160 and 162 and one adder 166 also labelled PADD. The two
`
`multiplexers are controlled separately respectively by con-
`trol signals INTRA and SKIP. Multiplexer 162 accepts as an
`additional input the IDCT data when the SKIP signal is logic
`low (value 0) which is added to the register output 158 when
`INTRA is asserted low (value 0). Thus the vertically inter-
`polated data VINT is processed with the input data IDCT
`data, and the final result WR DATA is provided as an output
`signal from the selector element 124.
`It is to be understood that FIG. 12 depicts a circuit suitable
`for processing only a single data bit. In actuality at least
`eight such circuits are provided for a single decoder, each
`such circuit being identical and side by side and connected
`to an eight bit parallel bus carrying DATA IN and driving an
`eight bit parallel bus WR DATA for the output signal. As is
`
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`12
`well known in MPEG, each macroblock includes six blocks,
`four of which are luminance blocks and two of which are
`
`chrominance (color) blocks. Each of these blocks includes 8
`pixels><8 pixels where each pixel is expressed by 8 bits of
`data. The circuit of FIG. 12 thus processes one pixel at a
`time.
`The various control signals shown in FIG. 12 are provided
`as follows. Multiplexer 132 is driven by the signal RIGHT
`HALF which is decoded from the MPEG bit stream and is
`provided from the VLD decompression circuit.
`Conventionally, in MPEG 1, RIGHT HALF is provided by
`logic for motion vector reconstruction. If either MPEG
`vector RECON RIGHT FOR or RECON RIGHT BACK
`
`(each being eight bit vectors) is an odd number, and also is
`in a 1/2 pixel unit, then RIGHT HALF is asserted high
`(value 1).
`Each of the clocked elements in FIG. 12, i.e. elements
`128, 138, 140, 142, 158, is driven by the memory clock
`signal which drives the entire chip of which this circuit is a
`part. Typical clock frequencies are 40 or 50 MHz, which is
`conventionally provided from a crystal oscillator.
`Registers 138 and 158 are optional and included for
`timing purposes in case the signal path is too long, to meet
`the cycle time requirement. The control signal SHM is
`derived from control signal RIGHT HALF and is e.g. a few
`cycles delayed version of the RIGHT HALF signal. The
`amount of delay is zero to N+1 cycles where N is the
`dimension of the block in pixels, as used above. Thus simple
`logic (not depicted) generates the signal SHM from the
`RIGHT HALF signal. The control signal INTRA controlling
`multiplexer 160 is a bypass signal which allows bypassing
`of the output of both the horizontal interpolation element
`118 and the vertical interpolation element 122 by instead
`providing the 0 (zero) signal as an output signal from
`multiplexer 160 when INTRA is asserted logic high (value
`1). Signal INTRA is derived from the compressed bit stream
`and provided from the VLD decompression circuitry.
`Signal INTRA is provided as is conventional in MPEG 1.
`If the MPEG code word PICTURE CODING TYPE has a
`
`value of 001, then that picture is INTRA-coded, and INTRA
`is asserted high. If the MPEG code word MACROBLOCK
`INTRA has a value of 1, then that macroblock is INTRA-
`coded, and similarly INTRA is asserted high.
`Register 158, similar to register 138,
`is provided for
`timing purposes and is optional. The SKIP control signal for
`multiplexer 162 indicates to skip reading from the IDCT
`block, and is used when there exist skipped macroblocks or
`multiple skipped macroblocks. The SKIP signal is provided
`as is conventional in MPEG. If MPEG code word MAC-
`
`ROBLOCK ADDRESS INCREMENT has a value greater
`than 1, or if MPEG code word MACROBLOCK ESCAPE
`is present, then SKIP is asserted high.
`Adders 134, 154 and 166 are e.g. ripple adders. For higher
`performance, these alternatively are carry select adders or
`carry look-ahead adders. These higher performance adders
`would be especially useful for an MPEG 2 implementation.
`In order to accommodate the needed carry bit, the full frame
`reconstruction circuit of FIG. 12 is a 9 bit data path from the
`HREG register 138 through the VADD adder 154. Each
`adder 134, 154 and 166 is a rounding adder with a built-in
`one or two bit rounding function in order to output an 8 bit
`result. Note that
`the IDCT data signal
`is a 9 bit
`twos
`complement signal. The entire selector element 124 is a 9 bit
`data path except that, as described above, the adder 166 is a
`rounding adder outputting an 8 bit result as the signal WR
`DATA.
`
`The following describes the logic used by selector ele-
`ment 124 with relation to the picture types of FIG. 10. The
`
`Page 21 of 24
`
`Page 21 of 24
`
`
`
`5,774,676
`
`13
`entire frame reconstruction circuit of FIG. 12 is used for
`reconstructing blocks or macroblocks in a video frame. The
`data flows for reconstructing respectively the I-type frame,
`the P-type frame and the B-type frame are as follows:
`1. To reconstruct an I-type frame, the IDCT data flows to
`WR DATA;
`the horizontal and vertical interpolation
`elements 118 and 122 are not used. Thus signal INTRA
`is asserted high (value 1) and signal SKIP is asserted
`low (value 0).
`2. To construct a P-type frame, both the outputs of the
`horizontal interpolation and vertical interpolation ele-
`ments 118 and 122 and the IDCT data are used. In this
`
`case the INTRA signal is asserted low and the SKIP
`signal is also asserted low. However, for skipped blocks
`(versus macroblocks) the IDCT data is not used. Thus
`SKIP is asserted high or low depending on the type of
`macroblock. If the macroblock is a skip-type, SKIP is
`high; otherwise, SKIP is low.
`3. To construct a B-type frame, the horizontal and vertical
`interpolation elements 118 and 122 are used once if
`there is only one direction of prediction, i.e. forward
`prediction or backward prediction. For bidirectional
`prediction, i.e. forward and backward prediction, hori-
`zontal and vertical interpolation elements are each used
`twice, once for forward and once for backward predic-
`tion.
`
`This is performed as shown in FIG. 13A by duplicated
`horizontal and vertical interpolation element circuitry for
`parallel processing of data coming from two different
`sources i.e., forward reference frame and backward refer-
`ence frame. The first parallel path includes elements 118,
`122 and 124:
`the second path includes elements 118A,
`122A, and 124.
`Alternatively as shown in FIG. 13B, this is performed by
`serial processing, using one set of horizontal and vertical
`interpolation elements 118, 122 in multiple passes, where
`the first pass is for one direction of prediction and a second
`pass is for the other direction of prediction. In this case the
`data path is used twice via a simple feedback loop 178, and
`there is an additional storage register 180 which stores
`intermediate data. This is called the IDCT memory which
`then in the next pass is read backwards for the other
`direction of prediction.
`For reconstruction of the B frame hence the INTRA signal
`is asserted low, but since the IDCT data is not used, the SKIP
`signal is variously asserted high or low, as for the P-type
`frame.
`
`Also, there is a frame reconstruction logic circuit (not
`shown) which conventionally decodes the picture type from
`a code word present in the MPEG bit stream.
`Advantageously, the circuit of FIG. 12 processes one data
`entry for each clock cycle. Since the data arrives in two data
`entries every two clock cycles, which is equivalent to one
`data entry per clock cycle, no memory (such as FIFO
`memory) is needed for buffering between the memory and
`the data in terminal advantageously. On the output side at the
`WR DATA port, also no FIFO or other such memory is
`needed. Due to the three stage pipeline architecture
`described in the above-referenced first application, the buff-
`ers between the second (IDCT etc.) stage and the third (FR)
`can be used for storing intermediate result and final result
`data WR DATA. This eliminates the need for any output
`FIFO because the buffers between IDCT and FR can serve
`
`this purpose.
`in accordance with the invention is an
`Also present
`error/warning correction process. If the compressed video
`bit stream is not able to be decoded in the picture layer (due
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`14
`
`to errors in the bit stream, the first pipeline stage (which is
`the VLD) generates an error signal. If the VLD cannot
`decode the bit stream in the slice, macroblock, or block
`layer, a warning signal is conventionally generated by the
`VLD. Recovery from such errors is made via an interrupt. In
`this case the VLD transmits the error signal and hence an
`interrupt is generated along with the error signal. Recovery
`from the warning signal is performed by skipping a current
`slice. When the frame reconstruction circuit of FIG. 12
`receives the warning signal, it reconstructs the current slice
`as skipped macroblocks via the SKIP signal.
`If the current picture is a P-type picture, in this case the
`frame reconstruction circuit reconstructs the remaining mac-
`roblocks in the slice with a reconstructed motion vector
`equal to zero and no DCT coefficients, as described above.
`For the case of a B-type picture, the macroblocks have the
`same macroblock type, (forward, backward, or both motion
`vectors) as the prior macroblock, differential motion vectors
`are equal to zero, and there are no IDCT coefficients used,
`as described above. Thus whatever reference frame was
`being used before the VLD became “stuc ” continues in use.
`It is assumed that the motion vector is zero for a P-type
`frame, and there is no change in the motion vector for B-type
`frame. This is accomplished by conventional logic.
`Advantageously, frame reconstruction in accordance with
`the present invention is economical in logic; for instance the
`circuit of FIG. 12 may be implemented for all 8 pixel data
`bits using approximately 2,800 gates. Due to bus and
`memory inefficiencies, a block of 8 pixels><8 pixels is
`decompressed in less than 450 cycles. According to the
`MPEG standard, 840 clock cycles are available for playing
`(decompressing) 30 MPEG SIF format video frames per
`second. (SIF is the conventional MPEG 1 frame size of
`352x240 pixels). Since the circuit
`is partitioned into a
`three-stage pipeline as described above, where the first stage
`is the VLD,
`the second stage is IQ/IZZ/IDT, and frame
`reconstruction (FR) is the third stage, each stage processes
`an 8 pixel><8 pixel block within 840 cycles. Hence the actual
`maximum throughput of the video decompression circuit is
`considerably faster than the MPEG requirement.
`While the presently frame reconstruction disclosed
`embodiment is of a logic circuit including a number of
`conventional “hardwired” logic elements, the invention is
`not so limited. Alternatively the present frame reconstruc-
`tion can be carried out in e.g. programmable logic or a
`programmable processor, given sufficient performance to
`process video data.
`Included in the microfiche appendix which is a part of this
`disclosure is a computer code listing entitled “SCCS:
`vdetop.vhd”. This listing is VHDL code which is a descrip-
`tion of the circuitry of the video decompression module as
`described above. Using appropriate commercially available
`translation tools, it is easily accomplished to provide cir-
`cuitry as described by this VHDL code.
`The other element for video decompression referred to
`above is the software driver (program) executed by the host
`computer microprocessor. A flow chart of this program is
`shown in FIGS. 14A through 14F. FIG. 14A shows the
`MPEG driver modules. This MPEG driver includes code for
`
`video decompression, audio decompression and synchroni-
`zation therebetween. The right hand side of FIG. 14A shows
`the video decompression,
`i.e. VDE code, modules. This
`includes six modules which respectively represent VDE
`initialization, open, add packet, decode, close and exit.
`Detail of each of these modules is shown in FIGS. 14B
`
`through 14F on a step by step basis. This flow chart is self
`explanatory to one of ordinary skill in the art, and therefore
`its content is not repeated here.
`
`Page 22 of 24
`
`Page 22 of 24
`
`
`
`5,774,676
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`15
`An actual computer program which implements this video
`decompression for the higher level MPEG layers is included
`in the microfiche appendix and entitled “CP3 VDE Driver—
`High Level Routines.” This is annotated to refer to the
`various modules shown in the right hand portion of FIG.
`14A and also additional related modules involved in the
`video decompression process. This computer program is
`written in the “C” and assembly computer languages.
`The various computer code listings herein are not limiting
`but are illustrative of a particular embodiment of one version
`of the present invention. It is to be understood that given the
`description of the embodiments of the invention herein,
`various implementations of systems in accordance with the
`invention may be made using different types of computer
`languages and other circuitry arrangements.
`This disc
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