`
`Pag 1 of 23
`Page 1 of 23
`
`HTC-LG-SAMSUNG EXHIBIT 1005
`
`

`

`
`
`Page 2 of 23
`Page 2 of 23
`
`

`

`
`
`digest of papers
`
`February 25 -"B. 19L?
`
`I
`
`rFITY-FIFIST 1EEE COMPUTER
`
`CIETT :f-JTEPMATIONAL CONFEFIEI'ch
`
`ILEErIIm
`
`n mam
`
`Page 3 of 23
`Page 3 of 23
`
`

`

`digest ofpapers
`
`COMPCON ’96
`
`Technologies for the Information Superhighway
`
`Forty—First IEEE Computer Society International Conference
`
`Sponsored by — The IEEE Computer Society
`
`February 25 —28, 1996
`
`Santa Clara, California
`
`Tokyo
`
`IEEE Computer Society Press
`Los Alamitos, California
`-
`
`Washington
`
`.
`
`Brussels
`
`. -
`
`Page 4 of 23
`Page 4 of 23
`
`
`
`

`

`
`
`
`
`IEEE Computer Society Press
`10662 Los Vaqueros Circle
`PO. Box 3014
`Los Alamitos, CA 90720-1264
`
`Copyright © 1996 by The Institute of Electrical and Electronics Engineers, Inc.
`All rights reserved.
`
`Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries may
`photocopy beyond the limits of US copyright law, for private use of patrons, those articles in this volume
`that carry a code at the bottom of the first page, provided that the per-copy fee indicated in the code is paid
`through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.
`
`IEEE Copyrights Manager, IEEE
`Other copying, reprint, or republication requests should be addressed to:
`Service Center, 445 Hoes Lane, PO. Box 1331, Piscataway, NJ 08855—1331.
`
`The papers in this book comprise the proceedings of the meeting mentioned on the cover and title page. They
`reflect the authors’ opinions and, in the interests of timely dissemination, are published as presented and
`without change. Their inclusion in this publication does not necessarily constitute endorsement by the
`editors, the IEEE Computer Society Press, or the Institute ofElectrical and Electronics Engineers, Inc.
`
`IEEE Computer Society Press Order Number PRO7414
`ISBN 0—3186-7414-8
`ISSN 1063-6390
`
`IEEE Order Plan Catalog Number 96CB35911
`Order Plan ISBN 0-8186-7415-6
`Microfiche ISBN 0-8186-7416-4
`
`IEEE Computer Society Press
`Customer Service Center
`10662 Los Vaqueros Circle
`PO. Box 3014
`Los Alamitos, CA 90720-1264
`Tel: +1-714-821-8380
`Fax: +1-714-821-4641
`Email: cs.books@computer.org
`
`Additional copies may be orderedfrom:
`
`IEEE Service Center
`445 Hoes Lane
`PO. Box 1331
`Piscataway, NJ 08855-1331
`Tel: +1—908-981-1393
`Fax: +1-908-981—9667
`misc‘ustserv @computer.org
`
`IEEE Computer Society
`13, Avenue de I‘Aquilon
`B—1200 Brussels
`BELGIUM
`Tel; +32—2—770-2198
`Fax: +32-2—770—8505
`euro.ofc @computer.org
`
`Editorial production by Mary E. Kavanaugh
`Cover by Joseph Daigle
`Printed in the United States of America by KNI
`
`f2”
`.
`\ug
`
`
`
`
`
`IEEE Computer Society
`Gosliima Building
`2-l9—1 Minami-Aoyama
`Minato—ku, Tokyo 107
`JAPAN
`Tel: +81~3—3408-3118
`Fax: +81-3-3408—3553
`tokyo.ofc@computer.org
`
`Page 5 of 23
`Page 5 of 23
`
`®
`
`The Institute of Electricai and Electronics Engineers. Inc.
`
`hoohfithflii
`
`

`

`Proceedings of COMPCON ’96
`
`Table of Contents
`
`Message from the General Chair .............................................................................................. xi
`
`Message from the Program Chair .......................................................................................... xiii
`
`Organizing Committees ............................................................................................................. xiv
`
`Session 1: Wireless Interconnects
`
`Chair: John Barr —~— Motorola
`
`
`
`CDPD and Emerging Digital Cellular Systems ........................................
`
`a
`
`T. Meianchuk, P. Dupont, and S. Backer
`
`Wireless Network Extension Using Mobile IP ..............................“4333‘?”
`KL. Geiger, J.D. Solomon, and KJ. Crisler
`%
`
`
`
`The Bay Area Research Wireless Access Network (BARWAN) ............................................... 15
`RH. Katz, EA. Brewer, E. Amir, H. Balakrishnan, A. Fox, S. Gribble,
`T. Hades, D. Jiang, GT. Nguyen, V. Padmanabhan, and M. Stemm
`
`Session 2: ATM Networks
`
`Chair: Anujan Vanna —- University of California, Santa Cruz
`
`Performance of Explicit Rate Flow Control in ATM Networks ................................................. 22
`L. G. Roberts
`
`MPEG—2 Over ATM: System Design Issues ............................................................................. 26
`S. Varma
`
`FAST: A Simuiation Testbed for ATM Networks .................................................................... 32
`D. Stiliadis and A. Varma
`
`Session 3: Broadband Interactive Data Services
`
`Chair: Ilja Bedner — Hewiett-Packard
`
`HP BIDS — Broadband Interactive Data Solution .................................................................... 39
`I. Bedner and A. Ranoas
`
`Design Considerations for a Hybrid Fiber Coax High-Speed Data Access Network ................... 45
`D. Picker
`
`Session 4: Agent Languages
`
`Chair: Adam Hertz —~ General Magic
`
`Mobile Telescript Agents and the Web ..................................................................................... 52
`P. Do‘mei
`
`Mobile Agent Security and Telescript ....................................................................................... 58
`J. Tardo and L. Valente
`
`.__
`_'_j::
`
`‘
`
`Page 6 of 23
`Page 6 of 23
`
`

`

`
`
`Session 5: World Wide Web
`
`Chair: Robert Hagmann —M Oracle
`People, Places, and Things: The Next Generation Web ............................................................ 65
`J. Gwertzman and M. Seltzer
`An Internet Difference Engine and its Applications ................................................................... 71
`T. Ball and F. Douglis
`Don’t Get Caught in the Web: A Fieldguide to Searching the Net ............................................ 77
`W.R. Tuthill
`
`Session 6: World Wide Web Servers
`
`Chair: Winfried Wilcke _ HAL Computer Systems
`A Scalable and Highly Available Web Server ............................................................................ 85
`D.M. Dias, W. Kish, R. Mnkherjee, and R. Tewari
`
`Session 7: Performance Characterization and Analysis
`Co-Chairs: Nasr Ullah and Marianne Hsinng —— Motorola
`The Capture, Characterization, and Performance Analysis of Macintosh® Traces ...................... 94
`S. McMahon
`
`A Measurement Study of Memory Transaction Characteristics on a
`PowerPC-Based Macintosh ..................................................................................................... 100
`T. Adams
`Load Miss Performance Analysis Methodology Using the PowerPCTM 604 Performance
`Monitor for OLTP Workloads ................................................................................................. 111
`EH. Welbon, RS. Moore, FE. Levine, and GP. Roth
`Workload Effects on SMP Scaling in AIX Version 4 .............................................................. 117
`K. Dixit, J. Van Fleet, and B. Olszewski
`
`Session 8: Panel — Networking Virtual Environments
`Chair: Michael Zyda —- Naval Postgraduate School
`Panelists: M. Zyda ~— “Networking Large—Scale Virtual Environments”
`T. Meyer — “The Future of VRML”
`M. Macedonia —~— “A Taxonomy for Networked Virtual Environments”
`W. Katz —— “Defense and Entertainment Industry Efforts in Networking
`Virtual Environments”
`
`Session 9: PowerPC Microprocessors and Systems
`
`Co-Chairs: Nasr Ullah —— Motorola
`
`Kaivalya Dixit — IBM
`Design of the PowerPC 604eTM Microprocessor ...................................................................... 126
`M. Denman, P. Anderson, and M. Snyder
`The Performance and PowerPC PlatformTM Specification Implementation of the
`MPC106 Chipset .................................................................................................................... 132
`CD. Bryant, MJ. Garcia, BK. Reynolds, LA. Weber, and GE. Wilson
`
`Page 7 of 23
`Page 7 of 23
`
`vi
`
`

`

`PowerPC Platform: A System Architecture ............................................................................ 140
`S. Bunch, R. Hochspmng, and T. Moore
`
`Motorola PowerPCTM Migration Tools — Emulation and Translation ..................................... 145
`T. Afzal, M. Brerernirz, M. Kacher, S. Menyhert, M Ommermon, and W. Sn
`
`Session 10: PA-RISC Evolution
`
`Chair: Ruby Lee — Stanford University
`
`64-bit and Multimedia Extensions in the PA—RISC 2.0 Architecture ........................................ 152
`R. Lee and J. Huck
`
`Mid—Range and High—End PA—RISC Computer Systems ................................... ; ..................... 161
`R. Elsbernd
`
`PA73OOLC Integrates Cache for Cost/Performance ................................................................. 167
`D. Hollenbeck, SR. Undy, L. Johnson, D. Weiss, P. Tobin, and R. Carlson
`
`Session 1 1 : Having it your Way — High-Code-Density, High-Integration,
`and High-Performance ARMS
`
`Chair: Allen Baum — Apple Computer
`
`Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and
`Consumer Applications ........................................................................................................... 176
`L. Goudge and S. Segars
`
`ARM7100 ..._. A High-Integration, Low—Power Microcontroller for PDA Applications ............ 182
`G. Budd and G. Milne
`.
`'
`-
`
`StrongARM: A High—Performance ARM Processor ............................................................... 188
`R. Wirek and J. Montonaro
`
`Session 1 2: MPEG2
`
`Chair: Vivian Shen — Hewlett-Packard
`
`A Scalable Chip Set for MPEG2 Realeime Encoding .................'. .j ........................................ 193
`A. Ngai, J. Sutton, C. Boice, and C. Gebler
`'
`
`Performance Comparison of MPEG1 and MPEG2 Video Compression Standards ................... 199
`S. Lin
`
`Mediaprocessing in the Compressed Domain .......................................................................... 204
`V. Bhaskaran
`
`Session 1 3:
`
`Interactive Television
`
`Chair: Robert Hagmann _ Oracle
`
`A Distributed System Client/Server Architecture for Interactive Multimedia Applications ....... 211
`S. Rege
`
`Dynamic Bandwidth Allocation for Interactive Video Applications over Corporate
`I Networks ................................................................................................................................ 219
`CI. Beckmann
`
`The Tiger Shark File System ................................................................................................... 226
`R.L. Haskin and RB. Schmuck
`
`Page 8 of 23
`- Page 8 of 23
`
`vii
`
`

`

`
`
`Session 1 4: Interactive 1V Settop
`
`Chair: Deven Kalra —- Hewlett—Packard
`Interactive Television Settop Terminal Architectures .............................................................. 233
`AN. Nair
`Multimedia Transmission Link Protocol — A Proposal for Digital Information
`Transmission in HFC Cable Systems ......................................................................................
`R~F. Chin and R. Hutchinson
`DAVID® System Software v2.0 for Interactive Digital Television Networks ..........................
`A. Davidson
`
`39
`
`241
`
`Session 1 5: Scalable Clusters
`Chair: Marco Annaratone —-— DEC Western Research Laboratory
`Overview of Memory Channel Network for PCI ..................................................................... 244
`R. Gillett, M. Collins, and D. Pimm
`Digital’s Clusters and Scientific Parallel Applications ............................................................
`R. Kaufinann and T. Reddin
`Overview of Digital UNIX Cluster System Architecture
`W.M. Cardozo, F.S. Glover, and WE. Snaman, Jr.
`
`250
`
`254
`
`............................
`
`Session 1 6: HAL Computer Systems
`Chair: Winfried Wilcke —- HAL Computer Systems
`
`A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip ...................................................
`A. Mu, J. Larson, R. Sastry, T. Wicki, and WW. Wilcke
`Performance Limiting Factors in Http (Web) Server Operations ..............................................
`F. Prefect, L. Doan, S. Gold, 7'. Wicki, and W. Wilcke
`
`261
`
`267
`
`Session 17: Exploiting New Storage and Network Technologies
`Chair: Norman 1. Pass —— IBM Almaden Research Center
`SSA: A High—Performance Serial Interface for Unparalleled Connectivity .............................. 274
`A. Wilson
`Redundant Arrays of Independent Libraries (RAIL): A Tertiary Storage System ....................
`D.A. Ford, R.J.T. Morris, and A.E. Bell
`Randomized Data Allocation for Real—Time Disk I/O .............................................................
`S. Berson, R.R. Muntz, and WK. Wong
`
`280
`
`286
`
`29]
`
`Services and Architectures for Electronic Publishing ...............................................................
`D.M. Choy and RJ. T. Morris
`
`Session 1 8: Multimedia Authoring
`Chair: Michael A. Harrison —— University of California, Berkeley
`Graphical Objcot-Oriented Multimedia Application Development: Technology
`and Market Trends ..................................................................................................................
`H. Steger
`-
`
`299
`
`Page 9 of 23
`- Page 9 of 23
`
`viii
`
`

`

`Graphical Containment in Multimedia Authoring .................................................................... 300
`H. Epelman-Wang, S. Markowitz, and B. Roddy
`'
`
`User Interfaces for Authoring Systems with Object Stores .............................................. , ....... 305
`B. Roddy, S. Markowitz, and H. Epelman-Wang
`
`Session 1 9: Competing Architectures for Multimedia Processing
`
`Chair: Cary Kornfeld — consultant
`
`The MpactTM Media Processor Redefines the Multimedia PC
`P. Foley
`
`. . . ..- ......................................... 311
`
`An Architectural Overview of the Programmable Multimedia Processor, TM-l
`S. Rathnam and G. Slavenbnrg
`
`...................... 319
`
`Improving Performance for Software MPEG Players .............................................................. 327
`D.F. Zucker, MJ. Flynn, and RB. Lee
`
`Session 20: The MicroUnity Mediaproeessor
`Chair: Steve Manser — Micro Unity Systems
`
`Architecture of a Broadband MediaProcessor .......................................................................... 334
`C. Hansen
`
`MicroUnity Software Development Environment .................................................................... 341
`R. Hayes, G. Loyola, C. Abbott, and H. Mossalin .
`
`Broadband Algorithms with the MicroUnity Mediaprocessor .................................................. 349
`C. Abbott, H. Massolin, K. Peterson, T. Karzes, L. Yamano, and G. Kellogg
`
`Session 21: DRAM Technologies
`
`Chair: S. Peter Song —— Somsnng
`
`Burst and Latency Requirements Drive EDO and BEDO DRAM Standards ............................ 356
`A. Mormann
`'
`
`Synchronous DRAM Evolutionary Changes Bring Costherformance Advantages in
`Memory Systems .................................................................................................................... 360
`AB. Cosorooba
`.
`
`High Bandwidth RDRAM Technology Reduces System Cost
`R. Crisp
`'
`
`............................................ 365
`
`Multi-Gigabyte/sec DRAM with the MicroUnity MediaChannelTM Interface ........................... 378
`T. Robinson, C. Hansen, B. Herndon, and G. Rosseel
`
`Session 22: Pentium®Pro System Architecture
`Chair: Konrad Lai — Intel
`
`An Overview of the Pentium®Pro Processor Bus .................................................................... 383
`N. Sarangdhor and G. Singh
`
`Pentium®Pro Processor Workstation/Server PCI Chipset ........................................................ 388
`M. Bell and T. Holman
`'
`
`Multiprocessor Validation of the Pentium®Pro Microprocessor ............................................... 395
`D. Marr, S. Thakkar, and R. chker
`
`Page 10 of 23
`Page 10 of 23
`
`ix -
`
`

`

`
`
`Session 23': Storage Technology
`
`Chair: Harry S. Gill — IBM
`
`Data Storage IC Technolgy ..................................................................................................... 402
`J. Kovacs and R. Kroesen
`
`Session 24: UltraSPARC and Java
`
`Chair: Robert Garner — Sun Microsystems
`
`UltraSPARCTM: Compiling for Maximum Floating-Point Performance .................................. 408
`P. Tirnmalai, D. Greenley, B. Beylin, and K. Sabramanian
`
`UltraSPARC—IFM: The Advancement of UltraComputing ...................................................... 417
`G. Goldman and P. Tirnmalai
`
`JavaTM and HotJava: A Comprehensive Overview ................................................................. 424
`S. Shoio, A. van Hofl‘, and H. Jellinek
`
`Session 25: Desktop Color -—- From Eye to Paper
`Chair: Allen Baum — Apple Computer
`
`:
`
`Digital Cameras and Electronic Color Image Acquisition ...................................................._.
`J. Dalton
`'
`
`.
`
`.
`
`_ 431 '
`
`Electronic Color Printing Technology ..................................................................................... 435
`. GK. Starkwearher
`.
`
`ColorSyncTM: Synchronizing the Color Behavior of Your Devices .....................................‘.
`W~L. Chu and S. Swen
`
`.
`
`. . 440
`
`Session 26: Architecture of Workflow Management Systems
`
`Chair: Berthold Reinwald — IBM Almaden Research Center
`
`il
`
`a;
`
`
`
`
`is
`
`a a
`
`;
`
`
`
`
`
`.
`Object—Oriented Workflow Technology in InConcert ................. -.................
`-
`S.K. Sarin
`_
`Structured Workflow Management with Lotus Notes Release 4 ..................................-..........' .
`B. Reinwald and C. Mohan
`
`................. 446
`.
`. 451
`
`.
`
`.
`
`.
`
`An Architecture for Large—Scale Work Management Systems ........................................ '. ......._458
`M. Beizer
`-
`.
`
`Session 27: “Toy Story”
`
`Chair: Darrell Long — University of California, Santa Cruz
`
`The Making of Toy Story ._....................................................................................................... 463
`M. Henna, H. Hickel, E. Johnson, and S. Konishi
`
`Additional Paper: The following paper was presented as the MN paper in Session 12
`
`Single Chip MPEG2 Decoder with Integrated Transport deocder for Set-top Box ................... 469
`J. Fandrianto
`
`Author Index ....................................................................................................................... 473
`
`Page 11 of 23
`Page 11 of 23
`
`
`
`

`

`
`
`An Architectural Overview of the Programmable
`Multimedia Processor, TM-l
`
`Selliah Rathnam, Gert Slavenburg.
`
`Philips Semiconductors
`811 E. Arques Avenue, Sunnyvale, CA 94088
`
`ABSTRACT
`
`
`s'the irst in afamily ofprogrammable multimedia
`cess'or from the Trimedia product group of Philips
`
`
`m .onductors. This "C” programmable processor
`"a high performance VLIW—CPU core with Video and
`
`peripheral units designed to support the popular
`
`ti
`'edia applications. TM—I
`is des1gned to concur-
`
`.ently process video, audio, graphics, and communica-
`
`'
`'
`ata. The VLIW-CPU core is capable of executing a
`main of twenty seVen operations per cycle, and the
`
`d execution rate is about five operations per cy-
`
`efo " the timed a plications. The audio unit easily han-
`
`ifi’e'rent au lo formats including the 16-bit stereo
`"The video unit is capable 0 processing difierent
`
`nd RGB pixelformats with orizontal and vertical
`
`tug-and color space conversion. TM—I applications
`
`can range from low-cost, stand alone systems such as
`video
`ones to programmable, multipurpose plug-in
`cards fiir traditional computers.
`
`‘ INTRODUCTION
`1.0
`h— erformance multi-
`TM-l is a buildin -block for hi
`media a plications t at deal with ig -qua1ity video and
`audio.
`-1 easil
`im lements o ular multimedia stan—
`dards such as MP G— and MP
`-2, but its orientation
`around a powerful general-purpose CPU makes it capa-
`ble of implementing a variety of multimedia algorithms,
`whether open or proprietary.
`
`More than just an inte rated microprocessor with up- -
`usual penpherals, the T -1 microprocessor IS a flutd
`
`
`
`
`
`
`
`Huf‘lman decoder
`Sliceat-a-time
`MPEG-1 3. 2
`
`CCIH6011'656
`YUV 4:222
`
`CCIRECH {656
`YUV 4:2:2
`
`I S D0430 kHz
`Sterio digital audio
`
`I S DG-eo kHz
`Storage digital audio
`
`I20 bus to
`camera, etc.
`
`I20 Interface ‘
`m “’2 em
`
`Synchronous
`Serial
`interface
`
`v.34 or ISBN
`Front End
`
`Down at up scaling
`YUV —> FlGB
`
`Image
`Coproeessor
`
`
`
`P
`
`PC! Bus
`
`' 1. TM-1 block diagram.
`
`Page 12 of 23
`
`319
`
`

`

`
`
`Page 13 of 23
`Page 13 of 23
`
`CCIRBOHBSB
`YUV 4:2:2
`
`Stereo
`Audio In
`
`CC|H601 [656
`YUV 4:2:2
`
`Stereo
`Audio Out
`
`
`
`v.34 Modern
`Front End
`
`Figure 2. TM-1 system connections. A minimal
`T -1 system requires few supporting compo-
`nents.
`..
`
`computer system controlled by a small real-time OS ker—
`nel t at runs on the VLIW processor core. ”I‘M-1 contains
`a CPU, a hi h-bandwidth internal bus, and internal bus-
`mastering D A peripherals.
`
`TM-l is the first member of a famil of chips that will
`carry investments in software forwar
`in time. Compati~
`bility between famin members is at the source—code lev-
`cl; binary compatibllity between family members is not
`guaranteed. Al
`family members, however, will be able
`to
`erform the most important multimedia functions,
`suc
`as running MPEG-2 software.
`
`Defining software com atibility at the source-code
`level
`ives Philips the free om to strike the optimum bal—
`ance etween cost and performance for all the chips in
`the TM—l family. Powerful compilers ensure that pro-
`grammers seldomly need to resort to non— ortable as—
`sembler
`rogrammmg. Programmers use T -1’s power—
`ful low- eve] operations from source code; these DSP—
`like operations are invoked with a familiar function-call
`syntax. Trimedia also
`rovides hand—coded and tuned
`multimedia libraries w ich can be used to increase the
`performance of the multimedia applications.
`
`As the first member of the family, TM—l is tailored for ,
`use in PC-based ap lications. Because it is based on a
`general-purpose C
`, TM—l can serve as a multi—func—
`tion PC enhancement vehicle. Typically, a PC must deai
`with multi—standard video and audio streams, and users
`desire both decompression and compression, if possible.
`While the CPU chips used in PCs are becoming ca able
`of low—resolution real-time video decompression,
`igh«
`quality video decompression—not to mention com res—
`sron—wis still out of reach. Further, users deman that
`their systems provide live video and audio without sacri-
`ficing the responsiveness of the system.
`
`TM-l enhances a PC system to rovide real-time mul-
`timedia, and it does so with the a vantages of a special-
`pugaose, embedded solution—low cost and chip count—
`an the advantages of a eneral-purpose rocessor—re-
`programmability. For P
`applications, M—l far sur—
`passes the capabilities of Died-function multimedia
`0 ms.
`
`Other Trimedja family members will have different
`sets of interfaces a pro date for their intended use. For
`example, a TM-] cfirp or a cable—TV decoder box would
`eliminate the video-in interface.
`
`2.0 TM-l CHIP OVERVIEW
`
`The key features of TM-l are:
`
`eneral- urpose VLIW proces—
`- A very powerful,
`sor core that coor 'nates al on-chip activ1ties. In
`addition to implementin the non—trivial parts of
`multimedia algorithms,
`is
`rocessor runs a small
`real-time operating system at is driven by inter-
`rupts from the other units.
`' DMA—driven. multimedia input/output units that
`operate independently and that properly format
`data to make processing efficient.
`- pMA—driven multimedia coprocessors that operate
`independently and erform operations speclfic to
`important multime 1a algorlthms.
`- A high—performance bus and memolar system that
`provrdes communicatlon between T —l s process-
`ing units.
`
`Figure 1 shows a block diagram of the TM—l chip. The
`bulk of a TM-l system consrsts of the TM-1 micro r -
`cessor itself, a block of synchronous DRAM (SDRA1iVI)
`and minimal external circuitry to interface to the incom—
`ing and/or outgoing multimedia data streams. TM-l can
`gluelessiy interface to the standard PCI bus for ersonal-
`computer-based a plications; thus, TM-‘l can e placed
`directly on the P mainboard or on a plug—in card.
`
`Figure 2 shows a possible TM-l system application. A
`video-in ut stream, If present, might come dlrectly from
`a CCIR Ol-compliant digital video camera chip in YUV
`412:2 format; the interface is glueless in this case. A non—
`standard camera chi
`can be connected via a video de—
`coder chi
`(such as t e Phili
`s SAA7111). A CCIR 601
`out at vi eo stream is provi ed directly from the TMwl
`to rive a dedicated video monitor. Stereo audio input
`and output re uire external ADC and DAC support. he
`operation of
`e video and audio interface units is highly
`customizable through programmable parameters.
`
`The glueless PCI interface allows the TM—l to display
`video Via a host PC’s video card and to lay audio via a
`host PC’s sound hardware. The Image
`cprocessor pro—
`vides dis lay support for live video in an arbitrary num-
`ber of ar itraiily overlapped windows.
`
`Finally, the V34 interface requires only an external
`modem front-end chip and phone line interface to pro-
`vide remote communication support. The modem can be
`used to connect TM—l—based systems for video phone or
`video conferencing applications, or it can be used for
`general—purpose data communication in PC systems.
`
`3.0 BRIEF EXAMPLES OF OPERATION
`
`The ke to understanding TM— 1' operation is observing
`that the PU and peripherals are time—shared and that
`communication between units is through SDRAM mem~
`
`320
`
`

`

`
`
`cry. The CPU switches from one task to the next; first it
`decompresses a Video frame, then it decompresses a slice
`of the audio stream, then back to video, etc. As neces-
`gar , the CPU issues commands to the peripheral units. to
`are estrate their operation.
`
`the PCI bus for archival on local mass storage, or the host
`can transfer the compressed video over a network, such
`as ISDN. The data can also be sent to a remote system us—
`ing the integrated V34 interface to create, for example,
`a video phone or video conferencing system.
`
`The TM—l CPU can enlist the ICP and video-in units
`to help with some of the straightforward, tedious tasks
`assocrated with video processing. The function of these
`units is programmable. For example, some video streams
`are—Jor need to be—scaled horizontally, so these units
`can handle the most common cases of horizontal down—
`and tip-scaling without
`intervention from the TM-l
`CPU.
`
`3.1 Video Decempression in a PC
`A typical mode of operation for a TM—l s stem is to
`serve as a video-decom ression engine on a CI card in
`a PC. In this case, the C doesn’t know the TM—l has a
`powerful, general—purpose CPU; rather, the PC just treats
`the hardware on the PCI card as a “black-box” engine.
`
`Video decompression begins when the PC operating
`s stem hands the TM—l a pointer to compressed video
`ata in the PC’s memory (t e details of the communica-
`tion rotocol are t pica 1y handled by a software driver
`insta led in the PC 5 operating system).
`
`The TM—l CPU fetches data from the compressed vid-
`eo stream via the PCI bus, decompresses frames from the
`video stream, and places them into local SDRAM. De-
`compression ma be aided by the VLD (variable-length
`decoder) unit, w ich implements Huffman decoding and
`is controlled by the TM»l CPU.
`
`When a frame is ready for dis lay, the TM—l CPU
`ives the ICP (image coprocessor a display command.
`he ICP then autonomously fetches the decom ressed
`frame data from SDRAM and transfers it over
`6 PCI
`bus to the frame buffer in the PC’s video dis Ia card (or
`the frame buffer in PC system memory if t e C uses a
`UMA (Unified Memory Architecture) frame buffer).
`The ICP accommodates arbitrary window size, position,
`and overlaps.
`
`3.2 Video Compression
`
`Another typical application for TM—l is in video com-
`pression. In this case, uncompressed video is usually
`supplied directly to the TM—l system via the video-in
`unlt. A camera chip connected directI
`to the video-in
`unit supplies YUV data in eight—bit,
`:2:2 format. The
`video-in unit takes care of sampling the data from the
`camera chip and demultiplexmg the raw video to
`SEDRAM in three separate areas, one each for Y, U, and
`
`When a complete video frame has been read from the
`camera chip b the video-in unit, it interrupts the TM—l
`CPU. The CPU compresses the video data in software
`(using a set of powerful data-parallel operations) and
`Writes
`the compressed data to a separate area of
`SDRAM.
`
`Since the powerful, general-pu ose TM-l CPU is
`available, the com ressed data can e encrypted before
`being transferred or security.
`
`4.0- VLIW CORE AND PERIPHERAL
`UNITS
`
`4.1 VLIW Processor Core
`
`The heart of TM—l is its powerful 32—bit CPU core.
`The CPU implements a 32-bit linear address space and
`128, fully general-purpose 32-bit registers. The registers
`are not separated into banks; any operation can use any
`register for any operand.
`
`The core uses a VLIW instruction—set architecture and
`is fully general-purpose. TM-l uses a VLIW instruction
`length t at allows up to five simultaneous operations to
`be issued. These operations can target any five of the 27
`functional units in the CPU, including inte er and float-
`ing-point arithmetic units and data-par
`e1 DSP—likc
`units.
`
`Instruction Cache (32Kb)
`
`Instr. Fetch Buffer
`
`Decompression Hardware
`
`Issue Register ( 5 Ops )
`
`Register File ( 128 X 32 )
`
`Operation Routing Network
`
`Execution Unit ( 27 Functions )
`
`Register Routing and Forwarding Network
`
`The compressed video data can now be disposed of in
`any of several ways. It can be sent to a host system over
`
`Figure 3. VLIW Processor Core and Instruction
`Cache.
`
`Page 14 of 23
`Page 14 of 23
`
`321
`
`

`

`
`
`
`Although the processor core runs a tiny real-time op-
`erating system to coordinate all activities in the TM—l
`s stem, t e processor core is not intended for true gener—
`a -purpose use as the only CPU in a computer system.
`For example, the processor core does not im lement vir-
`tual memory address translation, an essentia feature in a
`general—purpose computer system.
`
`TM-l uses a VLIW architecture to maximize roces—
`sor throughput at the lowest possible cost. VL
`archi-
`tectures have performance exceeding that of superscalar
`general-purpose CPUs without the extreme complexity
`of a superscalar implementation. The hardware saved by
`eliminating superscalar logic reduces cost and allows the
`integration of multimedia—specific features that enhance
`the power of the processor core.
`
`The TM-l operation set includes all traditional micro-
`processor operations. In addition, multimedia—specific
`operations are included that dramatically accelerate stan-
`dard video compression and decompression algorithms.
`As just one of the five operations issued in a single TM-
`1 instruction, a sin 1e special or “custom” operation can
`implement up to
`1 traditional microprocessor o era-
`tions. Multimedia-specific operations combined wit
`the
`VLIW architecture result in tremendous throughput for
`multimedia applications.
`
`Internal “Data Highway” Bus
`4.2
`The internal data bus connects all internal blocks to«
`ether and provides access to internal control registers
`in each on—chi peripheral units), external SDRAM, and
`the external P I bus. The internal bus consists of sepa-
`rate 32—bit data and address buses, and transactions on
`the bus use a block~transfer protocol. Peripherals can be
`masters or slaves on the bus.
`
`Access to the internal bus is controlled by a central ar—
`biter, which has a request line from each otential bus
`master. The arbiter is configurable in a num er of differ—
`ent modes so that the arbitration al orithm can be tai-
`lored for different ap lications. Perip eral units make re-
`quests to the arbiter or bus access, and dependin on the
`arbitration mode, bus bandwidth is allocated to t e units
`in different amounts. Each mode allocates bandwidth
`differently, but each mode guarantees each unit a mini—
`mum bandwidth and maximum service latency. All un-
`used bandwidth is allocated to the TM-l CPU.
`
`The bus allocation mechanism is one of the features of
`TM-l that makes it a true real—time system instead ofJust
`a highly integrated microprocessor With unusual periph-
`erals.
`
`4.3 Memory and Cache Units
`
`TM-l’s memory hierarchy satisfies the low cost and
`high bandwidth requirement of multimedia markets.
`Since multimedia Video streams can require relatively
`large temporary storage, a significant amount of DRAM
`is required.
`
`TM‘l has a glueless interface with s nchronous
`DRAM (SDRAM) or
`synchronous grap 1cs RAM
`
`(SGRAM), which provide higher bandwidth than the
`standard DRAM. As the SDRAM has been supported by
`major DRAM vendors,
`the competition among those
`vendors will kee the SDRAM rice in par with that of
`the standard D M. TM—l‘s RAM memory size can
`range from 2Mbytes to 64 Mbytes.
`
`The "I'M-1 CPU core is supported b separate l6—KB
`data and 32-KB instruction caches.
`he data cache is
`dual—ported in order to allow two simultaneous load!
`store accesses, and both caches are eight—way set-asso—
`ciative with a 64-byte block size.
`
`4.4 Video-In Unit
`
`The video-in unit interfaces directly to any CCIR 601/
`656-com liant device that outputs eight—bit parallel,
`412:2 Yliif time-multiplexed data. Such devices include
`direct digital camera systems, which can connect glue-
`lessly to TM—l or through the standard CCIR 656 con-
`nector with only the addition of ECL level converters.
`Non-CCIR—compliant devices can use a di
`ital decoder
`chi
`, such as the Philips SAA7111, to iute ace to