A T & T NELEC (I C)
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`[allE D - DUSDBEE [3013642 5‘17 -ATTE
`
`DSP3210 Information Manual
`introduction
`
`1. INTRODUCTION
`
`The AT&T DSP321O brings the power of floating~point signal processing to personal computers and workstations
`opening a wide range of multimedia applications. From its conception, the DSP3210 has been engineered with a
`single focus: enabling advanced multimedia functions on personal computers and workstations. Based on AT&T's
`very successful DSP320 architecture, the DSP3210 breaks new ground in its ability to be easily integrated into
`personal computer and workstation system designs. Particular attention was paid to primary bus interfacing; the
`DSP3210 is compatible with both lntei and Motorola microprocessor signalling. This allows designers to easily
`create low-cost systems using the DSP3210 as a bus—master device. A full bus-level SmartMode/ of the
`DSP3210 is offered by Logic Automation for system simulation of designs incorporating the DSP3210.
`
`in addition to its optimizing C compiler and assembly language support tools, the DSP3210 features a powerful
`real-time operating system, the AT&T Visible Caching Operating System” ( VCOSTM), which supports both multi-
`tasking and multi-processing. The VCOS operating system is an open development environment that allows the
`DSP3210 to use existing system memory in PCs and workstations rather than requiring expensive dedicated
`SRAM. Complete realatime debugging tools are included with the VCOS operating system to speed both
`application and algorithm development. By separating the application and algorithm development phases of
`multimedia software development, development schedules are simplified and shortened . The VCOS operating
`system includes its own multimedia function library complete with speech processing, speech recognition,
`graphics, music processing, and modem functions.
`In addition to new application software, the DSP3210 has
`access to the large base of existing DSPBZC application software.
`
`It describes the architecture, instruction set, and
`This document is a reference guide for the DSP3210 device.
`interfacing specifications of the device. The information necessary to write programs for the DSP3210 is also
`given in this manual, Separate documents are available with detailed information on the software and hardware
`development tools. No previ0us experience with digital signal processors is necessary to use this document, but
`an understanding of digital signal processing concepts and assembly language programming on microprocessors
`or minicomputers is recommended.
`
`1.1 Digital Signal Processing With The DSP3210
`
`A key element shared by all DSP applications is a large number of repetitive mathematical operations combined
`with extreme memory bandwidth requirements. To perform floating-point arithmetic operations, conventional
`microprocessors and co—processors use software routines and/or microcode. Newer RlSC- and DISC-based
`microprocessors offer much higher floating-point performance but lack the memory bandwidth and signal
`processing architecture required for DSP applications. Microprocessors also include many functions unnecessary
`for signal processing resulting in an unacceptable price/performance ratio for high~volume, low-cost signal
`processing applications.
`
`The DSP32tO architecture combines a hardware floating—point arithmetic unit with an architecture that supports 4
`memory accesses per instruction cycle, allowing the device to perform up to 33 million floatingpoint operations
`per second (with a clock rate of 66.7 MHz). This raw floating-point performance is combined with the DSP3210's
`signal processing architecture to enable real~time applications such as speech compression/recognition/synthesis,
`3D graphics transformations, high-quality music coding/decoding, image processing. and real-time handwriting
`analysis/recognition. New functions can easily be added to DSP3210-based systems with the addition of
`application software. Multiple DSP32105 can be combined easily to increase system performance. (AT&T‘s
`VCOS real-time operating system directly supports multiple DSP3210 implementations.)
`
`The use of floating~point arithmetic in the DSP3210 simplifies application development because it eliminates the
`effects of scaling, normalization, and overflow (which complicate development when using a fixed-point device).
`Also, many existing algorithms developed for use on large computers and array processors (using floating-point
`arithmetic) can be easily converted for use on the DSP3210. Program development is typically 3 to 10 times
`faster on the DSP3210 than similar program development on fixedrpoint processors. This is especially critical in
`multimedia applications where time-to market is a critical parameter, and a large percentage of application
`development is performed by third-party application developers.
`In addition to ease of program development,
`32—bit floating—point is often required for advanced algorithm implementations.
`’ SmartMoo’el is a registered trademark of Logic Automation,
`
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`A T & T NELEC (I C)
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`DSP321O Information Manual
`
`Early in the devetopment of a particular application, one must determine the dynamic range and precision
`requirements for the given algorithm. The following is a comparison of the dynamic range and precision
`attainable for various data word sizes. The floating-point representation of a number in the DSP3210 consists of
`a 24-bit mantissa and an 8—bit exponent. The magnitude of the mantissa is normalized to lie between 1 and 2.
`Thus, the range for the magnitude of a floating-point number N is approximately:
`
`providing an overall dynamic range in excess of 1500 dB.
`
`[N1 = (1 x 2-127, 2 x 2127) or(5.9 x10 ‘39 , 3.4 x1038).
`
`Figure 1-1 shows the dynamic range for DSP3210 floating-point numbers as compared with the dynamic range of
`16- and 24-bit fixed—point devices.
`
`1500
`
`100
`
`700
`
`4:
`E 500
`Q
`
`300
`
`16-BiT
`FIXED~POINT
`
`32—BIT
`24—BIT
`FiXED-POINT FIXED—POINT
`
`Figure 1-1 Dynamic Range of Fixed- and Floating-Point DSPs
`
`The precision of a floating-point number is determined by the size of the mantissa. The DSP3210 fioating~point
`format prevides 24 bits of precision at ail magnitudes within the range of numbers represented by the 24bit
`mantissa and 8-bit exponent.
`(Note that the DSP3210 also has eight extra bits, the guard bits, in the mantissa ot
`the 40~bit floating-point adder and accumulators. These guard bits provide added precision during accumulation
`operations).
`in contrast, the precision of a fixed-point format is a function of its word size and the magnitude of
`the given number. Figure 1-2 shows the bits of precision versus magnitude of a number for the DSP3210 floating-
`point format, as well as 16— and 24-bit fixed-point formats.
`
`1—2
`
`
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`ENE D - BUSEIEIEI:
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`[301.0649 BEE .ATTE
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`DSP3210 Information Manual
`Introduction
`
`32-BIT FLOATING POINT
`
`|
`
`I I
`
`I
`I
`I
`
`24-BIT
`SATURATION
`
`I I
`
`l I
`
`16-BlT
`
`SATURA'TION
`
`I
`
`24
`
`15
`
`8
`
`z
`g
`‘L’
`O
`g
`o.
`LL
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`0 g
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`£3
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`Figure 1-2 Precision of Fixed— and Floating-Point DSPs
`
`1.2 The AT&T Floating—Point Digital Signal Processor Family
`
`MAGNlTUDE
`
`AT&T was the first to produce floating-point digital signal processors and has continued to play a leadership role
`in the floating'point marketplace. Figure 1-3 shows the evolution of the AT&T family of floating-point digital signal
`processors.
`
`DSP320 — 80 ns
`
`
`
`
`DSP3210 - 60 ns
`
`DSPSZiO - 72 ns
`
`DSF’32C — 100 ns
`
`30
`
`20
`
`10
`
`‘53
`9
`Ll.
`
`2
`
`
`
`
`
`
`o NMOS
`
`o CMOS
`
`DSP32 - 150 ns
`
`DSP32 — 250 ns
`
`1980 1982 1984 1986 1988 1990 1992
`
`Figure 1—3 AT&T Floating-Point DSP Family Evolution
`
`1-3
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`EHE D I 0050038 0010645 2T“!
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`.ATTE’
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`DSP3210 information Manual
`
`1.2.1 The AT&T DSP32 Digital Signal Processor
`
`in 1984, AT&T developed the first single-chip floating-point programmable digital signal processor, the DSP32.
`The design goals of the DSP32 were high performance and ease of use. A major contributor to these goals was
`the selection of 32-bit floating-point arithmetic for this device.
`In the DSP32, a highly pipelined architecture allows
`the device to achieve high throughput. This architecture includes a 32—bit floating-point data arithmetic unit (DAU)
`and a 16-bit fixed-point control arithmetic unit (CAU). The DAU incorporates a 32-bit floating-point multiplier, a
`40-bit floatingspoint adder, and four 40-bit accumulators. The CAU performs 16-bit fixed-point arithmetic and logic
`operations, and provides data move and control capabilities. This unit includes 21 general-purpose registers.
`The DSP32 processes over six million instructions per second. All instructions execute in a single cycle (four
`clock periods or 160 ns) and include post-normalization for each floating-point operation. An instruction may have
`two floating-point operations: a floating—point multiplication and a floatingepoint addition, yielding two floating-point
`operations per instruction cycle. The DSP32 architecture also introduced several significant architectural
`features, many of which are still unequaled by competing digital signal processors. The DSP32 was the first DSP
`to offer a byte-addressable address space. the first with a unified memory architecture (program and data share
`the same space), the first to offer DMA, and the first DSP architecture to support 4 memory accesses per
`instruction cycle (a feature still exclusive to AT&T DSPs).
`
`1.2.2 The AT&T DSP32C Digital Signal Processor
`
`The DSP32C Digital Signal Processor is upward compatible with the DSP32 (object code, source code, and pin
`compatibility). The DSPSZC offers higher throughput, lower power dissipation, and lower cost than the DSP32.
`Major enhancements over the DSP32 include a larger address space, higher throughput parallel l/O, a fully
`vectored interrupt structure, and many instruction enhancements to better address the needs of DSP systems
`designers. The DSP3ZC has been very successful in the SD graphics, speech processing, PC add—on card, and
`telecommunications application areas. The DSPBZC is fabricated in 0.75 pm CMOS technology and is packaged
`in standard tell-pin and 68—pin (microcomputer version) plastic packages as well as a 133-pin ceramic PGA
`package.
`
`The DSPSZC‘S two execution units, the control arithmetic unit (CAU) and the data arithmetic unit (DAU), are used
`to achieve the high throughput of 12.5 million instructions per second. The CAU performs 16— or 24—bit integer
`arithmetic and logic Operations, and provides data—move and control capabilities. This unit includes 22 general~
`purpose registers. The DAU performs 32bit floating—point arithmetic for signal processing functions.
`it includes a
`32-bit floating—point multiplier, a 40-bit floating-point adder, and four 40-bit accumulators. The multiplier and the
`adder work in parallel to perform 25 million floating-point computations per second. The DAU also incorporates
`special-purpose hardware for data-type conversions.
`
`On-chip memory includes 1536 words of RAM. Up to 16 Mbytes of external memory can be directly addressed by
`the external memory interface that supports wait states and bus arbitration. All memory can be addressed as 8-,
`16, or 32-bit data, with the 32bit data being accessed at the same speed as 8» or 16bit data.
`
`in addition to
`The DSPSZC has three l/O ports: an external memory port, a serial port, and a 16-bit parallel port.
`providing access to commercially available memory, the external memory interiace can be used for memory‘
`mapped l/O. The serial port can interface to a time division multiplexed (TDM) stream. a codec, or another
`DSP32C. The parallel port provides an interface to an external microprocessor, Three on-chip direct~memory~
`access (DMA) controllers support direct memory access via the serial input, serial output, and parallel l/O ports.
`
`14
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`A T 8. T HELEC (I C)
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`ENE D I DDSUDEE 001.0895 135 .ATTE
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`DSP3210 lnformatlon Manual
`Introduction
`
`A single~ievel interrupt facility can respond to four internal and two external, individually maskable spurces. A
`relocatable vector table controls program flow based on the source of the interrupt.
`
`The DSPBZC has two general types of instructions that correspond to the two execution units: data arithmetic
`(DA) instructions and control arithmetic (CA) instructions. Primarily, DA instructions perform 32-bit floating-point
`multiply/accumulate operations for signal processing algorithms. Other DA instructions convert the DSP32C
`internal floating-point data to and from each of the following types: 8-, 16-, or 24-bit 2's complement integer. 8-bit
`u‘law, 8—bit A-law, or 32bit singleprecision lEEE standard floating-point. The CA instructions perform
`microprocessor operations such as 16- and 24-bit integer arithmetic and logic functions, conditional branching,
`and moving data.
`
`in summary, some of the key features of the DSP32C are as follows:
`
`Full. 32—bit floating-point arithmetic
`Four memory accesses per instruction cycle
`Single, linear address space
`Byte addressable internal and external memory
`Up to 16 Mbytes of external memory
`1536 words of on—chip RAM
`
`16 Mbits/s serial l/O ports and 16-bit parallel l/O port with DMA options
`8- or 16—bit microprocessor interface requiring no additional logic
`
`Single—precision, single-cycle, lEEE floating-point conversion capability
`Bit reverse addressing mode
`Four 40bit accumulators
`
`Zero-overhead looping
`
`16- and 24bit integer operations
`Vectored internal and external interrupts with hardware context save
`
`Low‘power CMOS technology
`
`The DSPSZC also includes extensive hardware and software support from both AT&T and many third parties. A
`bus functional simulation model is offered by Logic Automation, a complete DSPBZC hardware emulator is
`available from Hewlett-Packard (64773). For more information on the DSPBZC. refer to the DSP32C information
`Manual, DSPSZC Data Sheet, or any of several software support documentation manuals available from your
`AT&T account manager.
`
`1.2.3 The AT&T DSP3210 Digital Signal Processor
`
`The DSP3210 Digital Signal Processor is the newest member of AT&T's Floating-Point DSP Family. The
`DSP3210 is an enhancement of the DSP32€ architecture designed specifically to meet the needs of the
`PCNVorkstation multimedia market. The DSP3210 is a three-part product composed of the DSP3210 device, the
`V008 real-time OS, and the V003 multimedia function library. The DSP3210 is a very low—cost systems solution
`(no local DSP RAM is required for systems solutions) with complete applications support and full. 32—bit floating-
`point processing power. The DSP3210 is source code compatible with the DSPBZC via AT&T's DSPBZC to
`DSP3210 source code translator. New features added to the DSP3210 are briefly outlined in Table 1—1.
`
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`SHE D - DDSDUEB 001.06”? 0?]:
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`.ATTE
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`DSP3210 information Manual
`
`Table 1-1 DSP3210 Features
`
`
`
`
`
`
`
`
`Benermmanspularon.
`
`Compatibility with Motorola and lntel bus protocols
`(byte select of size/offset)
`Quad—word transfer capability
`
`Programmable 32-bit timer
`interruptible do—ioops that can be used in interrupt
`routines
`
`Simplifies hardware design.
`
`Increased system performance
`
`Reduces system cost.
`Improves software performance
`
`Simplifies control of serial DMA channels.
`
`Repeat facility for single instruction do loops
`(no reofetching of instruction)
`Page break detect signal for DRAMS
`Support for signed characters and unsigned shorts
`
`Packaged in a low cost 132 PQFP
`
`Speeds block move operations
`
`improves memory system performance.
`improved compiler performance.
`
`Low cost, small footprint.
`
`
`
`
`
`
`
`
`
`
`1.3 Support Software Tools
`
`A variety of tools are available to aid in application program development for the DSP3210. These tools are
`initially offered under the UNIX®, Axis-DOS“, or Macintosh ill operating systems. In addition to
`Assembler/Simulster/Compiler support tools, the DSP3210 includes the AT&T VCOS real’time operating system
`complete with its multimedia function library as well as powerful debugging and testing tools.
`
`AT&T DSP3210 Support Software Tools
`
`Software tools used to create, test, and debug DSP3210 application programs at the assembly language level are
`packaged in the DSP3210 Support Software Tools package. An assembler, link editor, simulator, and other
`utilities are included. The simulator, which has capabilities such as single‘sfepping, breakpointing, and execution
`profiling, performs precise simulations of the device.
`
`’ MS—DOS is a registered trademark of Microsoft.
`T Macintosh fl is a registered trademark of Apple inc.
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`A T & T MELEC (I C)
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`ENE D I 00501125 [1010th T05 -ATTE
`
`DSP3210 Information Manual
`Introduction
`
`AT&T DSP321O Application Software Library
`
`The DSP3210 Application Software Library is a collection of commonly-used signal processing and SD graphics
`functions. Each function is carefully benchmarked to allow applications to easily be built from collections of
`assembly language functions while meeting real—time processing requirements. Many functions are offered in
`several implementations, giving the programmer flexibility in balancing speed and memory requirements .
`
`AT&T DSP3210 C Language Compiler
`
`The optimizing C Language compiler for the DSP3210 allows application programs to be written in a general,
`high-level language.
`in applications where preliminary program development is performed using the C-ianguage
`on a minicomputer or supercomputer, the source code can be ported to the DSP3210 with a minimal amount of
`time and effort. A symbolic debugger and several libraries of commonly used arithmetic and signal processing
`functions are included with the compiler.
`
`1.4 Other Applicable Documentation
`
`The following documents provide specific information on the DSP3210 and its hardware and software
`development tools. When designing application hardware and software, it is important to have accurate
`information. Contact yOur local account representative for the latest issue of a document.
`
`The AT&T DSP3210 Digital Signal Processor Data Sheet contains up-to—date timing requirements and
`specifications, electrical characteristics, and a summary of the instruction set and device architecture.
`
`The AT&T DSP3210 Support Software Tools User Manual describes how to install and use the DSP3210 support
`software.
`
`The AT&T 08.03210 Application Sofhvare Library Reference Manual contains information on the use and design
`of each assembly~language routine included in the DSP3210 Application Software Library.
`
`The AT& T DSP3210 C—Language Compiler User Manual describes how to set up and use the DSP3210 C
`compiler.
`
`The AMT DSP3210 C-Language Compiler Library Reference Manual provides the information necessary to
`implement the C programming language with the DSP3210.
`
`1.5 Assistance
`
`Assistance is available throughout the life of the product. These services include:
`
`I Technical documentation and product samples
`:-
`Information on determining and selecting the appropriate hardware and software
`
`The AT&T DSP Bulletin Board prevides the latest and most up—to-date information about AT&T DSP products and
`application assistance:
`
`1200/2400 baud
`7 data bits, 1 stop bit, even parity
`215-778-4444
`
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`A T a T NELEC (I C)
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`EHE D - UDSUUEE 001.05%“! mm IATTB
`
`DSP3210 information Manual
`
`For technical assistance or further information including ordering information and part numbers, please contact
`the nearest office through the following phone numbers:
`
`Domestic (USA & Canada)
`
`Northeast Region
`508—626-21 61
`
`MidvAtlantic Region
`2157682626
`
`Southeast Region
`404-446-4700
`
`North Central Region
`612-885—4300
`
`South Central Region
`214-869-2040
`
`Southwest Region
`602-244-1100
`
`Rocky Mountain Region
`303-850-5415
`
`Pacific Northwest
`4086226555
`
`Southern California
`714—220-6223
`
`International
`
`Europe (except Spain & Portugal)
`+49 89 950 86 0
`Telefax: +49 89 950 86 111
`
`Spain and Portugal
`+34 1 404 6012
`Telefax: +34 1 404 6252
`
`Japan
`813-593-3301
`Telex: J32562 ATTlJ
`Telefax: 813-593-3307
`
`internal (AT&T Customers)
`
`Pacific Rim
`65225-5233
`Telex: R8 42898
`Telefax: 635-225-8725
`
`AT&T internal customers should contact their local AT&T Account Management Office.
`If the Account Management telephone number is not known, call 1-800-372-2447 and ask for the telephone
`number of your account representative.
`
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`1) n [1058025 0010850 blah EATTE’
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`CHAPTER 2. APPLICATIONS
`
`2. APPLICATIONS ............................................................................................................................................ 2-1
`2.1 PC/Workstation Multimedia Applications ................................................................................................... 2—2
`Figure 2-1 Typical PC Multimedia System Configuration ............................................................................. 2—2
`2.2 3—D Graphics Applications ........................................................................................................................... 2-3
`Figure 2-2 Typical 3-D Gtaphics System Configuration ............................................................................... 2—3
`
`
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`DSP3210 information Manual
`Applications
`
`2. APPLICATIONS
`
`The DSP3210 can be used in many different application areas including: telecommunications, speech processing,
`image processing, graphics, array processors, robotics, studio electronics, instrumentation, and military
`applications.
`
`ELECTRONIC DATA PROCESSING
`
`I Mass Memory
`I Workstations
`
`I Front-End Processor
`
`lNDUSTRlAL
`
`I Robotics
`I image Processing
`I Process Control
`I Real-Time Simulators
`I
`instrumentation
`
`TELECOMMUNICATlONS
`
`Disc controllers, high-precision servo control
`Graphics, translations, rotations, shading, perspective scaling,
`inversion, multiplication, numeric accelerators, array processing
`Bit manipulation, encryption
`
`High-precision servo control
`Restoration, pattern recognition, compression
`Minicomputer functions
`Graphics, servo control, system modeling
`Oscilloscopes, FFT, spectrum analysis, signal generators
`
`I PBX
`I Switches
`- Modems
`I Transmission
`
`Tone detection, tone generation, MF, DTMF
`Tone detection, tone generation, line testing
`Echo cancellation, filtering, error correction and detection
`Multi-pulse LPC, ADPCM, transmultiplexing, encryption
`
`GOVERNMENT/MiLlTARY
`
`I Sonar
`I ECM
`I Airtrame
`
`Beam forming, FFT
`FFT, adaptive filtering
`Simulation
`
`I Radar Tracking
`
`Precision FFT, matrix inversions
`
`SPEECH
`
`I Recognition
`I Synthesis
`I Coding
`
`CONSUMER
`
`Feature extraction, spectrum analysis, pattern matching
`LPC, format synthesis
`ADPCM, LPC, multi-pulse LPC, vectorquantization
`
`I Studio Electronics
`I Entertainment
`I Educational
`
`Digital audio
`High-end video (special effects)
`
`When the software required for a DSP application is being developed. it is often desirable to use some standard
`algorithms already in existence. Each application requires a somewhat different use of these algorithms, yet there
`are great similarities from the processing point of view. Many of the algorithms available are usable in a wide
`variety oi physical problems. The driving lorce behind most of the algorithms has been an attempt to reduce the
`computational and data transfer requirements to accommodate the performance constraints of available
`hardware, Many of these algorithms have been coded in DSP3210 assembly language and are presented in the
`A T& T DSP3210 Application Software Library Reference Manual,
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`A T 8: T HELEC (I C)
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`514E D I UDSDUEE 001.0652 I-iEl'i IATTE
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`DSP3210 Information Manual
`
`2.1 PC/Workstation Multimedia Applications
`
`The DSP3210 is intended to be used in PC and workstation system architectures in which the DSP32iO is a
`parallel processor to a host processor. The DSP3210 maintains a 32-bit bus master interface to system memory
`(see Figure 2— 1) The primary benefit of this system architecture is that the DSP is able to access program and
`data from system memory without host intervention and expensive local SRAMis replaced by general purpose
`DRAM Since the DSP3210 supports both big- and littleendian byte ordering sharing both data and pointer
`values with any host microprocessor is easily accomplished. This is especially useful in multimedia applications
`where intimate communications between the host uP and DSP are necessary. For real—time signal processing,
`on-chip SRAM is loaded with code and data from system memory before executing. Typically, applications are
`broken down into functions that are executed successively in this fashion.
`
`This techniqueis also used to create low-cost ElSA and MCA addon cards The DSP32tO acts as a bus master
`on the 32bit bus to access system memory (rather than adding memory to the DSP3210 card) lSA 16bit add-on
`cards typicaliy employ local memory since their 16-bit width would present a memory bottleneck to the DSP3210.
`However, the visible caching technique employed by the VCOS operating system permits the use of slow,
`inexpensive DRAM for local memory with minimal impact on system performance. Applications are compatible
`across all implementations described here.
`
`Low-cost, single-chip
`A/D and D/A converter
`On-chip RAM used for kernel storage
`and program/data cache.
`
`
`Telephone
`
`Speaker!
`Microphone
`
`INTERFACE
`
`SYSTEM BUS ‘
`
`Digital Audio Data
`
`
`
`
`
` BUS MASTER
` Direct interface to system bus
`
`provides high bandwidth and
`
`
`\ low cost.
`
`System memory provides tow‘cost
`storage of functions and data.
`
`Figure 2-1 Typical PC Multimedia System Configuration
`
`2-2
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`PAGE 11 of 27
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`

`

`A T & T NELEC (I C)
`
`HE D - 0050025 0010553 375 IATTE
`
`DSP3210 Information Manual
`
`Applications
`
`2.2 3-D Graphics Applications
`
`Although the DSP3210 was primarily designed for personal computer/workstation multimedia applications, it is
`ideally suited to perform the floating-point, compute intensive calculations in a typical 3-D transformation pipeline.
`In fact, while performing graphics operations, the DSP3210 often outperforms far more costly processors which
`are touted for their graphics capabilities. These operations consist of matrix multiplies, divides, square root
`computations, comparisons, and integer conversions.
`in addition to its native floating-point performance, byte
`addressability, and large address space, the DSP3210 has on-chip hardware to improve the efficiency of many of
`these operations such as: reciprocal seed, 8-, 16—, and 32-bit integer to/from floating-point conversion, clip-test
`register, Z—buffering, etc. A typical graphics system will contain multiple DSP3210 processors that operate in
`parallel to renderthe image. The low cost of the DSP3210 makes multiple DSP graphics systems practical. its
`page—break and quarter-cycle wait state features significantly reduce system costs while increasing system
`performance. Inexpensive DRAM can be used for local memory while still achieving the high throughput
`necessary for high-speed 3-D transformations. The DSP3210's flexible bus protocol also makes it possible for
`several DSP3210 devices to share the same command and output buffers with little or no performance
`degradation, further reducing system costs. Figure 2—2 shows a typical 3—D graphics subsystem architecture
`employing a common command buffer/output buffer configuration.
`
`
` DSP 1
`
`MEMORY
`
`lNTERFACE BRN
` MULTiPLE DSP32103
`C
`
`0am, son,
`BGACKNLOCKN
`
`O
`
`S
`
`Y
`5
`
`T
`
`E
`M
`
`HOST
`CPU
`
`
`
`.
`
`GRAPHICS
`COMMAND
`
`
`BUFFER
`PROCESSOR
`
`
`
`
`
`BRN, BGN.
`
`
`BGACKN,LOCKN
`
`
`
`FRAM E
`BUFFER
`
`DSP N MONITOR
`
`BRN
`MEMORY
`
`lNTERFACE
`
`
`
`
`Figure 2-2 Typical 3-D Graphics System Configuration
`
`
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`A T 3 T MELEC (I C)
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`511E D
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`UUSDDEE [201.0659 BBL .ATTE
`
`CHAPTER 3. DSP3210 ARCHITECTURE
`
`3. DSP3210 ARCHITECTURE ........................................................................................................................ 31
`Table 3-1 DSP321O Features/Benefits ................................
`................ 3-1
`Figure 3—1 DSP321O Block Diagram ............................................................................................................. 3-2
`31 Functional Units ........................................................................................................................................... 3-3
`3.1.1 Control Arithmetic Unit (CAU) .................................................................................................................. 3-3
`3.1.2 Data Arithmetic Unit (DAD) ....................................................................................................................... 3-3
`3.1.3 On-Chip Memory ...................................................................................................................................... 33
`3.1.4 Bus Interface ........................................................................................................................................... 34
`3.1.5 Serial 1/0 (810) ......................................................................................................................................... 3-4
`3.1.6 DMA Controller (DMAC) ............................... i ........................................................................................... 3-4
`3.1.7 Timer ........................................................................................................................................................ 3-5
`3.1.8 Bit l/O (BEO) .............................................................................................................................................. 3-5
`32 Processor Control Features ........................................................................................................................ 3-5
`3.2.1 Seriat l/O DMA ......................................................................................................................................... 3-5
`3.2.2 Exception Processing ............................................................................................................................... 35
`3.2.3 Wait-for-Interrupt ...................................................................................................................................... 36
`3.3 Data Types ................................................................................................................................................. 3-6
`3.3.1 32-bit 28 Complement Data Type ........................................................................................................... 3—6
`3.3.216-bit2's Complement Data Type ........................................................................................................... 3-7
`3.3.3 32-bit Floating-Point Data Type ................................................................................................................ 3-7
`Figure 3—2 DSPBZC Internal 32-bit Floating—Point Format ............................................................................. 3—?
`3.4 Memory Organization .................................................................................................................................. 3—8
`Figure 33 Memory Addressing ...................................................................................................................... 39
`Figure 3-4 Memory Map ................................................................................................................................ 3-10
`Figure 3-5 10 Memory Map ........................................................................................................................... 311
`3.5 Addressing Modes ....................................................................................................................................... 3-11
`Table 32 Addre