Paper No. 32
`
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`––––––––––––––––––
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`––––––––––––––––––
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`HTC CORPORATION, HTC AMERICA, INC., and LG ELECTRONICS, INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`
`––––––––––––––––––
`
`Case No. IPR2015-01501
`U.S. Patent No. 7,777,753
`
`––––––––––––––––––
`
`PETITIONERS’ REPLY
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`––––––––––––––––––
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`––––––––––––––––––
`
`HTC CORPORATION, HTC AMERICA, INC., and LG ELECTRONICS, INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`
`––––––––––––––––––
`
`Case No. IPR2015-01501
`U.S. Patent No. 7,777,753
`
`––––––––––––––––––
`
`PETITIONERS’ REPLY
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`IPR2015-01501
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`Petitioners’ Reply
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`Table of Contents
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`I.
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`II.
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`INTRODUCTION ........................................................................................... 1
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`BOWES AND MPEG SATISFY THE CLAIMS ........................................... 1
`
`A.
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`B.
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`C.
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`D.
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`The Combined System Includes The Idle State Limitation .................. 1
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`The Combined System Discloses the Claimed Video Circuit. ............. 3
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`1.
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`2.
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`3.
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`Bowes Discloses a Video Circuit. ............................................... 3
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`The Bowes/MPEG Combination Uses Shared Memory ............. 9
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`Bowes Can Retrieve The Data It Stores. ................................... 13
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`Bowes and MPEG Disclose the Claimed Arbiter ............................... 14
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`Reasons To Combine Bowes And MPEG ........................................... 17
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`III. CERTAIN DEPENDENT CLAIMS ............................................................. 23
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`IV. CONCLUSION .............................................................................................. 23
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`Exhibit List
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`1005
`[NEW]
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`1006
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`1007
`1008
`1009
`
`Exhibit # Reference Name
`1001
`U.S. Patent No. 7,777,753 (“the ’753 patent”)
`1002
`File History for U.S. Patent No. 7,777,753
`1003
`U. S. Patent No. 5,546,547 (“Bowes”)
`1004
`ISO/IEC 11172-2:1993: Information technology—Coding of moving
`pictures and associated audio for digital storage media at up to about
`1,5 Mbit/s—Part 2: Video,” (1st ed. August 1, 1993) (“MPEG
`Standard”)
`S. Rathnam et al., “An Architectural Overview of the Programmable
`Multimedia Processor, TM-1,” IEEE Proceedings of COMPCON ’96,
`pp. 319-326 (1996) (“Rathnam”)
`R.J. Gove, “The MVP: A Highly-Integrated Video Compression
`Chip,” Proceedings of the IEEE Data Compression Conference (DCC
`‘94), pp. 215-224 (March 29-31, 1994) (“Gove”)
`U.S. Patent No. 5,774,676 (“Stearns”)
`Declaration of Dr. Santhana Chari (“Chari Decl.”)
`International Organization for Standardization, Website of ISO/IEC
`11172-2
`WorldCat Entry for Rathnam
`
`1010
`[NEW]
`1011
`1012
`1013
`1014
`1015
`1016
`1017
`1018
`1019
`
`RESERVED
`RESERVED
`RESERVED
`Brad Hansen, The Dictionary of Multimedia, 1997
`RESERVED
`RESERVED
`U.S. Patent No. 5,748,983 (“Gulick 983”)
`WO 96/11440, PCT/US95/12933, Shared Memory System (“Whai”)
`Shanley, et al., “PCI System Architecture,” Addison-Wesley
`Publishing Company, 1995 (3rd ed.) (“Shanley”)
`ii
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`1021
`1022
`1023
`1024
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`1025
`
`Exhibit # Reference Name
`1020
`Stone, H., “Microcomputer Interfacing,” Addison-Wesley Publishing
`Company, 1982
`RESERVED
`RESERVED
`U.S. Patent No. 5,797,028 (“Gulick 028”)
`“Accelerated Graphics Port Interface Specification,” Intel
`Corporation, July 31, 1996 (Revision 1.0) (“AGP”)
`VESA Unified Memory Architecture Hardware Specifications
`Proposal,” Version 1.0p (“VUMA”)
`RESERVED
`RESERVED
`U.S. Patent No. 5,432,900 (“Rhodes”)
`
`1026
`1027
`1028
`[NEW]
`1029
`1030
`1031
`1032
`[NEW]
`1033
`[NEW]
`1034
`[NEW]
`1035
`[NEW]
`1036
`[NEW]
`
`1037
`[NEW]
`1038
`[NEW]
`
`Curriculum Vitae of Dr. Harold Stone
`Expert Declaration of Dr. Harold Stone (“Stone ’753 Decl.”)
`Settlement Agreement
`Reply Declaration of Dr. Harold Stone (“Stone Reply Decl.”)
`
`U.S. Patent No. 5,682,484 (“Lambrecht ’484”)
`
`U.S. Patent No. 5,375,068 (“Palmer”)
`
`U.S. Patent No. 5,557,538 (“Retter”)
`
`K. Konstantinides and V. Bhaskaran, “Recent Developements in the
`Design ofImage and Video Processing ICs,” Chapter 2 - VLSI Signal
`Processing Technololgy, Kluwer Academic Press, 1994
`Deposition Transcript of Dr. Mitchell A. Thornton, Ph.D. (June 17,
`2016)
`Information technology – Generic Coding of Moving Pictures and
`Associated Audio Information: Systems, ISO/IEC 13818-1:1996,
`iii
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`1039
`[NEW]
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`Exhibit # Reference Name
`ITU-T Rec. H.222.0 (1996) (“MPEG-2 Standard”)
`Srinath V. Ramaswamy and Gerald D. Miller, “Efficient
`Implementation of the Two Dimensional Discrete Cosine Transform
`for Image Coding applications on the DSP96002 Processor,” Proc. of
`the Midwest Conf. on Circuits and Systems, (IEEE 1993)
`U.S. Patent No. 6,081,750 (“Hoffberg”)
`
`1040
`[NEW]
`1041
`[NEW]
`1042
`[NEW]
`1043
`[NEW]
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`U.S. Patent No. 5,495,481 (“Duckwall”)
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`Microsoft Press Computer Dictionary (3d Ed. 1997)
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`Curriculum Vitae of Dr. Harold Stone (Revised)
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`iv
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`Petitioners’ Reply
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`I.
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`INTRODUCTION
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`The Petition demonstrated it would have been obvious to combine the video
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`decoding techniques of the MPEG-1 Standard with the system of Bowes and that
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`such a combined system satisfied the claims, including the requirement that a
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`decoder receive image data from the main memory. Pet. at 38-49; Ex. 1030 at
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`¶¶153-179. As Dr. Stone explained, “a person having ordinary skill in the art
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`would have understood that Bowes’ DSP 20, as modified by MPEG Standard,
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`would be configured to receive data from main memory subsystem 14
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`corresponding to a current video image to be MPEG-video decoded and to output
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`video data corresponding to the current video image to be displayed via video
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`controllers 131, the current video image to be displayed adapted to be stored in
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`main memory subsystem 14.” Ex. 1030 at ¶163. Patent Owner’s formal response
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`presents nothing to overcome this showing. The claims at issue should therefore
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`be held unpatentable.
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`II. BOWES AND MPEG SATISFY THE CLAIMS
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`A. The Combined System Includes The Idle State Limitation
`
`Claim 1 of the ‘753 Patent requires “an arbiter circuit … configured … to
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`control access to the main memory by: providing access to the main memory for a
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`request for access to the main memory when the arbiter circuit is in an idle state
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`…”. Patent Owner asserts the Bowes/MPEG combination does not satisfy this
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`claim element because Bowes does not disclose an “idle state.” Resp. at 3-5.
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`Patent Owner has never asked for a construction of “idle state,” so it must be
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`given its customary meaning to a person of ordinary skill in the art. See Microsoft
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`Corp. v. Proxyconn, Inc., 789 F.3d 1292, 1297 (Fed. Cir. 2015). Such a person
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`would understand “idle state,” in the context of the 753 Patent, to mean a state in
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`which no component is accessing the memory, or requesting access to the memory.
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`See, e.g., Ex. 1001 at 13:4-6 (“The first state is idle when there is no device
`
`accessing the memory and there are no requests to access the memory.”); see also
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`Microsoft Press Computer Dictionary (3d Ed. 1997) (Ex. 1042) (“idle state … n.
`
`The condition in which a device is operating but is not being used.”); U.S. Patent
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`No. 5,495,481 at 2:59-61 (Ex. 1041) (“All inactive nodes stay in the idle state A0
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`until the occurrence of an internal or external event.”); Ex. 1032 (Dr. Stone: “[A]n
`
`idle state” is, e.g., “when no requests are pending.”).
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`Bowes discloses exactly such a state. In particular, Bowes discloses an
`
`arbitration scheme in which, whenever the non-CPU components of the system are
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`not accessing the memory, or requesting access to the memory “the state of the
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`memory bus assignment defaults to the CPU and remains parked on the CPU until
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`other resources request the memory bus.” Ex. 1001 at 8:30-33; Ex. 1032 at ¶90.
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`Of course, in such a state where the CPU is also not accessing the memory, no
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`component would be accessing the memory, or requesting access to the memory.
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`Ex. 1032 at ¶¶91-93.
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`Patent Owner’s mistake is to assume that the system is not idle because the
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`“assignment” of the bus defaults to the CPU, but never explains why a system
`
`cannot be in a default state that is idle. Moreover, Patent Owner’s argument is
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`based on its expert’s opinions that the arbiter of Bowes monopolizes the bus,
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`employs a statically fixed priority schedule, and “allows a device to control the bus
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`for a '’time slice’ period.” Resp. at 4-5. All of these assertions are irrelevant, since
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`the claim language does not preclude any of them, but also erroneous, as Dr. Stone
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`explains. Ex. 1032 at ¶¶90-93. Moreover, these characterizations of Bowes’
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`disclosure are flawed for the reasons explained below with respect to Patent
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`Owner’s obviousness arguments. See infra § II.D; Ex. 1032 at ¶¶ 75-82.
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`B.
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`The Combined System Discloses the Claimed Video Circuit.
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`1.
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`Bowes Discloses a Video Circuit.
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`Patent Owner asserts that the DSP 20 disclosed in Bowes is not a “video
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`circuit” as claimed, Resp. at 11-19, that Bowes “does not state that the DSP is
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`suitable for video compression and decompression,” id. at 11, and that “a POSA
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`would recognize that a DSP used for image processing is not suitable for video
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`compression and decompression,” id. at 12.
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`However, the Board’s interpretation of the claimed “decoder” is “hardware
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`and/or software that translates data streams into video or audio information.”
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`Paper 14 at 10-11. “Suitability” for decompression is not part of that
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`interpretation, and neither Patent Owner nor its expert dispute that the prior art
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`included “off the shelf” DSPs capable of video compression and decompression
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`pursuant to the MPEG Standard or that a skilled artisan could have implemented
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`the Bowes/MPEG combination using such prior art DSPs. Ex. 1032 (Reply Dec. of
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`Dr. Stone) at ¶¶8-10; see, e.g., Ex. 1006 at Fig. 1; Ex. 2008 at 2; Ex. 1039 at 25.
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`Indeed, at least one commercially available prior art DSP specifically
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`designed for decompressing MPEG video data was the Texas Instruments MVP.
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`See Robert J. Gove, “The MVP: A Highly-Integrated Video Compression Chip,”
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`DCC ’94, Data Compression Conference, Mar. 29-31, 1994, pp. 215-224 (Ex.
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`1006); Ex. 1032 at ¶10. Thus, the skilled artisan implementing the combination of
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`Bowes and MPEG could have simply purchased a suitable DSP “off the shelf,” and
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`would have known to do so. Ex. 1032 at ¶10; see, e.g., U.S. Patent No. 6,081,750
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`(Ex. 1040) at 66:41-49 (filed in June 1995 and noting that a board containing the
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`MVP chip “is available from General Imaging Corp., Billerica Mass….[and] …
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`also available from Wintriss Engineering Corp., San Diego, Calif.”).
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`Bowes, moreover, is directed to a system for carrying out various types of
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`real-time digital signal processing, including “compressed audio (both high fidelity
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`audio and speed), high resolution still images, [and] video ….” Ex. 1003 at 1:35-
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`37. And Bowes states that such technologies “will allow for collaboration at a
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`distance such as by video conferencing,” id. at 1:39-41, which a person of skill
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`would understand to require the translation, including decompression, of data
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`streams into video and audio, Ex. 1032 at ¶¶5-7.
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`Bowes also explains that “[e]ach of these aspects of real-time information
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`processing may require dedicated processors designed for their implementation.
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`However, it is becoming more and more common to use programmable digital
`
`signal processors (DSP) available on the market today.” Ex. 1003 at 1:42-43.
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`Bowes then explains the DSP 20 used with his invention “may be an off-the-shelf
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`DSP such as the AT&T® DSP3210.” Id. at 2:21-22 (emphasis added). Thus, the
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`DSP of Bowes is not limited to an audio or image decoder, but is an “off the shelf”
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`DSP capable of decoding various types of data, including audio and video data
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`used for video conferencing, and intended to be used in a technological context
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`requiring the decompression of video data. Ex. 1032 at ¶¶4-7. Such a device
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`clearly satisfies the claimed “video circuit” and the Board’s interpretation of
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`“decoder.”
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`Patent Owner seeks to avoid these facts by focusing instead on the specific
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`chip Bowes discloses as used in his “preferred embodiment implementation,” the
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`AT&T DSP3210. See Ex. 1003 at 6:28-30; Resp. at 11-18. But the obviousness
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`combination advanced in the Petition and on which the Board instituted trial is not
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`limited to the preferred embodiment of Bowes, but rather relied on the more
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`general description in Bowes of a generic processor referred to as “DSP 20,” see
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`Pet. at 38-40, a fact the Board recognized in its Institution Decision, Paper 14 at 18
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`(noting, in response to Patent Owner’s preferred embodiment argument, that
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`“Petitioner identifies DSP 20 as the decoder …”). Indeed, Bowes explicitly
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`contemplates using DSPs other than DSP3210. Ex. 1003 at 6:40-44 (“[Bowes’
`
`system design] provides for flexibility as newer technology and faster DSPs are
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`developed.”).
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`Moreover, Patent Owner cites no evidence that the DSP3210 could not be
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`used in the system of Bowes to decode MPEG-1 video and the undisputed evidence
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`on this record is that it could. For example, Dr. Stone testifies that “the DSP3210
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`is a high performance computation engine, suitable for numerically intensive
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`algorithms like those required to decode MPEG,” that the internal circuitry of the
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`chip “yield[s] 33.4 MFLOP performance” based on “fast conversion between
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`floating-point and fixed-point representations” and “is therefore perfectly suitable
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`for decoding MPEG-1 data streams.” Ex. 1032 at ¶¶18-19.
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`Patent Owner’s expert, Dr. Thornton, never testified otherwise. Rather,
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`while Dr. Thornton testified that he thought the DSP3210 was not “suitable” or
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`“appropriate,” see, e.g., Ex. 2009 at ¶49, he pointedly refused to testify that it did
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`not satisfy the Board’s interpretation of “decoder” or that it could not be used to
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`decode MPEG video:
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`Q. … Your position is that the DSP disclosed in Bowes is an image
`processor, not a video processor, right?
`
`A. I never said that.
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`*
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`*
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`*
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`You said: It's not appropriate for that because of its architecture.
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`A. Right.
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`Q. But that's different from saying: No, it could not be a video MPEG
`decoder. Right? That is a different statement?
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`A. Yes, that's a different statement.
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`Ex. 1037 at 66:5-12; 67:8-14; 69:2-8 (emphasis added). Thus, the undisputed
`
`record before the Board is that the DSP3210 could be used to decode MPEG-1
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`video in the cited combination.
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`Patent Owner does assert, based on the testimony of its expert, that the
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`DSP3210 would not be “suitable” for MPEG decoding because it has a floating
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`point capability and because its fixed point core would supposedly be too slow to
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`decode MPEG data. Resp. at 13-16; Ex. 2009 at ¶54. As Petitioners’ expert
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`explains, however, “there are several errors” in Dr. Thornton’s analysis, including
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`(1) focusing on a supposed processing requirement for MPEG-2 even though the
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`Board instituted trial on Bowes in view of MPEG-1 (a standard requiring a much
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`lower maximum data rate), Ex. 1032 at ¶21(b); (2) relying on a data rate (524
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`MIPS) inconsistent with the document from which it comes and completely
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`missing from the citation provided to support it, id. at ¶21(a) & (c); (3)
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`understating the capabilities of the DSP3210 by at least 100%, id. at ¶21(f); and (4)
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`ignoring that the processing requirements for converting MPEG data to fixed-point
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`format are “comparable” to the processing requirements for converting MPEG data
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`to floating-point format, id. at ¶¶12-17. As Dr. Stone further explains, a skilled
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`artisan would reasonably have expected the DSP3210 to adequately decode
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`MPEG1 data based on Prof. Thornton’s own exhibits. Id. at ¶¶22-23.
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`Finally, Patent Owner contends that its assertions are confirmed because
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`Apple once produced a product that employed the DSP3210, but used some other
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`chip for decoding video. Resp. at 17-19. However, Patent Owner cites no
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`evidence the Apple Quandra was intended to decode MPEG video, and the
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`document Patent Owner cites demonstrates that Apple did contemplate that the
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`DSP3210 used in that product would decompress video. Ex. 2005 at 82; Ex. 1032
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`at ¶¶22-23.
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`But Patent Owner’s assertions regarding the DSP3210 are beside the point.
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`As demonstrated above, the obviousness combination at issue is not limited to the
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`DSP3210, and there is no question that prior art “off the shelf” devices could
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`decode MPEG-1, such as the prior art Texas Instruments MVP chip, which was
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`specifically designed for decoding MPEG video, Ex. 1006, and the HP chip
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`identified by Prof. Thornton, Ex. 2008. See Ex. 1032 at ¶¶10-11.
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`2.
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`The Bowes/MPEG Combination Uses Shared Memory
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`Patent Owner next argues that even if one would have combined MPEG
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`with the system of Bowes, a person of ordinary skill in the art would not have
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`stored previously decoded images in the main memory of Bowes, but instead
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`would have stored them in the 8K cache memory of the Bowes’ preferred
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`embodiment chip, the AT&T DSP3210. Resp. at 19. Patent Owner then points out
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`that the “8K SRAM cache [] is insufficient to store a previously decoded image
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`frame, [so] if a POSA were to combine Bowes with the MPEG Standard, he would
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`have used a larger dedicated memory with sufficient space to store an image frame
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`and the DSP would retrieve the previously decoded image from this dedicated
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`memory.” Resp. at 20 (emphasis added).
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`But the obviousness combination on which the Board instituted trial is not
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`limited to the preferred embodiment DSP3210 disclosed in Bowes, so Patent
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`Owner’s arguments, limited as they are to a fictional modification of the DSP3210,
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`do not address that combination. Patent Owner is not entitled to change the
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`obviousness combination on which the Board instituted trial. The system of Bowes
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`was specifically designed so that his DSP used the main memory for real time
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`digital signal processing, such as for decoding video data. Ex. 1003 at 4:55-64;
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`6:58-62. This was the system, combined with the MPEG standard, that was the
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`basis for the Board’s institution of trial and against which Patent Owner was
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`required to argue the patentability of its claims. Its arguments directed to some
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`other system are irrelevant.
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`In any event, a skilled artisan would not have modified Bowes as Patent
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`Owner argues, and Patent Owner cites no evidence to the contrary. For example,
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`Patent Owner cites the testimony of Petitioner’s expert Dr. Stone (Resp. at 20), but
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`in the cited passages Dr. Stone opines that a skilled artisan would not use a cache
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`memory to hold image data as Patent Owner contends, no matter how large,
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`because such a system would “not guarantee that you could retrieve it” (Ex. 2006
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`at 159:22-23) and that even if one did the image data “will also be backed up to
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`main memory,” (id. at 163:22-23). Dr. Stone confirms Patent Owner’s error, and
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`explains that “[s]uch a modification of Bowes in that situation would be entirely
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`unreasonable and impractical for several reasons.” Ex. 1032 at ¶¶24-28.
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`Patent Owner cites testimony from its expert Prof. Thornton to putatively
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`support its point, but the cited passage merely parrots Patent Owner’s own
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`response, word-for-word, and cites only the same testimony by Dr. Stone in
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`support. Compare Ex. 2009 at ¶60 with Resp. at 20. Prof. Thornton’s ipse dixit
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`opinion, citing only testimony that contradicts that opinion, cannot support the
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`Board’s fact-finding and should be given little, if any, weight. Cadiocom, LLC v.
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`Robert Bosch Healthcare Sys., Inc., IPR2013-00451, Paper 65 at 28-29 (Jan. 15,
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`2015); 37 C.F.R. § 42.65(a).
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`And there were good reasons why a skilled artisan would not modify Bowes
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`as Patent Owner contends. For example, the cache memory of the DSP3210 is on
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`the same silicon as the chip’s other circuitry, Ex. 2006 (Stone Dep. Tr.) at 149:5-6;
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`Ex. 2001 at 2-2 (Figure 2-1: “On-chip RAM used for kernel storage and
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`program/data cache”), the cache would have to be made several orders of
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`magnitude larger to accomplish what Patent Owner suggests, Ex. 1032 at ¶26
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`(“The sheer complexity and expense of such a redesign, including finding
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`sufficient space on the DSP die to hold such a massive cache, would be
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`prohibitive. A person of ordinary skill in the art would not even consider it.”), and
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`the whole point of the Bowes invention is to use the main memory, Ex. 1003 at
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`4:55-64; 6:58-62; Ex. 1032 at ¶ 27 (citing Ex. 1003 at 2:52-63, 4:49-60). Patent
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`Owner’s argument therefore rests on the implausible assertion that a skilled artisan
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`would have redesigned the entire DSP3210 chip — without any attempt to explain
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`what would motivate such a massive expense and effort, or how one could even
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`find space on the chip for such additional cache memory — when the alternative
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`would be to do exactly what Bowes already says should be done and for which he
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`specifically designed his system: use the main memory.
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`Indeed, Patent Owner’s theory is based on the erroneous analysis of its
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`expert, Prof. Thornton, which concludes that the Bowes DSP 20 includes its own
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`local RAM (it doesn’t; he was looking at the wrong figure, Ex. 1032 at ¶¶33-35),
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`and must have an unmentioned larger memory for bus synchronization purposes
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`and into which it would have stored decoded video frames (it doesn’t, and, even if
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`it did, it need only store a small multiple of the bus width, Ex. 1032 at ¶¶36-41).
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`Moreover, as Dr. Stone explained, one would not use a cache memory alone
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`— of any size — as the only storage for previously decoded MPEG images
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`because one could not be sure the images would remain in the cache until needed,
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`since the cache is also used for other types of data. Ex. 2006 (Stone Dep. Tr.) at
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`158:5-159:23. As Dr. Stone explains:
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`One could enlarge the cache in the AT&T DSP3210, but could not
`reliably store image data in that cache without also storing it in main
`memory and retrieving it from main memory when necessary. My
`deposition testimony was that if you stored the data in the DSP cache,
`you could not reliably retrieve it from the cache because it could have
`been evicted from the cache when you attempted to retrieve it at a
`later time. Accessing another copy in main memory would be
`necessary.
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`Ex. 1032 at ¶32. Thus, the claims would still be satisfied even if the preferred
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`embodiment DSP of Bowes were modified as Patent Owner suggests, since the
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`ability to access image data in main memory would necessarily have been part of
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`such a modified system.
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`3.
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`Bowes Can Retrieve The Data It Stores.
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`Patent Owner also argues that the Bowes DSP can not retrieve from main
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`memory the same data that it stores to main memory. Resp. at 24-26. This
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`extraordinary interpretation of the Bowes DSP — that it is not capable of retrieving
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`data that it had previously written into memory — is based on a single passage in
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`Bowes which describes how a “block write mode” can be used to store data into
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`main memory “so that some other parts of the computer system can utilize it.”
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`Resp. at 25. But the cited sentence actually says that “[i]n many cases it will be
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`necessary to push that data back out to the DRAM so that some other parts of the
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`computer system can utilize it,” and that the block write mode could be used for
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`that purpose. Ex. 1003 at 7:6-12 (emphasis added). Thus, Bowes does not state
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`that his DSP cannot retrieve data it previously wrote to main memory, but instead
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`merely states that the bock write mode can be used “in many cases” where data
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`needs to be written to main memory so other parts of the system can use it. Id.; see
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`Ex. 1032 at ¶¶ 43-44.
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`Patent Owner also argues that Petitioner has not identified any portion of the
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`MPEG Standard that discloses reading image data from memory. Resp. at 26. But
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`the MPEG Standard discloses that previously decoded images must be used to
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`decode at least some video images consistent with the MPEG standard, Ex. 1004 at
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`8, 42-48, 66-67; Fig. 4, and the Petition demonstrated that Bowes discloses a DSP
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`20 that will access main memory as needed to carry out real time signal processing,
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`such as the processing required for video conferencing, Pet. at 40-42. To a person
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`of ordinary skill in the art, the combination therefore discloses a video decoder that
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`writes and reads image data to and from main memory in order to decompress
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`video images pursuant to MPEG. Pet. at 41-42; Ex. 1030 at ¶¶157-163; Ex. 1032
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`at ¶¶ 43-44. That is sufficient to show obviousness, as the Board recognized in its
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`Institution Decision. Paper 12 at 25-28; see also KSR Int’l Co. v. Teleflex Inc., 550
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`U.S. 398, 418 (2007), (“As our precedents make clear, however, the analysis need
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`not seek out precise teachings directed to the specific subject matter of the
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`challenged claim …”).
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`C. Bowes and MPEG Disclose the Claimed Arbiter
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`Patent Owner next argues that “[i]ndependent claim 1 recites an arbiter
`
`circuit configured to control access to the main memory …” and that the “memory
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`controller and arbiter (MCA) 200” of Bowes does not control access to memory.
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`Resp. at 26-32. According to Patent Owner, the MCA of Bowes instead controls
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`access to the memory bus. Id.
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`But the Petition demonstrated that the “memory controller and arbiter
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`(MCA) 200” of Bowes controls access to the memory by controlling access to the
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`bus, Pet. at 43-44; Ex. 1030 at ¶¶166-167; Ex. 1003 at 5:28-29, 6:45-54, 9:64-65,
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`10:2-8, and claim 1 does not recite how access to the memory is controlled, so any
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`technique of controlling access to the memory would satisfy that claim language.
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`Indeed, the Board rejected Patent Owner’s argument in the Institution Decision,
`
`noting that “Patent Owner does not explain, however, why controlling access to the
`
`memory bus does not, in turn, control access to the main/system memory,” Paper
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`12 at 26, and Patent Owner provides no further explanation on this point in its
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`formal response.
`
`Moreover, Patent Owner has never requested a narrowing interpretation of
`
`this claim language; nor could it consistent with the specification. As Dr. Stone
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`explains, the arbiter disclosed in the specification controls access to memory by
`
`controlling access to the bus. Ex. 1032 at ¶¶46-51, 54-61. This is confirmed by,
`
`for example, claim 7 of the related 368 Patent, which requires “an arbiter circuit …
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`for controlling access to the bus,” IPR2015-01500, Ex. 1001 at 17:9-11 (emphasis
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`added), and which the Board must assume is supported by the only arbiter
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`disclosed in the patent. Ex. 1032 at ¶¶63-69. Thus, just as in Bowes, the way the
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`arbiter disclosed in the specification controls access to the memory is by
`
`controlling access to the memory bus. Even under Phillips, the claims must be
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`construed broadly enough to cover that functionality. Phillips v. AWH
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`Corporation, 415 F.3d 1303, 1313 (Fed. Cir. 2005) (“Importantly, the person of
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`ordinary skill in the art is deemed to read the claim term not only in the context of
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`the particular claim in which the disputed term appears, but in the context of the
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`entire patent, including the specification.”).
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`Patent Owner also argues that in Bowes “a device can be allowed to access
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`the peripheral bus without being granted access to the main memory.” Resp. at 28.
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`But controlling access to the memory bus is still one way to control access to the
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`memory, even if the bus may be used for non-memory accessing operations as
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`well. Indeed, as Dr. Stone explains, the specification describes that the bus is also
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`used for non-memory accesses, Ex. 1032 at ¶48 (citing Ex. 1001 at 12:13-14), so
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`the claims cannot be fairly read to distinguish such a system. Vitronics Corp. v.
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`Conceptronic, Inc., 90 F.3d 1576, 1583 (Fed. Cir. 1996) (a claim interpretation that
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`excludes a preferred embodiment “is rarely, if ever, correct”).
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`Patent Owner also asserts that the MCA of Bowes grants access to bus
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`cycles, not to memory requests, Resp. at 28-29, but the claims recite neither. All
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`that is required is an arbiter for controlling access to the memory, and whether that
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`is accomplished by granting access to bus cycles or memory requests is beside the
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`point.
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`Finally, Patent Owner argues that granting access to memory is supposedly
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`more efficient than granting access to a bus, Resp. at 29-31, but that also is
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`irrelevant, even if one were to incorrectly accept it as a distinction from Bowes.
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`The claims recite an arbiter for controlling access to the memory—they do not
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`require that such controlling be carried out in any particular manner.
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`D. Reasons To Combine Bowes And MPEG
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`The Petition demonstrated it would have been obvious to combine Bowes
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`and MPEG because to do would have been the use of known techniques to achieve
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`predictable results, and also because there was a “‘growing need for a common
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`format representing compressed video on various digital storage media,’ which
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`would have motivated on[e] skilled in the art to modify” Bowes to “perform MPEG
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`video decoding.” Pet at 41-42. Patent Owner does not dispute these two reasons to
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`combine included in the Petition. See Resp. at 32-41.
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`Rather, Patent Owner asserts that “the DSP of Bowes is not suitable for
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`video decoding,” citing its earlier argument. Resp. at 33. However, as
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`demonstrated above, Patent Owner’s suitability arguments are focused solely on
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`the preferred embodiment DSP3210 of Bowes, not on the more general “DSP 20”
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`on which trial was instituted, the prior art included other DSPs capable of decoding
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`MPEG video, and the DSP3210 was also capable of performing that function. See
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`supra § II.B.1; Ex. 1032 at ¶¶8-23.
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`Patent Owner also argues that “[a] POSA would not deem using shared
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`memory between a decoder and another device as being advantageous,” Resp. at
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`32-34, citing its expert’s unsupported assertion relating to “power consumption and
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`space saving benefits,” Ex. 2009 at ¶77. Patent Owner is mistaken. Whether
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`“using shared memory between a decoder and another device [is] advantageous” is
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`irrelevant, since Bowes already discloses that functionality. See, e.g., Ex. 1003 at
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`2:50-64; 6:22-26. The issue here is whether there was a reason to combine Bowes
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`and MPEG, which the Petition demonstrated and Patent Owner does not dispute,
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`not whether there was a reason to combine Bowes, MPEG and shared memory.
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`In any event, Bowes discloses that the advantage obtained from using shared
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`memory is avoiding the cost of adding “an expensive block of static random access
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`memory (SRAM)” which “greatly reduces the cost of computer systems.” Ex.
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`1003 at 4:55-64; see also Ex. 1032 at ¶¶72-74. Neither Patent Owner nor its expert
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`dispute this advantage to the use of shared memory.
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`Patent Owner also asserts, block citing seven full pages of testimony, that
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`“Dr. Stone testified, at the time of the filing of the ’753 Patent, a POSA would not
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`have concluded that using a shared memory for video decoding is advantageous as
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`compared to using a dedicated memory.” Resp. at 34. The cited Stone testimony
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`says nothing of the sort. Rather, Dr. Stone explained that a skilled artisan would
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`consider many factors when deciding to use a shared memory and that counsel’s
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`incomplete hypotheticals did not provide enough information to give definitive
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`answers to those questions. See Ex. 2006, 134:23-141:22; see also Ex. 1032 at
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`¶¶31-32. The testimony is irrelevant, in any event, since the question is whether to
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`combine Bowes and MPEG, not whether to combine Bowes and a sha
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