United States Patent
`
`[19]
`
`Lambrecht
`
`[11]
`
`Patent Number:
`
`5,682,484
`
`[45] Date of Patent:
`
`Oct. 23, 1997
`
`US005682484A
`
`[54]
`
`[75]
`
`[73]
`
`[21]
`
`[22]
`
`[5 1]
`[52]
`
`[581
`
`[5 6]
`
`SYSTEM AND METHOD FOR
`TRANSFERRING DATA STREAMS
`SHVIULTANEOUSLY ON MULTIPLE BUSES
`IN A COMPUTER SYSTEM
`
`Inventor: Andy Lambrecht, Austin, Tex.
`
`Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, Calif.
`
`Appl. No.: 559,664
`
`Filed:
`
`Nov. 20, 1995
`
`Int. Cl.‘ ...................................................... G06F 13/00
`U.S. Cl. .......................... 395/308; 395/306; 395/841;
`395/281; 395/154
`Field of Search ................................... .. 395/306, 308,
`395/847, 841, 855, 858, 309, 281, 822,
`840, 162, 163, 200.09, 154, 200.04, 200.12;
`370/8513, 85.9, 85.11; 364/514; 463/43
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`et al.
`
`......................... 395/306
`
`1/1981 Richter ................................... 371/68.1
`4,245,344
`2/1991 Davis et a]. .
`4,991,169
`5,072,442 12/1991 Todd ....................................... 370/265
`5,208,745
`5/1993 Quentin et al. .
`5,245,322
`9/1993 Dinwiddie, Jr. et al. .
`5,274,763 12/1993 Banks.
`5,274,784 12/1993
`5,325,423
`6/1994 Lewis .
`.............................. 395/308
`5,345,566
`9/1994 Tanji et a1.
`5,404,463
`4/1995 McGarvey . ...... ... ..
`.. .... 395/308
`5,404,465
`4/1995 Novakovich et a1.
`.................. 395/308
`5,450,551
`9/1995 Amini et al.
`.
`5,487,167
`1/1996 Dinallo et al.
`
`.
`
`102
`
`5,502,824
`5,519,839
`5,526,017
`5,530,902
`5,533,205
`5,557,757
`5,564,001
`
`3/1996
`Heil ......................................... 395/293
`5/1996
`Culley et al. .
`Wilkie ..................................... 345/115
`6/1996
`McRoberts et al. .
`6/1996
`7/1996
`Blackledge, Jr. et al. .
`9/1996 Gephardt et al.
`.
`10/1996 Lewis.
`
`OTHER PUBLICATIONS
`
`PCI Local Bus —PCI Multimedia Design Guide —Revision
`1.0 —Mar. 29, 1994, 43 pages.
`
`Primary Examiner—Jack B. Harvey
`Assistant Examiner—An'o Etienne
`
`Attomey, Agent, or Firm—Conley, Rose & Tayon; Jeffrey C.
`Hood
`
`[57]
`
`ABSTRACT
`
`A computer system optimized for real-time applications
`which provides increased performance over current com-
`puter architectures. The system includes a standard local
`system bus, such as the PCI bus, and also includes a
`dedicated real-time bus or multimedia bus. Thus multimedia
`devices such as video cards, audio cards, etc., as well as
`communications devices, transfer real-time data through a
`separate bus without requiring arbitration for the PCI bus.
`The computer system of the present invention thus provides
`much greater performance for real-time applications than
`prior systems. In various embodiments, multimedia devices
`transmit addressing and control information for a multime-
`dia bus transfer either over the PCI bus or using a separate
`serial control channel. The multimedia bus may also com-
`-prise separate multimedia channels for diiferent data types.
`Methods are also disclosed for transferring periodic multi-
`media data over flue multimedia bus.
`
`8 Claims, 25 Drawing Sheets
`
`MUL'|1MEJ|A
`DEVICE
`
`1
`Petitioners HTC and LG — Exhibit 1033, p.
`HTC and LG v. PUMA, IPR2()l5—()l5()l
`
`
`
`Petitioners HTC and LG - Exhibit 1033, p. 1
`HTC and LG v. PUMA, IPR2015-01501
`
`

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`Petitioners HTC and LG — Exhibit 1033, p. 2
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 2
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 2 of 25
`
`5,682,484
`
`14-2
`
`7
`
`PCI E)(PANSl0N
`172 BUS INTERFACE
`
`MULTIMEDIA
`BUS
`INTERFACE
`
`FIG. 2
`
`Petitioners HTC and LG — Exhibit 1033, p. 3
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 3
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 3 of 25
`
`5,682,484
`
`
`
`MULTIMEDIA
`
`BUS TRANSFER
`
`
`
`TRANSFER CON'|'ROL
`|NFORMA'I10N ON
`PCI EXPANSION BUS
`
`302
`
`304-
`
`FIG. 3A
`
`Petitioners HTC and LG — Exhibit 1033, p. 4
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`
`TRANSFER DATA
`
`ON MULTIMEDIA
`
`
`
`BUS
`
`Petitioners HTC and LG - Exhibit 1033, p. 4
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. ‘Patent
`
`Oct.28,1997
`
`Sheet 4 of 25
`
`5,682,484
`
`PCI/MUL1'|MEDlA
`BUS TRANSFER
`
`
`
` TRANSFER CONTROL
`
`
`
`
`INFORMA'I1ON ON
`PCI EXPANSION BUS
`
`
`
`
`
`312
`
`314
`
`316
`
` TRANSFER HIGH
`
`BANDWIDTH
`
`TRANSFER FLAG
`
`
`
`
`
`
`
`
`TRANSFER DATA ON
`MULTIMEDIA BUS AND
`
`
`PCI EXPANSION BUS
`
`
`
`
`
`
`DATA LINES
`
`FIG. 3B
`
`Petitioners HTC and LG — Exhibit 1033, p. 5
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 5
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 5 of 25
`
`_
`
`5,682,484
`
`MULTIMEDIA
`BUS TRANSFER
`
`322
`
`TRANSFER CONTROL
`INFORMATION ON
`PCI EXPANSION BUS
`
`324-
`
`TRANSFER
`PERIODIC DATA
`REQUEST
`
`
`
`AVAILABILITY FOR
`PERIODIC DATA
`TRANSFERS
`
`
`
`
`
`SET PERIODIC
`TRANSFER FLAG
`T0 NO A
`
`332
`
`333
`
`SET PERIODIC
`TRANSFER FLAG
`TO YES
`
`334
`
`340
`
`.
`
`PERFORM SINGLE
`TRANSFER
`
`
`
`PERFORM PERIODIC
`TRANSFERS
`
`
`
`FIG. 3C
`
`Petitioners HTC and LG — Exhibit 1033, p. 6
`HTC and LG v. PUMA,iIPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 6
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 6 of 25
`
`5,682,484
`
`Oo 0
`
`.!
`
`._,_§._____--_t____-
`
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`
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`
`Petitioners HTC and LG — Exhibit 1033, p. 7
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 7
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 7 of 25
`
`5,682,484
`
`5 F
`
`IG.
`
`
`CONNECTOR4%?CONNECTOR402/J$REAL—T|MEPCIEXPANSIONBUS
`
`
`
`
`Petitioners HTC and LG — Exhibit 1033, p. 8
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`
`
`400ADD—|NCARD
`
`Petitioners HTC and LG - Exhibit 1033, p. 8
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 8 of 25
`
`5,682,484
`
`
`
`mt.mVe¢
`
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`
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`
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`
`Petitioners HTC and LG — Exhibit 1033, p. 9
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 9
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 9 of 25
`
`5,682,484
`
`.3:«$3.cm:I
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`
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`
`Petitioners HTC and LG — Exhibit 1033, p. 1()
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 10
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 10 of 25
`
`5,682,484
`
`/142A
`
`PCI EXPANSION
`BUS INTERFACE
`
`MULTIMEDIA
`BUS
`INTERFACE
`
`CONTROL
`CHANNEL
`INTERFACE
`
`FIG. 8
`
`Petitioners HTC and LG — Exhibit 1033, p.
`1 1
`HTC and LG v. PUMA,iIPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 11
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 11 of 25
`
`5,682,484
`
`
`
`MULTIMEDIA
`BUS TRANSFER
`
`
`
`
`
`FIG. 9A
`
`Petitioners HTC and LG — Exhibit 1033, p. 12
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`
`
`TRANSFER DATA
`ON MULTIMEDIA
`BUS
`
`
`
`TRANSFER CONTROL
`INFORMATION ON
`
`CONTROL CHANNEL
`
`54-2
`
`54-4-
`
`Petitioners HTC and LG - Exhibit 1033, p. 12
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 12 of 25
`
`5,682,484
`
`MULTIMEDIA
`BUS TRANSFER
`
`552
`
`TRANSFER CONTROL
`, INFORMATION ON
`CONTROL CHANNEL;
`
`
`
`
`
`GAIN ACCESS
`
`
`
`554-
`
`TRANSFER PERIODIC
`DATA REQUEST TO
`RECEMNG DEVICE
`
`556
`
`
`
`
`
`
`RECENING
`EVICE INDICATES
`AVAILABILITY FOR
`
`PERIODIC DATA
`TRANSFERS
`
`
`
`
`SH PERIODIC
`
`TRANSFER FLAG
`T0 NO
`
`
`552
`I
`
`5
`5 3
`
`SE|' PERIODIC
`TRANSFER F|_AG
`TO YES .
`
`PERFORM SINGIE
`
`TRANSFER
`
`564
`
`I
`55°
`
`PERFORM PERIODIC
`TRANSFERS
`
`FIG. 9B
`
`Petitioners HTC and LG — Exhibit 1033, p. 13
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 13
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 13 of 25
`
`5,682,484
`
`9 .
`
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`
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`
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`
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`
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`
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`
`Petitioners HTC and LG — Exhibit 1033, p. 14
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 14
`HTC and LG v. PUMA, IPR2015-01501
`
`
`
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 14 of 25
`
`5,682,484
`
`MULTIMEDIA BUS
`INTERFACE
`
`$174-A
`
`I
`
`TIME
`SLOTTING
`LOGIC
`
`PROGRAMMABLE
`TIME SLOT
`REGISTERS
`
`MM BUS
`
`MONITORING
`
`BUS
`TRANSCENERS
`
`COLUSION
`DETECTION
`LOGIC
`
`FIG.
`
`11
`
`Petitioners HTC and LG — Exhibit 1033, p. 15
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 15
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 15 of 25
`
`5,682,484
`
`N F 9
`
`o_.._
`
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`
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`
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`
`Petitioners HTC and LG — Exhibit 1033, p. 16
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`
`
`._._E_;n_z<mBm_:ommo._.zoE_on_oEz_m_2<mE.mO...n_m._.<oo._._<
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`
`
`
`
`
`
`
`
`
`us:
`
`Petitioners HTC and LG - Exhibit 1033, p. 16
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 16 of 25
`
`5,682,484
`
`2 .
`
`o_:._
`
`mamzo_mz<$n._an.
`
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`
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`
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`
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`
`Petitioners HTC and LG — Exhibit 1033, p. 17
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`EHN3
`
`222
`
`
`
`EOE::8
`
`Petitioners HTC and LG - Exhibit 1033, p. 17
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 17 of 25
`
`5,682,484
`
`DATA BUS
`REGISTERS
`
`
`
`t FIG. 14
`
`Petitioners HTC and LG — Exhibit 1033, p. 18
`HTC and LG v. PUMA,iIPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 18
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`.0.“0
`
`91
`
`/05
`
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`
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`
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`
`am
`
`Petitioners HTC and LG — Exhibit 1033, p. 19
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 19
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 19 of 25
`
`5,682,484
`
`_
`
`mam_zo_mz<n_xm_.8A8.“
`
`<3.
`
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`
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`
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`
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`
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`
`Petitioners HTC and LG — Exhibit 1033, p. 20
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 20
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 20 of 25
`
`5,682,484
`
`MULTIMEDIA MEMORY
`ADDRESS SPACE
`
`GENERAL
`
`ADDRESS
`SPACE
`
`GENERAL
`ADDRESS
`SPACE
`
`FIG. 17
`
`Petitioners HTC and LG — Exhibit 1033, p. 21
`HTC and LG v. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 21
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 21 of 25
`
`5,682,484
`
`502
`
`504
`
`505
`
`508
`
`510
`
`512
`
`514-
`
`516
`
`CPU TRANSFERS
`MULTIMEDIA DATA
`TO_MA|N MEMORY
`
`CPU TRANSFERS
`DATA STRUCTURE TO
`DMA ENGINE
`
`DMA ENGINE PR|0R|'I1ZES
`DATA STRUCTURE
`IN COMMAND QUEUE
`
`DMA ENGINE
`ARBITRATES FOR
`MAIN MEMORY
`
`DMA ENGINE
`TRANSFERS MULTIMEDIA
`DATA FROM MAIN MEMORY
`T0 MULTIMEDIA MEMORY
`
`MULTIMEDIA DEVICE
`ACCESSES MUL'I1MEDIA
`DATA FROM
`
`MULTIMEDIA MEMORY
`
`MULTIMEDIA ENGINE
`PERFORMS OPERATIONS
`USING MULTIMEDIA DATA
`
`MULTIMEDIA ENGINE
`GENERATES MULTIMEDIA
`°”"°”TS
`
`FIG. 18
`
`Petitioners HTC and LG — Exhibit 1033, p. 22
`HTC and LG v. PUMA,iIPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 22
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 22 of 25
`
`5,682,484
`
`3
`
`SH
`
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`Petitioners HTC and LG — Exhibit 1033, p. 23
`HTC and LG V. PUMA, IPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 23
`HTC and LG v. PUMA, IPR2015-01501
`
`
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 23 of 25
`
`5,682,484
`
`902
`
`/
`
`PCI EXPANSION
`BUS INTERFACE
`
`MEMORY
`DATA
`CHANNEL
`|N'l'ERFACE
`
`FIG. 20
`
`Petitioners HTC and LG — Exhibit 1033, p. 24
`HTC and LG v. PUMA,iIPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 24
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`U.S. Patent
`
`Oct. 23, 1997
`
`Sheet 24 of 25
`
`5,682,484
`
`
`
`no:9.3%QNE
`
`
`
`
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`Petitioners HTC and LG — Exhibit 1033, p. 25
`HTC and LG V. PUMA, IPR2()15—()15()1
`
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`Petitioners HTC and LG - Exhibit 1033, p. 25
`HTC and LG v. PUMA, IPR2015-01501
`
`
`

`
`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 25 of 25
`
`5,682,484
`
`1 42D
`
`5
`
`PCI EXPANSION
`BUS MUL11MED|A
`PC] EXPANSION
`Bug |N1'ER|.-ACE MODE INTERFACE
`LOGIC
`
`FIG. 22
`
`Petitioners HTC and LG — Exhibit 1033, p. 26
`HTC and LG v. PUMA,iIPR2()15—()15()1
`
`Petitioners HTC and LG - Exhibit 1033, p. 26
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`1
`SYSTEM AND METHOD FOR
`TRANSFERRING DATA STREAMS
`SIMULTANEOUSLY ON MULTIPLE BUSES
`IN A COMPUTER SYSTEM
`
`FIELD OF THE INVENTION
`
`The present invention relates to a computer system which
`includes a system expansion bus such as the Peripheral
`Component Interconnect (PCI) bus and also includes a
`separate real-time or multimedia bus which transfers peri-
`odic and/or multimedia stream data for increased system
`performance for multimedia and real-time applications.
`
`DESCRIPTION OF THE RELATED ARI‘
`
`Computer architectures generally include a plurality of
`devices interconnected by one or more various buses. For
`example, modern computer systems typically include a CPU
`coupled through bridge logic to main memory. The bridge
`logic also typically couples to a high bandwidth local
`expansion bus or system expansion bus, such as the periph-
`eral component interconnect (PCI) bus or the VESA (Video
`Electronics Standards Association) VL bus. Examples of
`devices which can be coupled to local expansion buses
`include video accelerator cards, audio cards,
`telephony
`cards, SCSI adapters, network interface cards, etc. An older
`type expansion bus is generally coupled to the local expan-
`sion bus for compatibility. Examples of such expansion
`buses included the industry standard architecture (ISA) bus,
`also referred to as the AT bus, the extended industry standard
`architecture (EZISA) bus, or the microchannel architecture
`(MCA) bus. Various devices may be coupled to this second
`expansion bus, including a fax/modern, sound card, etc.
`Personal computer systems were originally developed for
`business applications such as word processing and
`spreadsheets. among others. However, computer systems are
`currently being used to handle a number of real time
`applications,
`including multimedia applications having
`video and audio components, video capture and playback.
`telephony applications, and speech recognition and
`synthesis, among others. These real time applications typi-
`cally require a large amount of system resources and band-
`width.
`
`One problem that has arisen is that computer systems
`originally designed for business applications are not well
`suited for the real-time requirements of modem multimedia
`applications. For example, modem personal computer sys-
`tem architectures still presume that the majority of applica-
`tions executing on the computer system are non real-time
`business applications such as word processing and/or
`spreadsheet applications, which execute primarily on the
`main CPU. In general, computer systems have not tradition-
`ally been designed with multimedia hardware as part of the
`system, and thus the system is not optimized for multimedia
`applications. Rather, multimedia hardware is typically
`designed as an add-in card for optional insertion in an
`expansion bus of the computer system, wherein the expan-
`sion bus is designed for non-realtime applications.
`In many cases, multimedia hardware cards situated on an
`expansion bus do not have the required system bus band-
`width or throughput for multimedia data transfers. For
`example, a multimedia hardware card situated on the PCI
`expansion bus must first arbitrate for control of the PCI bus
`before the device can begin a data transfer or access the
`system memory. In addition, since the computer system
`architecture is not optimized for multimedia, multimedia
`
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`hardware devices are generally required to share bus usage
`with non-real time devices.
`
`Also, multimedia hardware devices generally do not make
`eflicient usage of system resources. As an example, multi-
`media hardware cards typically include their own memory in
`addition to system memory. For example, video accelerator
`cards are typically configured with one to four Megabytes of
`video RAM. Audio cards, video capture cards, and other
`multimedia cards are also generally configured with dedi-
`cated on-board memory. This requirement of additional
`memory adds undesirable cost to the system.
`As multimedia applications become more prevalent, mul-
`timedia hardware will correspondingly become essential
`components in personal computer systems. Therefore, an
`improved computer system architecture is desired which is
`optimized for real-time multimedia and communications
`applications as well as for non-realtime applications. In
`addition,
`improved methods are desired for transferring
`real-time data between multimedia devices.
`
`Applicant is aware of two new graphics standards from
`the Video Electronics Standards Association (VESA) which
`are designed to improve digital video transfers in computer
`systems. These two standards are referred to as the VESA
`advanced feature connector (VAFC) and the VESA media
`channel (VMC). Athird standard has been proposed by Intel
`and ATI referred to as the shared frame buffer interconnect
`(SFBI).
`The VAFC standard is a 32 bit replacement for prior 8 bit
`VGA connectors which supports video at much higher
`resolutions and in better color. The VMC standard also oifers
`a 32 data path and supports up to 15 video streams simul-
`taneously. The VMC standard comprises a dedicated chan-
`nel for real-time video, and peripherals can communicate
`independently Without slowing the system CPU. The VMC
`standard also decouples the memory subsystem from the
`video transfer specification, allowing graphics board manu-
`facturers to offer a variety of boards with differing types of
`graphics memory.
`The SFBI standard combines frame buffers and memory
`use by each multimedia system into a single shared memory
`pool. The SFBI standard also includes a protocol for arbi-
`trating among devices attempting to access the memory.
`However, one drawback to this standard is that the standard
`is designed to maintain all of the components on a single
`board. The SFBI standard does not provide an external
`feature connector unless SFBI cards are connected to
`another device over the host bus. In addition, SFBI cards can
`include a VMC or VAFC connector for connecting to a VMC
`or VAFC card.
`
`SUMMARY OF THE INVENTION
`
`The present invention comprises a computer system and
`method optimized for real-time applications which provides
`increased performance over current computer architectures.
`The system preferably includes a standard local expansion
`bus or system bus, such as the PCI bus, and also includes a
`dedicated real-time bus or multimedia bus. Thus multimedia
`devices, such as video devices, audio devices, etc., as well
`as communications devices, transfer real-time data through
`a separate bus without requiring arbitration for or usage of
`the PCI bus. The computer system of the present invention
`thus provides much greater performance for real-time appli-
`cations than prior systems. In an alternate embodiment, the
`computer system only includes one or more dedicated
`real-time buses which replace the PCI bus.
`In the preferred embodiment. the computer system com-
`prises a CPU coupled through chip set or bridge logic to
`
`Petitioners HTC and LG — Exhibit 1033, p. 27
`HTC and LG v. PUMA,iIPR2()l5—()l5()l
`
`Petitioners HTC and LG - Exhibit 1033, p. 27
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`5,682,484
`
`3
`main memory. The bridge logic couples to a local bus such
`as the PCI bus. The computer system also includes a
`real-tirne expansion bus or multimedia bus for transferring
`real-time or multimedia data. A plurality of multimedia
`devices. such video devices, audio devices, MPEG encoders
`and/or decoders, and/or communications devices, are
`coupled to each of the PCI bus and the multimedia bus. In
`one embodiment, the multimedia bus transfers only periodic
`stream data, such as audio data at 44,100 samples per
`second, video data at 30 frames per second, or real-time
`communication streams at rates dependent on the transport
`media.
`
`The computer system preferably includes a plurality of
`PCI expansion bus connector slots connected to the PCI bus
`for receiving add-in devices, and also preferably comprises
`one or more multimedia bus connector slots corresponding
`to respective ones of the PCI expansion bus connector slots.
`Thus, in one embodiment, the PCI bus and the multimedia
`bus are comprised on the motherboard and include respec-
`tive connector slots for receiving add-in cards. Multimedia
`device expansion cards each include two connectors which
`correspond to the PCI bus and the multimedia bus.
`Alternatively, the multimedia devices are comprised directly
`on the motherboard and connect directly to the PCI bus and
`the multimedia bus, and connector slots are not used.
`In one embodiment, the multimedia bus comprises pri-
`marily or only data lines.
`In this embodiment, control
`information for the periodic stream transfers is transferred
`on the PCI bus by a sourcing device, or is transferred by the
`CPU to the bridge logic. Thus multimedia data transfers
`initially involve the transfer of control or setup information
`on the PCI bus, or transfer of control or setup information by
`the CPU, to set up the transfer. This transfer of control
`information is followed by the transfer of the periodic data
`streams on the multimedia bus. Alternatively, once control!
`setup information has been used to set up the transfer, the
`periodic data stream may occupy both the PCI data lines and
`the multimedia bus for increased data throughput. In this
`embodiment, the transferring or source device transfers a
`multiple bus transfer request which requests simultaneous
`transfers on both the PCI bus and the multimedia bus. If the
`
`multiple bus transfer request is accepted, then the source
`device transfers data on both the PCI bus and the multimedia
`bus.
`
`invention further includes an improved
`The present
`method for transferring periodic data streams on a bus in the
`computer system, such as periodic video streams or periodic
`audio streams. According to this method, the transferring
`device first transmits addressing and control information to
`set up the transfer. The transferring device then transmits a
`periodic transfer data request to the receiving device. The
`periodic transfer data request includes information regarding
`the frequency and amount of the periodic transfers. The
`receiving device detennines if it can guarantee availability at
`the periodic time frequencies requested by the transferring
`device. If the receiving device indicates availability for the
`periodic transfers. the transferring device sets a periodic
`transfer flag. The transferring device then perfonns the
`periodic transfers to the receiving device at the specified
`time frequency. If the receiving device does not indicate
`availability for the periodic transfers. the transferring device
`performs only a single transfer and is required to transfer
`control information at the beginning of each subsequent
`periodic transfer.
`In a second embodiment. the computer system includes a
`dedicated control channel separate from the PCI bus and the
`multimedia bus for transferring control
`information for
`
`4
`multimedia bus data transfers. The control channel is pref-
`erably a serial bus. Alternatively, the control channel is a
`4-bit, 8-bit or 16-bit bus. Thus a multimedia data transfer
`initially involves the transfer of control infonnation on the
`dedicated control channel followed by the transfer of the
`periodic data streams on the multimedia bus.
`In a third embodiment, the multimedia bus comprises
`separate channels for ditferent data types. In the preferred
`embodiment, the computer system includes a first video data
`channel for. transferring video and/or graphics information,
`a second audio channel for transfening audio information,
`and optionally a third channel for transferring communica-
`tions information. The video channel is preferably 32 bits,
`24 bits, or 16 bits. Alternatively, the video channel is an 8-bit
`bus or a very high speed serial bus. The audio channel is
`preferably 16 bits or 8 bits. Alternatively, the audio channel
`is also a 32-bit bus or a very high speed serial bus. The
`communications channel is also preferably either 16 or 8
`bits. This third embodiment may use the PCI bus for control
`information transfers, or may use a separate control channel
`separate from the PCI bus and the multimedia bus for
`transferring control
`information for the periodic stream
`transfers.
`
`In a fourth embodiment, each multimedia device has a
`high speed link directly to system memory, which is pref-
`erably single or multiple ported memory. These individual
`links are preferably high speed serial interconnects but,
`alternatively, may be 4-bit, 8-bit, 16-bit, 24-bit, 32-bit,
`64-bit or any combination thereof. In this embodiment,
`intelligent bulfering is preferably implemented within the
`core logic, and arbitration for access to main memory is
`preferably implemented within the core logic. Each of the
`multimedia devices uses its dedicated memory data channel
`to perform data accesses and transfers directly to the main
`memory, bypassing PCI bus arbitration and PCI bus cycles.
`Alternatively, each of the multimedia devices includes a
`high speed memory channel directly to the memory con-
`troller in the core logic for accessing system memory.
`In a fifth embodiment, the multimedia bus is time sliced
`wherein time slices or time slots are allocated in proportion
`to the required bandwidth. In one embodiment, the time
`slices are each a constant size and a number of the equal
`sized time slots are allocated to respective data streams in
`proportion to the required bandwidth. In this embodiment,
`for example, video data streams may be allocated more time
`slots than audio data streams because of the increased data
`transfer band width requirements of video streams.
`Alternatively, the time slots are not equally sized, but rather
`are dynamically sized or allocated to data streams in pro-
`portion to the required bandwidth.
`In a sixth embodiment, multimedia devices that connect
`to the multimedia bus include intelligent controller circuitry
`which includes knowledge of the respective time slice
`allocated to the multimedia device. In this embodiment,
`arbitration for the multimedia bus is not required. Rather, a
`multimedia device which is a transmitter of video data
`monitors the bus and includes controller circuitry which
`begins transmitting the video data when the device’s respec-
`tive time slot occurs. A corresponding receiver device also
`knows that the current time slot is a video time slot and
`monitors the bus to receive the data.
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`In this embodiment, the interface circuitry of each of the
`multimedia devices are programmed at boot time for a static
`allocation of time slots. Alternatively, the interface circuitry
`in the multimedia devices is dynamically programmed by a
`central controller dependent upon the mix of real-time
`
`Petitioners HTC and LG — Exhibit 1033, p. 28
`HTC and LG v. PUMA,iIPR2()l5—()l5()l
`
`Petitioners HTC and LG - Exhibit 1033, p. 28
`HTC and LG v. PUMA, IPR2015-01501
`
`

`
`5,682,484
`
`5
`
`processes and applications and the corresponding data trans-
`fer bandwidth requirements. For example, the CPU may
`program each of the multimedia devices with a respective
`time slot at power-on. Alternatively, the CPU dynamically or
`heuristically allocates time slot based on bandwidth require-
`ments.
`
`In one embodiment of the invention, the computer system
`includes a centralized multimedia I/O processor which oper-
`ates to direct or “pull” data stream information through the
`system. The multimedia I/O processor is programmed with
`lmowledge of the various data rates, data periodicity, data
`sources and destinations, and coordinates all transfers within
`the system. Thus,
`the multimedia I/O processor creates
`connections between two or more devices and sets up
`transfers between devices. The centralized multimedia I/O
`
`processor of the present invention may be used exclusively
`in the multimedia bus or may be used on a standard PCI bus.
`In one embodiment, the centralized multimedia I/O pro-
`cessor byte slices the multimedia bus to allow different data
`streams to use different byte channels simultaneously. Thus
`the byte sliced multimedia bus allows different peripherals
`to share the bus simultaneously. The centralized multimedia
`I/O processor thus may assign one data stream to a subset of
`the total byte lanes on the multimedia bus. and fill the unused
`byte lanes with another data stream. For example, with a
`32-bit multimedia bus, if an audio data stream is only 16 bits
`wide and thus only uses half of the multimedia data bus, the
`multimedia bus intelligently allows data stream transfers on
`the unused bits of the bus. In this embodiment, the central-
`ized multimedia I/O processor includes knowledge of the
`destinations and allows transfers to occur without addressing
`information.
`
`In one embodiment of the invention, the computer system
`includes a multimedia memory coupled to each of the PCI
`local expansion bus and the real-time bus. One or more
`multimedia devices may be coupled to the PCI local expan-
`sion bus and the real-time bus. Each of these devices
`accesses the multimedia memory to retrieve necessary code
`and data to perform respective operations. The multimedia
`devices preferably include an arbitration protocol for access-
`ing the multimedia memory using the real-time bus.
`In one embodiment,
`the system bus (preferably PCI)
`implements a new mode of operation specifically for real-
`t:ime transfers. A signal (or signals) is used to indicate that
`the system bus should be placed in a special real time mode.
`When not in special real time mode, the system bus operates
`as usual. The real time mode is optimized for the transfer of
`high bandwidth real-time information.
`Therefore. the present invention comprises a novel com-
`puter system architecture and method which provides one or
`more real-time or multimedia buses, optionally with a local
`expansion bus, to increase the performance of real-time
`peripherals and applications. The multimedia bus of the
`present invention provides improved data transfers perfor-
`mance and throughput for real-time devices. The various
`embodiments discussed above may be combined in various
`ways for optimum real-time and/or multimedia perfor-
`mance.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A better understanding of the present invention can be
`obtained when the following detailed description of the
`preferred embodiment is considered in conjunction with the
`following drawings, in which:
`FIG. 1 is a block diagram of a computer system including
`a local expansion bus and a real-time bus or multimedia bus
`according to the present invention;
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`FIG. 2 is a block diagram of a multimedia device in the
`computer system of FIG. 1;
`FIG. 3A is a flowchart diagram illustrating a multimedia
`bus transfer which uses the PCI bus for control and address-
`ing information;
`FIG. 3B is a flowchart diagram illustrating a multimedia
`bus transfer which uses both the PCI bus data lines and the
`multimedia bus data lines for improved bandwidth;
`FIG. 3C is a flowchart diagram illustrating a multimedia
`bus transfer optimized for periodic data transfers;
`FIG. 4 is a block diagram of the motherboard of the
`computer system of FIG. 1;
`FIG. 5 illustrates a modular add-in card including a local
`expansion bus connector and a multimedia bus connector
`according to the present invention