UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION, HTC AMERICA, INC.,
`LG ELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.,
`and SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01501
`Patent 7,777,753
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
`
`Page 1 of 68
`
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION, HTC AMERICA, INC.,
`LG ELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.,
`and SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01501
`Patent 7,777,753
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
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`Page 1 of 68
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`
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`I.
`
`Introduction
`I am over the age of eighteen (18) and otherwise competent to make
`1.
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`this declaration.
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`2. My name is Mitchell Aaron Thornton. I am offering this declaration
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`in the matter listed above on behalf of Parthenon Unified Memory Architecture
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`LLC and at the behest of their attorneys Ahmad, Zavitsanos, Anaipakos, Alavi &
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`Mensing P.C. I am being compensated at my usual rate and my compensation is
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`not dependent on any opinions that I may take in this matter, any testimony, or any
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`intermediate or final resolution in the matter.
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`3.
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`I understand that the Board has issued an institution Decision in the
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`above-captioned IPR concluding that the Petitioner has established a reasonable
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`likelihood of success with respect to the following grounds (collectively “Instituted
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`Grounds”):
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`a. Obviousness of claims 1 and 2 over Bowes and the MPEG Standard;
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`b. Obviousness of claim 3 over Bowes, the MPEG Standard and Stearns;
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`and
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`c. Obviousness of claim 4 over Bowes, the MPEG Standard and
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`Shanley.
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`4.
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`This declaration is directed to an analysis of these Instituted Grounds.
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`II. My Background and Qualifications
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`1
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`5.
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`I earned a Bachelor of Science degree in Electrical Engineering from
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`Oklahoma State University in 1985. In 1990, I earned a Masters of Science degree
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`in Electrical Engineering from the University of Texas at Arlington. In 1993, I
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`earned a Masters of Science degree in Computer Science from Southern Methodist
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`University. I earned a Ph.D. in Computer Engineering from Southern Methodist
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`University in 1995. I am a Licensed Professional Engineer in the states of Texas,
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`Mississippi, and Arkansas. I also hold a Commercial General Radiotelephone
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`Operator License (GROL) with Ship Radar endorsement issued by the Federal
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`Communications Commission (FCC).
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`6.
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`I am currently the Cecil H. Green Chair of Engineering and Professor
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`in the Department of Computer Science and Engineering and in the Department of
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`Electrical Engineering at Southern Methodist University. Prior to 2002, I served as
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`a faculty member at Mississippi State University in the Department of Electrical
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`and Computer Engineering from 1999 through 2002. I served as a faculty member
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`at the University of Arkansas from 1995 through 1999 in the Department of
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`Computer Systems Engineering. In my university positions, my responsibilities
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`are research, teaching, and providing service in my profession. My teaching and
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`research area of expertise is generally in the area of computer engineering where I
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`specialize in hardware design for information processing systems.
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`7.
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`In addition to my academic rank of professor, I am also the Associate
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`and Technical Director of the Darwin Deason Institute for Cyber Security at
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`Southern Methodist University. The Institute mission is to advance the science,
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`policy, application and education of cyber security through basic and problem-
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`driven, interdisciplinary research. As Associate and Technical Director, I am
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`responsible for the coordination and oversight of all research projects within the
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`auspices of this multi-million dollar endowed research Institute that is comprised
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`of 11 principal investigators and their associated research teams. In this role, I am
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`routinely involved with several different state-of-the-art projects regarding the
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`technical aspects of information processing system processes, methods, software,
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`and hardware.
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`8.
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`Prior to my academic career, I was employed in the commercial sector
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`as an engineer. I was employed full-time at E-Systems, Inc. (now L3
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`Communications) in Greenville, Texas from 1986 through 1991 and resigned from
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`my position as Senior Electronic Systems Engineer in 1991 to pursue full-time
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`graduate studies in Computer Science and Computer Engineering. My duties at E-
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`Systems involved the design, analysis, implementation, and test of a variety of
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`different electronic systems including various information processing systems
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`centered around signal processing, data transmission and processing, and
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`communications systems. The communications systems I was involved with
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`3
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`processed a variety of different types of signals including data, audio, and video
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`systems. These systems were comprised of components such as receivers,
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`transmitters, computers, and special purpose circuitry.
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`9.
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`During the time I was in graduate school pursuing the Ph.D. degree, I
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`also worked part-time and full-time during the summer of 1992 at a commercial
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`integrated circuit (IC) design company named the Cyrix Corporation. At Cyrix, I
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`was a member of a design team that ultimately produced a microprocessor that is
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`compatible with the Intel Pentium. My duties included the design of the bus
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`controller and memory interface circuitry for this IC.
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`10. My practice and research covers a range of topics centered around
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`hardware design and analysis including secure circuit and embedded system
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`design, electronic design automation (EDA) methods, and algorithms for quantum,
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`classical digital systems, and large systems design. I have also maintained an
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`independent professional engineering practice since 1993 as a sole proprietor that
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`is a registered engineering firm in the state of Texas.
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`11.
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`I am a named inventor on three (3) issued patents and two (2) patent
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`applications under consideration at the USPTO. I have authored or coauthored over
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`200 scholarly publications in the fields of electrical engineering and computer
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`4
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`science.
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`12. My curriculum vitae and testimony list are included in Appendix A to
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`this declaration, which more fully sets forth my qualifications.
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`III. Documents Considered
`In addition to my knowledge and experience, I have reviewed and
`13.
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`relied upon the following materials in performing my analysis:
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`• The `753 Patent (including the publications incorporated therein) and its
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`file history;
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`• Petition for Inter Partes Review of U.S. Patent No. 7,777,753 including
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`the exhibits [IPR2015-1501];
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`• Patent Owner’s Preliminary Response in IPR2015-1501;
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`• Decision on Institution in IPR2015-1501;
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`• U.S. Patent No. 5,546,547 to Bowes [Ex. 1003] (“Bowes”);
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`• MPEG Standard [Ex. 1004] (also referred to as “MPEG”);
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`• U.S Patent No. 5,774,676 to Stearns [Ex. 1007] (“Stearns”);
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`• T. Shanley et al., “PCI System Architecture,” Addison-Wedley Publ’g
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`Co. (3rd ed. Feb. 1995) [Ex. 1019] (“Shanley”);
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`• Declaration of Harold S. Stone, Phd. [Ex. 1030] (“Stone Decl.”);
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`• DSP3210 Information Manual [Ex. 2001];
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`5
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`• AT&T DSP3210 Digital Signal Processor The Multimedia Solution,
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`Data Sheet, AT&T Microelectronics, March 1993
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`[Ex. 2003]
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`(“DSP3210 Datasheet”);
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`• Developer Note – Macintosh Quadra 840AV and Macintosh Centris
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`660AV Computers [Ex. 2005] (“Quadra Developer Notes”);
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`• Deposition testimony of Harold S. Stone, Phd. dated March 17, 2016
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`[Ex. 2006] (“Stone Depo.”);
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`• Excerpts from Stone, H.S., High-Performance Computer Architecture,
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`Addison-Wesley Publishing Company, Reading, Massachusetts, 1993,
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`ISBN 0-201-52688-3 [Ex. 2007];
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`• Kitson, F. and Bhaskaran, V., Interactive Video from Desktops to
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`Settops, HPL-95-58, Hewlett-Packard white paper, June 1995 [Ex.
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`2008].
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`IV. Summary of Opinions
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`14. As detailed below, it is my opinion that the challenged independent
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`claims are not obvious in view of Bowes and the MPEG Standard and that the
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`challenged dependent claims are also not obvious for at least the same reasons.
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`V. Legal Standards
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`6
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`15.
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`I am not an attorney or patent agent, and thus, I have relied upon
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`certain legal factors that have been explained to me. Some of these, which form the
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`legal framework for the opinions I am providing, are summarized below.
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`16.
`
`I understand that claims are to be interpreted from the perspective of
`
`one of ordinary skill in the art. I understand that in determining the level of
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`ordinary skill in the art, the following factors may be considered: (1) the
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`educational level of the inventor; (2) type of problems encountered in the art; (3)
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`prior art solutions to those problems; (4) rapidity with which innovations are made;
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`(5) sophistication of the technology; and (6) educational level of active workers in
`
`the field.
`
`17.
`
`I understand from reading the Board’s decision that in this inter partes
`
`review, claim terms are to be given their broadest reasonable construction in light
`
`of the patent specification. I also understand that claim terms are presumed to be
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`given their ordinary and customary meaning as would be understood by one of
`
`ordinary skill in the art. Furthermore, I understand that an inventor may provide a
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`contrary definition of a term in the specification, if it is done with reasonable
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`clarity, deliberateness, and precision. I also understand that care must be taken not
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`to read a particular embodiment appearing in the specification into the claim if the
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`claim language is broader than the embodiment.
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`18.
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`I understand that a claim may be invalid as anticipated or as being
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`obvious. I understand that anticipation is not at issue in this IPR and therefore, my
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`analysis is focused on the obviousness issue.
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`19.
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`I understand that the obviousness standard is defined in the patent
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`statute (35 U.S.C. § 103(a)). I also understand that a claim is not patentable and is
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`obvious if the differences between a claim and the prior art are such that the
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`claimed subject matter as a whole would have been obvious to a person having
`
`ordinary skill in the art at the time the invention was made. I understand that this
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`inquiry involves examination of number of factors including: (1) determining the
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`scope and content of the prior art; (2) ascertaining the differences between the
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`claim and the prior art; (3) resolving the level of ordinary skill in the prior art; and
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`(4) considering any secondary or objective evidence of non-obviousness. I
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`understand that secondary or objective evidence of non-obviousness include
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`factors such as commercial success, long felt need for the invention, and failure of
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`others.
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`20.
`
`I understand that an obviousness analysis involves comparing a claim
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`to the prior art to determine whether the claimed invention would have been
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`obvious to a Person of Ordinary Skill in the Art (“POSA”) in view of the prior art,
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`and in light of the general knowledge in the art. I also understand when a POSA
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`would have reached the claimed invention through routine experimentation, the
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`invention may be deemed obvious.
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`21.
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`I also understand that obviousness can be established by combining or
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`modifying the teachings of the prior art to achieve the claimed invention. It is also
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`my understanding that where this is a reason to modify or combine the prior art to
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`achieve the claimed invention, there must also be a reasonable expectation of
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`success in so doing. I understand that the reason to combine prior art references
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`can come from a variety of sources, not just the prior art itself or the specific
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`problem the patentee was trying to solve. And I understand that the references
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`themselves need not provide a specific hint or suggestion of the alteration needed
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`to arrive at the claimed invention; the analysis may include recourse to logic,
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`judgment, and common sense available to a person of ordinary skill that does not
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`necessarily require explication in any reference. Finally, it is my understanding that
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`obviousness can be established by choosing from a finite number of identified,
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`predictable solutions, with a reasonable expectation of success.
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`22.
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`I further understand that a patent composed of several elements is not
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`proved obvious merely by demonstrating that each of its elements was,
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`independently, known in the prior art. I further understand that a showing of a
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`suggestion, teaching, or motivation to combine the prior art references is an
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`essential evidentiary component of an obviousness conclusion. I further understand
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`that a claim is not obvious if the references relied upon in a proposed combination
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`teach away from the claimed combination in a way that would deter any
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`investigation into such a combination. For instance, it is my understanding that a
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`reference teaches way from a combination when using it in that combination would
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`produce an inoperative result.
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`VI. Level of Ordinary Skill in the Art
`In formulating my opinions, I have also considered the viewpoint of a
`23.
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`person of ordinary skill in the art (“POSA”) at the time of the filing of the `753
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`Patent.
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`24.
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`I understand that Dr. Stone has opined that a person of ordinary skill
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`in the art as of the effective filing date of the `753 Patent would have held an
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`accredited Bachelor’s degree in Electrical Engineering and/or Computer Science
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`and/or Computer Engineering and had three years’ experience in the fields of data
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`compression and overall computer system architecture. [Stone Decl., Ex 1030,
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`¶79].
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`25. Based upon my knowledge of this field, I conclude that a person of
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`ordinary skill in this art at the time of the filing of the `753 Patent, and for that
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`matter, at all subsequent times through the present, would have held at least an
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`accredited Bachelor’s degree in electrical engineering, computer engineering, or an
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`equivalent degree in a related discipline from an accredited institution of higher
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`10
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`learning and at least two to three years’ experience in signal and/or image
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`processing, computer architecture at both the systems and micro-architecture level.
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`In lieu of two to three years of experience, a person of ordinary skill in the art may
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`hold, in addition to a Bachelor’s degree as described above, a Master’s or other
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`graduate degree in electrical or computer engineering with a focus in computer
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`architecture and signal and/or image processing with one year of relevant
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`experience.
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`26. My analysis was performed from the perspective of such a person. If
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`I were to apply the level of ordinary skill as proffered by Dr. Stone in his
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`declaration, my analysis and conclusions would remain unchanged.
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`VII. State of the Prior Art and the `753 Patent
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`27. The computer memory storage requirements of a digital representation
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`of an uncompressed image is dependent on its resolution, color depth, and size in
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`pixels. Video files are comprised of sequences of images that are further enhanced
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`with a corresponding audio track to accompany them. As a result, a video file
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`quickly becomes large in size. The transmission of uncompressed video files is
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`prohibitively expensive.
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`28. Accordingly, video files are typically compressed at a transmitting
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`device. The compressed file is then transmitted to a receiving device where it is
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`decompressed. To that end, an encoder at the transmitter compresses the video file
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`and a decoder decompresses the file received at the receiver in order to retrieve the
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`original video and audio data. In order to ensure compatibility between devices, a
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`number of standards for encoding and decoding video files were developed. One of
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`those standards was developed by the Motion Picture Expert Group (“MPEG”) and
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`has been adapted as a standard for the communication of video.
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`29. Typically, a decoder requires its own dedicated memory. For instance,
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`traditional MPEG decoders require a 2 Mbyte dedicated memory which is utilized
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`during the decoding process. This dedicated memory is necessary to allow the
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`decoder to decode images in real-time without dropping frames which would result
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`in a deterioration of the video quality at the receiver. This prior art implementation
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`is shown, for example, in Figure 1c of the `753 Patent.
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`30.
`
` The `753 Patent discloses an improved system where the decoder and
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`another device (e.g., a microprocessor) share the main system memory. This
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`improved configuration eliminates the need for a dedicated decoder memory and
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`results in a more efficient utilization of main system memory by ensuring that
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`memory resources not used by the decoder remain available to other system
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`components.
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`VIII. Claim Construction
`I understand that the Board has construed the term “decoder” to mean
`31.
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`“hardware and/or software that translates data streams into video or audio
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`information.” (Institution Decision, Paper 12, at 10-11).
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`32.
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`I have used the Board’s construction of the term “decoder” in
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`performing my analysis. I have used the plain and ordinary meaning of the
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`remaining claim terms when performing my analysis.
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`IX. Analysis of Instituted Grounds
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`A. Claims 1 and 2
`
`1) Bowes and the MPEG Standard fail to disclose “providing access to
`the main memory for a request for access to the main memory when
`the arbiter circuit is in an idle state”
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`33. The arbiter circuit of Bowes does not have an “idle state.” Therefore,
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`in my opinion Bowes does not disclose this limitation.
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`34. The `753 Patent discloses an arbiter which has three states, one of
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`which is the idle state. [`753 Pat., 13:4-6]. In the idle state, “there is no device
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`accessing the memory and there are no requests to access the memory.” [`753 Pat.,
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`13:4-6] (emphasis added). Bowes does not disclose such an idle state. Instead, in
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`Bowes, “the state of the memory bus assignment defaults to the CPU and remains
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`parked on the CPU until other resources request the memory bus.” [Bowes, 8:30-
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`33]. Accordingly, in Bowes, even if there are no requests to access the memory,
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`the CPU is given access to the memory. Therefore, the arbiter of Bowes does not
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`have an “idle state” in which no device accesses the memory.
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`35. The use of the recited “idle state” is beneficial compared to the
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`arbitration scheme of Bowes. A POSA would understand that the `753 memory
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`arbiter being in an “idle state” allows for bus traffic that does not require memory
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`access to occur in an unimpeded fashion. As an example, a video decoder could
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`receive data from a peripheral device such as a DVD drive directly via the bus
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`while the `753 memory arbiter was in the “idle state.” Thus, a POSA would
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`appreciate that the `753 “idle state” aids in ensuring that no device monopolizes the
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`bus starving the other devices. [`753 Pat., 5:66-4:5]. In contrast, the Bowes bus
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`arbiter would not allow such bus traffic to occur until such time that the statically
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`fixed priority schedule according to the Bowes arbiter state diagram allows a
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`device to control the bus for a “time slice” period. The Bowes bus arbiter causes
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`the bus to be monopolized during the “time slice” period that the bus is assigned to
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`a particular bus master. [Bowes Pat., 8:23-27; 8:45-56; 9:11-15; FIG. 3].
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`2) Bowes and MPEG Standard fail to disclose wherein the video circuit
`is further configured to receive data from the main memory
`corresponding to at least one previously decoded video image
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`36. Figure 1c of the `753 Patent depicts a system having a decoder in
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`accordance with the prior art.
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`37. The system includes a number of components that are connected to a
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`peripheral bus (170) via interfaces. [`753 Pat., 2:56-63]. A Central Processing Unit
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`(“CPU”) (152) communicates with the peripheral bus (170) through an interface
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`circuit (146) enabling the main memory (168) of the system to be shared between
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`the CPU (152) and other peripherals that may require it. [`753 Pat., 2:64-67].
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`Typically, one of the peripherals connected to the peripheral bus (170) as a master
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`is a decoder (10). [`753 Pat., 3:1-3]. The decoder (10) receives encoded or
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`compressed data from a source peripheral (22) and decodes that data. For instance,
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`if the data to be decoded is image data, the decoder then directs the decoded
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`images to a video controller (120) for display. [`753 Pat., 3:3-14].
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`38. Traditionally, the decoder (10) included its own dedicated memory
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`(22) which was divided into three image area buffers (M1, M2, M3) and a
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`Compressed Data Buffer (CDB) and the compressed image to be decoded was
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`stored in the CDB before it was decoded. [`753 Pat., 3:14-19]. Typically, the
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`decoding of images under the MPEG Standard involves processing of “I”, “P” and
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`“B” frames. “I” frames are so called “intra” image frames whose compressed data
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`directly corresponds to an actual image. [`753 Pat., 3:31-32]. “P” frames are so
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`called “predicted” image frames the construction of which uses pixel blocks of a
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`previously decoded image frame. [`753 Pat., 3:23-25]. Finally, “B” frames are so
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`called “bidirectional” image frames the construction of which uses pixel blocks
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`from two previously decoded images. [`753 Pat., 3:26-28]. Accordingly, the “I”
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`and “P” image frames are used to reconstruct subsequent “P” and “B” frames while
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`“B” frames are not used to reconstruct subsequent image frames. [`753 Pat., 3:28-
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`30].
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`39. Figure 1c depicts how a prior art decoder (10) uses the buffers M1,
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`M2, and M3 of its dedicated memory (22) during the decoding process. [`753 Pat.,
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`3:20-22; 3:31-50]. Accordingly, in prior art systems, although the system included
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`a main memory (168) which the decoder (10) could access via the peripheral bus
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`(170), the decoder (10) utilized its local dedicated memory (22) not the main
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`memory (168) when decoding an image. Specifically, an image to be decoded was
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`stored in the CDB of the dedicated memory (22). The decoder (10) then received
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`the image to be decoded from the CDB in its dedicated memory (22). The decoder
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`(10) also received a previously decoded image (i.e., an “I” image frame or a “P”
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`image frame) from the buffers (M1, M2, M3) in its dedicated memory (22). The
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`decoder (10) then used the previously decoded image (i.e., the “I” or “P” image
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`frame) to decode the image to be decoded using, for example, the MPEG decoding
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`standard. The use of this dedicated memory (22) allowed the decoder (10) to
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`decode a compressed image without having to access the main memory and
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`avoided dropping image frames while preserving the available bandwidth on the
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`peripheral bus (170). [`753 Pat., 3:60-4:48].
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`40. The `753 Patent discloses an improved system which allows the
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`decoder and a first device (e.g., a CPU) to share the main system memory when
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`decoding an image and eliminates the need for a dedicated memory for the
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`decoder.
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`41.
`
` Figure 4 of the `753 Patent depicts an embodiment of the claimed
`
`invention where the decoder/encoder (80) shares the main memory (168) with
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`other peripheral devices (e.g., the CPU (152)). [`753 Pat., 10:14-17]. As shown in
`
`Figure 4, the decoder/encoder (80) does not have a dedicated memory and instead
`
`uses a region (22’) of the main memory (168) of the system for the decoding
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`process. [`753 Pat., 10:24-26]. The region (22’) of the main memory (168) includes
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`a Compressed Data Buffer (CDB) into which the image source (122) writes a
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`compressed image (i.e., an image to be decoded) and two image buffers M1, and
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`M2 associated with “I” and “P” image frames (i.e., previously decoded images).
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`[`753 Pat., 10:27-30]. The third buffer (M3) used in dedicated memory of prior art
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`decoders has been eliminated and the “B” frames which are not used to decode
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`other images are directly supplied to the display adapter (120) as they are being
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`decoded. [`753 Pat., 10:30-33].
`
`
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`42. Accordingly, in the improved system of the `753 Patent an image to
`
`be decoded is directed from the source (122) to the CDB in the main memory
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`(168). [`753 Pat., 10:34-36]. This image to be decoded is transferred from the CDB
`
`in the main memory (168) to the decoder/encoder (80) over the peripheral bus
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`(170) and is decoded by the decoder. [`753 Pat., 10:36-37]. If the decoded image is
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`an “I” image frame or a “P” image frame, the decoder/encoder (80) retransmits the
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`decoded image to buffers M1 and M2 in the main memory (168). [`753 Pat., 10:37-
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`39]. These “I” and “P” image frames may then be transmitted from the buffers M1
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`and M2 in the main memory (168) back to the decoder and used in decoding of
`
`subsequent “P” or “B” image frames or may be transmitted to the display adapter
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`(120) for display. [`753 Pat., 10:44-47]. If an image to be decoded corresponds to a
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`Page 19 of 68
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`“B” image frame, the decoder/encoder (80) decodes the image and it may directly
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`supply it to the display adapter (120) without storing it in the main memory (168)
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`if it is ready for display in the display sequence time frame. [`753 Pat., 10:39-42].
`
`43. Accordingly, in the improved system disclosed in the `753 Patent, the
`
`decoder’s dedicated memory is eliminated and instead, the decoder receives an
`
`image to be decoded (i.e., compressed image stored in CDB) and a previously
`
`decoded image (i.e., “I” image frames or “P” image frames stored in M1 and M2)
`
`from a region 22’ in the main memory (168). These “I” and “P” image frames may
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`then be utilized in decoding of subsequent “P” or “B” image frames by the
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`decoder. [`753 Pat., 10:44-47].
`
`44. Consistent with this improvement, dependent claim 2 recites that “the
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`video circuit is further configured to receive data from the main memory
`
`corresponding to at least one previously decoded image.”
`
`45. The Petitioner relies on the combination of Bowes and the MPEG
`
`Standard for disclosing a decoder that receives a previously decoded video image
`
`from the main memory. First, as discussed below, a POSA would not have been
`
`motivated to combine Bowes and the MPEG Standard. Moreover, even if a POSA
`
`were to combine Bowes with the MPEG Standard, such a combination would not
`
`disclose a video circuit that receives a previously decoded video image from the
`
`main memory for at least three reasons: (1) Bowes’ DSP is not a video circuit; (2)
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`Page 20 of 68
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`if such a combination was made, a POSA would have stored a previously decoded
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`image in the dedicated memory of the Bowes’ DSP (as in the prior art disclosed in
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`the `753 Patent); and (3) Bowes does not disclose the DSP writing data into the
`
`main memory and then reading the same data from the main memory.
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`BOWES’ DSP IS NOT A “VIDEO CIRCUIT”
`
`46.
`
`I understand that the Petitioner has identified the DSP (20) of Bowes
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`as being analogous to the video circuit recited in the `753 Patent. [Petition at 40].
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`The word “video” is only mentioned four times in Bowes. [Bowes, 1:34; 1:37;
`
`1:41; 6:16]. The first three times the term “video” is used in conjunction with a
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`description of related art and the fourth time, the term “video” is used in reference
`
`to a NuBus peripheral bus video controller and not in reference to a processing
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`application. The words “decode” or “decoding” never appear in Bowes.
`
`47.
`
`Instead, Bowes specifically teaches that the DSP in the preferred
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`embodiment is suitable for audio processing, image signal processing, speech
`
`processing, and modem emulation. [Bowes Pat., 1:48-49; 6:32-37]. Bowes does
`
`not state that the DSP is suitable for video compression and decompression
`
`applications such as the implementations of the MPEG Standard. A POSA would
`
`recognize that audio processing, speech processing and modem emulation are
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`clearly distinct from video compression and decompression. The same is true with
`
`20
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`respect to “image processing.”
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`Page 21 of 68
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`48. Dr. Stone, Petitioner’s expert, defines “image processing” in his
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`textbook as “a computation performed on a digitized representation of an image
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`whose purpose is to enhance the image or to extract information about the image.”
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`[Ex. 2007 at 499]. This textbook was published in 1993 and accurately reflects
`
`how a person of skill in the art would have understood the term “image
`
`processing” as of the priority date of the `753 Patent. In contrast, the MPEG
`
`Standard is directed to compressing and decompressing video sequences. [Ex.
`
`1004, p. 4]. Such a compression and decompression of video sequences is wholly
`
`different from
`
`image processing. For example, video compression and
`
`decompression requires maintaining the temporal relationship between consecutive
`
`image frames, an important concept that is absent when processing a single image.
`
`[See Stone Deposition, 102:19-104:5].
`
`49. There are additional reasons why a POSA would recognize that a DSP
`
`used for
`
`image processing
`
`is not suitable for video compression and
`
`decompression. Specifically, image processing requires precision and involves a
`
`host of arithmetic operations. In contrast, the primary concern in video
`
`compression and decompression is speed to ensure that video is delivered to
`
`viewer in real time. Therefore, video compression and decompression processes
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`typically do not require the same level of precision and arithmetic operations as
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`image processing. As a result, a POSA would typically use a different type of DSP
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`21
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`Page 22 of 68
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`for image processing as compared to video compression and decompression.
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`Specifically, the internal architecture of a DSP may be categorized according to the
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`type of numerical format it utilizes. A “floating point” DSP utilizes a format
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`wherein a single value is specified with three fields, a sign field indicating whether
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`the value is positive or negative; a mantissa or significand field indicating the
`
`precision of the value; and a signed exponent field indicating the magnitude. In
`
`contrast, a “fixed point” DSP utilizes a format wherein a single value represents
`
`the signed value using an appropriate signed value encoding such as 2’s
`
`complement and where the binary- or radix point is in a “fixed” position.
`
`50. That the DSP (20) of Bowes is not suitable for video compression and
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`decompression is further evident from the fact that Bowes states that in a preferred
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`embodiment, the DSP (20) of Bowes is the AT&T DSP3210. [Bowes, 6:28-30].
`
`Such a DSP is not suitable for MPEG video decoding because it is a floating point
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`DSP. [Ex. 2003, at 1]. Specifically, the AT&T DSP3210 utilizes a floating-point
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`Data Arithmetic Unit (DAU) that “is the primary execution unit for signal
`
`processing algorithms.” [Ex. 2003, at 5].
`
`51. Due to its use of a more complex format, a floating point DSP
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`generally incurs increased latency but provides increased accuracy and dynamic
`
`range (i.e., it can represent a wider range of numerical values). In contrast, a fixed
`
`point DSP allows higher performance but at the expense of decreased accuracy and
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`22
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`Page 23 of 68
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`dynamic range. Therefore, a POSA would appreciate that a floating point DSP is
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`not well-suited for video compression and decompression. [See, also, Stone Depo.,
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`Ex. 2006, 201:20-202:7].
`
`52. A POSA would appreciate that MPEG decoding is a high throughput
`
`operation consisting in part, of repeated inverse discrete cosine transforms (IDCT),
`
`VLD, de-quantization, and other processes. Floating-point DSPs (such as the
`
`DSP3210) provide for higher dynamic range and more accuracy in their
`
`computations, but at the expense of increased latency whereas a fixed point DSP
`
`requires shorter internal data paths providing for performance advantages. While it
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`may appear that the increased accuracy provided by floating-point DSPs would be
`
`advantageous in IDCT operations, for video and specifically MPEG video
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`decompression, the IDCT operations are performed over relatively short bit-exact
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`data that ultimately represents a pixel value, thus increased precision as provided
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`by a more costly floating-point DSP would offer no advantage when used as an
`
`MPEG video decoder. Further, the other intensive processes require a considerable
`
`amount of control instructions to be executed rather than arithmetic instructions
`
`(
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