Data Sheet
`March 1993
`
`gar—“rs: AT&T
`
`MM Microelectronics
`ll
`
`AT&T DSP3210 Digital Signal Processor
`The Multimedia Solution
`
`
`
`Features and Benefits
`
`amen:
`
`
`
`
`
`
`
`Microprocessor bus compatibility:
`
`-
`32bit, byte-addressable address space
`
`- Retry, relinquish/retry, and bus error support
`
`I Page mode DRAM support
`I Direct support for both 680x0 and 80x86 signaling
`
`
`
`Designed for efficient bus master designs allowing
`the DSP3210 to easily be incorporated into pP-
`based systems The 32~bit, byte~addressable
`space enables the DSP3210 and a uP to share
`common address space and pointer values as wel
`' Open development environment:
` AT&T VCOSTM operating system:
`- Dramatically lower system costs
`- Real-time, multitasking operating system
`
`
`I Uses host rather than local memory
`Full utilization of both pP and DSP3210
`Simplifies both algorithm and application
`a True parallel processing
`
`development
`a Complete task management
`
`Ease of programming/higher performance.
`
`Full 32bit floating~point arithmetic
`
`C—like assembly language
`
`Single-cycle PC relative addressing
`All instructions are single~cycle
`(four memory accesses per instruction cycle)
`Access to DSP32C programs
`
`Logic Automation” model
`
`Higher pertormcean"
`
`Access to the largest existing 32-bit DSP SW base.
`Faster, more efficient system development.
`
`introduction
`
`The DSP321 0 brings the power of floating-point
`signal processing to personal computers and
`workstations, opening a wide range of multimedia
`applications. The DSPSQiU has been engineered
`with a single focus: to enable advanced multimedia
`applications in personal computers and
`workstations. Based on AT&T‘s DSP320
`
`architecture, the DSP32t 0 has the unique ability to
`be integrated into personal computer and
`workstation system designs. Particular attention is
`paid to primary bus interfacing; the DSP3210 is
`compatible with both 80x86 and 680x0
`microprocessor signaling This allows designers to
`easily create low-cost systems by using the
`DSP32iO as a busomaster device. A full, bus-level
`SmartModel‘ of the DSP3210 is offered by Logic
`Automation, inc. for system simulation of designs
`incorporating the DSPBZiO.
`
`Along with its optimizing Ccompiler and assembly
`language software tools, the DSP3210 is further
`supported with ATaT's VCOS operating system.
`
`The VCOS operating system provides a powerful real-
`time, multitasking and multiprocessing environment
`which effectively manages multimedia applications
`across various computer platforms. By employing
`innovative task- and code-management techniques,
`VCOS operating system allows the DSP3210 to use
`existing system memory in PCs and workstations
`rather than expensive dedicated SRAM for DSP
`program and data storage.
`
`Complete real-time debugging tools are included to
`speed both application and algorithm development.
`By separating the application and algorithm
`development phases of multimedia software creation,
`the V008 operating system greatly simplifies and
`shortens development schedules.
`
`' Logic Automao'on and Smardidode/ are registered trademarks of
`Logic Automation, Inc.
`
`3 3058025 353181018 "3'35 -
`Page 1 of 39
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`(
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`PUMA EXHIBIT 2003
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`Page 1 of 39
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`

`

`AT&T DSP3210 Digital Signal Processor
`
`Table of Contents
`
`Contents
`
`Page
`
`Features and Benefits .............................................................................................................................................. 1
`Introduction .............................................................................................................................................................. 1
`
`Applications ............................................................................................................................................................ 4
`PC/Workstation Multimedia Applications ............................................................................................................... 4
`DSP3210 Motherboard Implementations ........................................................................................................... 4
`DSP3210 Addsln Cards ...................................................................................................................................... 4
`
`System Integration Under the V008 Operating System ................................................................................... 5
`Functional Description .............................................................................................................................................. 5
`Functional Units .................................................................................................................................................... 5
`Control Arithmetic Unit (CALI) ............................................................................................................................ 5
`Data Arithmetic (DAU) ....................................................................................................................................... 5
`On—Chip Memory ................................................................................................................................................ 6
`Bus Interface ...................................................................................................................................................... 6
`
`Serial l/O (SIO) ................................................................................................................................................... 6
`DMA Controller (DMAC) ..................................................................................................................................... 7
`Timer/Bit I/O ....................................................................................................................................................... 7
`DSP3210 Instruction Set ....................................................................................................................................... 7
`Processor Control Features .................................................................................................................................. 7
`Serial l/O DMA ................................................................................................................................................... 7
`
`Exception Processing ......................................................................................................................................... 8
`Low-Power, Powerdown Mode .......................................................................................................................... 8
`Boot ROM Code .................................................................................................................................................... 8
`F12 Silicon Revision .......................................................................................................................................... 8
`Start-Up Options ................................................................................................................................................ 8
`Operation of Boot ROM Routines ...................................................................................................................... 9
`Detailed Description of Boot Routines .............................................................................................................. 10
`Processor Mode Boot ........................................................................................................................................ to
`
`Starting Address Redirection (SAR) Boot ......................................................................................................... iO
`EPROM Boot .................................................................................................................................................... to
`
`
`
`Special Note for Intel—Style Signaling implementations (Alternate Loader Routines) ....................................... 12
`Detailed Description of Self-Test Routine ......................................................................................................... 12
`Listing 1, Boot ROM Code ................................................................................................................................ 13
`Pin Information ........................................................................................................................................................ 16
`Pin Descriptions ................................................................................................................................................ 17
`Absolute Maximum Ratings ..................................................................................................................................... 20
`~Iand ing Precautions .............................................................................................................................................. 20
`
`Electrical Specifications ........................................................................................................................................... 2i
`Timing Specifications ............................................................................................................................................... 22
`T‘ming Requirements for CKl ............................................................................................................................ 23
`T'ming Requirements for Synchronous Bus Interface Inputs ............................................................................ 23
`T'ming Characteristics for Synchronous Bus Interface Outputs ....................................................................... 24
`T'ming Characteristics for Synchronous Delay/Hold Times .............................................................................. 24
`T‘ming Relationships for Synchronous Bus lnterace Operation (55 MHz) ........................................................ 25
`T‘ming Relationships for Synchronous Bus lnterace Operation (86 MHz) ........................................................ 26
`T'ming Relationships for Asynchronous Bus Interace Operation ...................................................................... 28
`Timing Characteristics for Bus Arbitration ......................................................................................................... 29
`Timing Requirements for Serial Inputs .............................................................................................................. Bi
`T‘ming Requirements for Serial Outputs ........................................................................................................... 32
`Timing Characteristics for Serial Outputs .......................................................................................................... 32
`Timing Requirements for Serial Clock Generation ............................................................................................ 34
`Timing Characteristics for Serial Clock Generation .......................................................................................... 34
`Timing Requirements for Bit l/O ........................................................................................................................ 35
`Timing Characteristics for Bit I/O ...................................................................................................................... 35
`Timing Requirements for Interrupts ................................................................................................................... 36
`Timing Characteristics for Interrupts ................................................................................................................. 36
`Timing Requirements tor Reset ........................................................................................................................ 37
`Timing Characteristics for Reset and ZN .......................................................................................................... 37
`Outline Diagram ....................................................................................................................................................... 39
`
`2
`
`l uosuuaa Domain set, I
`
`Page20f39
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`Page 2 of 39
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`

`

`AT&T DSP3210 Digital Signal Processor
`
`introduction (continued)
`
`
`
`
`U
`
`RAMt
`
`DAU‘:32m FPU CAU: 32-bitINT
`
`
`- ADDRESS
`
`BOOT
`ROM
`
`t
`DATABUS 32
`
`RAMO
`
`t
`
`8E
`
`E
`t.
`
`3m
`
`a
`
`. FP MULTIPLY
`
`G ENERATION
`' FP ADD
`- ARITHMETIC
`
`
`
`' FORMAT CONVERT ' BIT
`
`
`MANlPULATlON
`TIM ER/
`
`. HW CONTEXT SAV-
`
`
`BIO
`
`
`
`
`Figure 1. DSP3216 Biock Diagram
`
`The VCOS operating system includes its own
`multimedia library, complete with speech processing,
`speech recognition, graphics, music processing, and
`modem modules. The VCOS system is an open
`environment, so application developers may access
`third—pasty moduies as well as AT&T's library.
`,
`.
`Flgllie 1 shows the DSszTO biock diagram. .5”
`addition to a hm” description Of the DSP3210 5
`application in muitimedia environments, each
`functionai unit, the instruction set, and the processor
`control features are described.
`
`This data sheet is designed to be a companion
`document to the AT&T DSP3210 Information Manuaf
`(MN91~0060MOS). The brief descriptions of the
`DSP3210‘5 architecture and instruction set are greatly
`expanded in the information manual. The data sheet
`is intended to give the iatgst, up-too’ate, timing
`specifications and boot R M firmware descriptions,
`white the information manual contains the detailed
`information needed to understand the DSPSZiO‘s
`operation.
`
`I Balances {tomcat} 343 -
`
`Page30f39
`
`Page 3 of 39
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`

`

`AT&T DSP3210 Digital Signal Processor
`
`Applications
`
`ospazio Add-in Cards
`
`The DSP3210 may be used in a variety of applications
`due to its raw floating-point power, low cost, low power
`dissipation, and interfacing flexibility However,
`multimedia was the primary application considered
`when designing the DSP3210.
`
`PClWorkstation Multimedia Applications
`
`DSP321O Motherboard implementations
`
`The DSP3210 is intended to be used in PC and
`
`workstation system architectures in which the
`DST-33210 is a parallel processor to a host processor.
`The DSPBZtO maintains a 32—bit bus—master interface
`to system memory (see Figure 2).
`
`The primary benefit of this system architecture is the
`DSP‘s ability to access program and data from system
`memory without host intervention. Furthermore,
`expensive local SRAM is replaced by the computer's
`existing system memory.
`
`Existing computers with BSA, lSA, MCA, NuBus‘,
`SBus, and proprietary bus or CPU direct~siot
`capabilities can be easily retrofitted with low-cost
`DSP3210 boards to perform identical applications to
`motherboard-equipped PCs.
`In systems with direct
`CPU slots or 32bit buses capable of bus mastering,
`these DSPBZtO-based cards require no DSP memory
`(memory is accessed via the bus or CPU direct slot).
`
`Using the visible caching technique native to the
`V008 operating system. boards installed in lower—
`bandwidth buses use inexpensive local 32—bit DRAM
`on the DSPBZiO add-in card in these environments,
`the DSP3210 uses the bus primarily to transfer tasks
`and WC to and from the DSPBQiO card.
`
`‘ NuBusis a registered trademark of Massachusetts institute of
`Technology.
`
`ON-CHIP RAM USED FOR KERNEL
`STORAGE AND PROGRAM/DATA
`CACHE
`
`HOST
`MICROPROCESSOH
`
`
`
`[3352:3210
`
`DAU
`A ,
`“Ad
`
`h
`I O
`i
`O
`
`TER
`BUS MAS
`INTERFA
`CE
`
`LOWCOST SINGLE-CHIP
`ND AND D/A CONVERTER
`TELEPHONE
`
`T7525
`CODEC
`
`l
`
`l
`
`LSPEAKER/
`MICROPHONE
`
`4—» DiGlTAL AUDO DATA
`
`SYSTEM BUS L.
`
`DIRECT lNTERFACE TO SYSTEM BUS
`
`D‘SK
`
`Egg/VégES: HiGH BANDWlDTH AND
`SYSTEM
`MEMORY \ SYSTEM MEMORY PROVIDES LOW~COST
`
`STORAGE or FUNCTEONS AND DATA
`
`Figure 2. Typical DSP321O PC/Workstation Motherboard Configuration
`
`4
`
`I ousooes DULBUEL EST I
`
`Page4of39
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`Page 4 of 39
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`

`

`
`
`AT&T DSP3210 Digital Signal Processor
`
`Applications (continued)
`
`System integration Under the V008 Operating
`System
`
`Since the DSP3210 supports both big— and little—endian
`byte ordering, sharing both data and pointer values
`with any host microprocessor is easily accomplished
`This is especially useful in multimedia applications
`where intimate communications between the host
`
`microprocessor and DSP are necessary. For real-time
`signal processing under the V008 operating system,
`on-chip SRAM is loaded with code and data from
`system memory before executing. Applications are
`broken into functions that are executed successively in
`this fashion. Nonreal-time background jobs may be
`either executed from system memory or cached into
`the D8P3210‘s internal memory.
`
`Functional Description
`
`Functional Units
`
`The DSP3210 consists of seven functional units:
`control arithmetic unit (CAU), data arithmetic unit
`(DAU), on-chip memory (RAMO, RAMl, boot ROM),
`bus interface, serial l/O (SlO), DMA controller (DMAC),
`and timer/bit l/O (BlO) unit.
`
`Control Arithmetic Unit {CAU}
`
`The CAU is responsible for performing address
`calculations, branching control, and to. or 32—bit
`integer arithmetic and logic operations.
`it is a RlSC
`core consisting of a 32—bit arithmetic logic unit (ALU)
`that performs integer arithmetic and logical operations
`a full 32—bit barrel shifter for efficient bit manipulation
`operations, a 32-bit program counter (PC), and twenty
`two 32-bit general—purpose registers.
`
`ADDRESS Bus
`DATA eus
`(32)
`
`(32)
`
`
`CAU
`
`
`
`BARREL SHlFTER 16/32
`
`(32
`3
`
`
`
`
`
`pc/pcsh (32)
`
`rO-A r14 32)(
`risu—rQO (32)
`sp(32)
`evtp (32)
`
`
`
`
`
`
`
`STACK ADDR (32)
`
`ps (16)
`
`
`Figure 3. Control Arithmetic Unit (CAU)
`
`II ousnuas [tumor-32 tits I
`
`Page5of39
`
`The CAU performs two types of tasks: executing
`integer, data move, and control instructions (CA
`instructions), or generating addresses for the operands
`of floating-point instructions (DA instructions). CA
`instructions perform load/store, branching control, and
`16- and 32—bit integer arithmetic and logical
`operations. DA instructions can have up to four
`memory accesses per instruction, and the CAU is
`responsible for generating these addresses using the
`postmodified, register-indirect addressing mode (one
`address is generated in each of the four states of an
`instruction cycle).
`
`Data Arithmetic Unit (DAU)
`
`The DAU is the primary execution unit for signal
`processing algorithms. This unit contains a 32—bit
`floating-point multiplier, a 40~bit floating—point adder,
`four 40bit accumulators, and a control register (dauc).
`The multiplier and adder work in parallel to perform
`16.7 million computations per second, yielding 33
`MFLOP performance. The multiplier and adder each
`produce one floating-point result per instruction cycle.
`The DAU contains a four~stage pipeline (fetch,
`multiply, accumulate, write). Thus, in any instruction
`cycle, the DAU may be processing four different
`instructions, each in a different stage of execution.
`
`DATA BUS
`
`(82)
`
`
`
`
`DAU
`(32)
`
`FLOATiNG—
`
`POlNT
`
`MULTIPLIER
`
`
`
`
`a0-a3 (40)
`
`
`{40)
`
`HARDWARE
`CONVERSEONS
`FLOATING~
`POINT
`ADDER
`
`Figure 4. Data Arithmetic Unit (DAU)
`
`The DAU supports two floatingrpoint formats: single
`precision (32-bit) and extended single precision
`(40—bit). Extended single precision provides eight
`additional mantissa guard bits. Postnormalization logic
`transparently shifts binary points and adjusts
`exponents to prevent inaccurate rounding of bits when
`the floating—point numbers are added or multiplied.
`This eliminates concerns such as scaling and
`quantization error.
`
`Page 5 of 39
`
`

`

`AT&T DSP3210 Digital Signal Processor
`
`Functional Description (continued)
`
`All normalization is done automatically, so the result in
`the accumulator is always fully normalized.
`
`Single-instruction, data—type conversions are done in
`hardware in the DAU, thus reducing overhead required
`to do these conversions. The DAU performs data-type
`conversions between the DSP32 32-bit floating—point
`format and lEEE P754 standard 32-bit floating-point.
`16- and 32-bit integer, 8—bit unsigned, Maw, and A-iaw
`formats. The DAU also provides an instruction to
`convert a 32bit floating—point operand to a 3-bit seed
`value used for reciprocal approximation in division
`operations.
`
`On—Chip Memory
`
`The DSP3210 provides on—chip memory for instruc-
`tions and data.
`instructions and data can arbitrarily
`reside in any location in both on- and off—chip memory.
`The DSP3210 provides two 1K x 32 RAMs and a 256 x
`32 boot ROM. The boot ROM is preprogrammed to
`enable the DSP3210 to boot directly from external
`memory. such as slow, inexpensive ROM or EPROM.
`
`Bus lnterface
`
`The external address bus of the DSP3210 is 32-bits
`
`wide and fully byte—addressable, allowing the
`DSP3210 to directly address 4 Gbytes of memory or
`memory—mapped hardware. External memory is
`partitioned into two logical address spaces, A and B.
`Each partition contains 2 Gbytes of address space.
`
`The number of wait—states for external memory
`partitions A and B are independently configurable via
`the pcw register. Configured waits of O, t, 2, or 3 or
`more wait—states are programmable; this simplifies the
`interface to fast external memory. Unlike most digital
`signal processors (which employ full-cycle wait-states}.
`the DSP321O offers much greater flexibility. This
`flexibility is achieved by offering 1/4 cycle wait—states.
`Each waitvstate is 1/4 of an instruction cycle, allowing
`greater granularity in determining optimal speed/cost
`memory trade-offs. When waits are externally con-
`trolled the DSP adds wait—states until the memory
`acknowledges the transaction via the SRDYN pin.
`
`The bus interface supports retry, relinquish/retry, and
`bus error exception handling, All signaling provided to
`the external system is configurable on reset to simplify
`the interface to a variety of microprocessor system
`buses.
`
`Sharing of the external memory interface is performed
`via a complete request/acknowledge protocol. System
`throughput is greatly enhanced by the DSPBEiO’s
`ability to execute from internal memory while the
`DSP3210 does not have ownership of the bus.
`
`8
`
`- ousuuas 801.3023 use I
`
`Page6of39
`
`The DSP3210 will continue to execute from internal
`
`memory until accesses to the external memory are
`needed. At that point, the DSP asserts the BRN signal
`and waits for BGN. The bus arbiter acknowledges the
`bus request by asserting the DSP3210‘s bus grant pin
`(BGN). The DSP3210, in turn, acknowledges the
`grant by asserting the bus grant acknowledge
`(BGACKN) and driving the external memory interface
`pins. When the BGN is negated, any ongoing external
`memory transaction is completed before the DSP
`relinquishes the bus by placing the external memory
`interface bus in the high-impedance state and negating
`BGACKN.
`
`Serial l/O (SIO)
`
`The SlO unit provides serial communications and
`synchronization with external devices. The SlO
`signals support a direct interface to a time-division
`multiplexed (TDM) line, a zero-chip interface to
`codecs, and direct DSP—thSP transfers for
`multiprocessor applications. The SlO performs serial-
`to-parallel conversion of input data, and parallel~to~
`serial conversion of output data at a maximum rate of
`25 Mbits/s.
`it is composed of a serial input port, a
`serial output port, and on-chip clock generators. Both
`ports are double buffered so that backvto-back
`transfers are possible. The SlO is configurable via the
`loo register. The input buffer (IBUF), the output buffer
`(OBUF), and the loo register are accessible as
`memory-mapped input/output (MMlQ) registers in the
`instruction set. The ibui and obuf are also accessible
`
`as l/O registers in the instruction set.
`
`The data sizes of the serial input and output can be
`configured independently.
`input data lengths of 8—, 16,
`and 32—bits and output data lengths of 8', i8-, 24», and
`32-bits can be selected. The input and output data
`can be independently selected to be most significant
`bit first or least significant bit first.
`
`SlO transfers can be made under program, interrupt,
`or DMA control. A program can test the input or output
`buffer status flags using conditional branch
`instructions. By configuring the exception mask
`register (emr), interrupt requests may be generated by
`the input and output buffer status flags.
`in DMA mode.
`transfers occur between lBUF, OBUF, and memory
`without program intervention.
`
`Di—‘r
`
`DO
`
`DATA Bus
`
`lCK, iLD, cox,“
`OLD, SY
`
`
`
`(32)
`
`Figure 5. Serial IO (SlO)
`
`Page 6 of 39
`
`

`

`AT&T DSP3210 Digital Signal Processor
`
`The BlO is a general-purpose 8‘bit input/output port.
`includes features that make it suitable for board—level
`
`it
`
`status signal generation and control signal testing by
`the DSP3210. The BIO interface consists of eight l/O
`lines, any of which can be independently configured as
`an input or an output. Outputs can be written with
`either 1 or 0, toggied, or left unchanged.
`inputs can be
`directly read and loaded into a CAU register and then
`tested, or the inputs can be read and directly written to
`memory. The registers associated with the BIO are
`accessible as registers in the DSP3210 instruction set.
`
`DSP3210 instruction Set
`
`The assembly language of the DSP3210 frees
`programmers from tedious memorization of assembly
`language mnemonics. DSPSZiO instructions are
`patterned after the C programming language and are
`entered in a natural equation syntax.
`in addition to
`being easier to learn, the resulting code is far more
`readable than mnemonic—based assembly languages,
`making code maintenance much easier.
`
`C-like assembly language —> Easy to learn/excellent
`readability
`
`Below is an example assembly language instruction:
`
`*rl++ : a0 : a1 + *r2++ * *r3++
`
`The execution of this instruction simply follows the
`conventions of the highvlevel C programming
`language:
`
`"Multiply the two floating-point values stored in the
`memory locations pointed to by registers r2 and r3.
`Add the result to the contents of accumulator at, store
`the result in accumulator a0, and write the result to the
`32-bit memory location pointed to by register rt.
`Postincrement pointer registers rt, r2, and r3,"
`
`Processor Control Features
`
`The DSPBZtO supports advanced control features that
`simplify system design and improve software
`performance. This section describes serial l/O direct-
`memory access (DMA), error and interrupt exceptions,
`and the powerdown mode.
`
`Serial l/O DMA
`
`External devices can access the onvchip RAM in the
`DSP3210, as well as external memory, using direct-
`memory access (DMA). DMA transfers occur between
`either internal or external memory and the serial l/O
`ports without processor intervention.
`
`Functional Description (continued)
`
`DMA Controller (DMAC)
`
`The DMA controller contains two DMA channels that
`are used in conjunction with the serial l/O: one for
`input DMA and one for output DMA. By configuring
`the input DMA channel, data being shifted into the
`serial input port can be buffered in memory without
`processor intervention. By configuring the output DMA
`channel, a butter of data in memory can be supplied to
`the serial output, as necessary, without processor
`intervention,
`
`The registers used to configure the DMA controller are
`directly accessible in the DSP3210‘s instruction set.
`By configuring the exception mask register (emr),
`interrupt requests can be generated when the memory
`buffer has been filled or emptied based on the size of
`the buffer requested.
`
`
`
`ADDRESS BUS
`
`(32)
`
`
`
`
`DATA Bus
`
`(32)
`
`Figure 6. DMA Controller (DMAC)
`
`Timer/Bit [/0
`
`The timer is a programmable 32-bit interval
`timer/counter used for interval timing, rate generation,
`event counting, or waveform generation. The input to
`the timer can be derived from the DSP3210 clock, or it
`may come from an external source. The output of the
`timer can generate a maskable interrupt, or it may be
`selected as an output of the chip to drive external
`hardware.
`it can be configured to count down to zero
`once or to count continuously by automatically
`reloading the counter with its initial value when it
`reaches zero. The count value may be read or
`changed at any time during operation. The registers
`associated with the timer are accessible as MMIO
`
`registers in the instruction set. By configuring emr,
`interrupt requests may be generated when the count
`reaches zero.
`
`
`DATA BUS
`
` bio (16)
`
`BlOO—«BlO?
`(32>
`b or: (8)
`
`timer (32)
`
`teen (8)
`
`arm (t 6}
`
`
`Figure 7. Timer/Bit i/O (BIO)
`
`
`E DUSBDEE DULBUEH Tact I
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`Page 7 of 39
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`Page 7 of 39
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`

`

`AT&T DSP3210 Digital Signal Processor
`
`Functional Description (continued)
`
`mode when either an unmasked interrupt is requested
`or an error exception occurs.
`
`Exception Processing
`
`Normal instruction processing can be altered by the
`introduction of interrupt routines or error handling
`routines. Exception processing is the set of activities
`performed by the processor in preparing to execute a
`handler routine or in returning to the program that took
`the exception. Error exception and interrupt excep-
`tions cause different activities to be performed.
`in
`particular, error exceptions abort the current instruction
`and cannot resume processing.
`interrupt exceptions
`shadow the current state of the processor before
`taking the interrupt exception; therefore, when the
`interrupt routine is complete, the program can be
`reinstated and continued.
`
`The error and interrupt exceptions are prioritized, and
`some error sources, in addition to all interrupt sources,
`are individually maskable via the emr. A relocatable
`vector table controls program flow based on the source
`of the interrupt exception.
`in response to a given
`exception, the DSP branches to the corresponding
`address in the exception vector table which contains
`pairs of 32-bit words.
`
`The DSP321 0 provides a zero~overhead context save
`of the entire DAU (floating—point unit) for interrupt
`processing.
`Interrupt latency is only three instruction
`cycles for interrupt entry and one instruction for
`interrupt exit. Before servicing the interrupt, the
`DSP3210 automatically saves the state of the machine
`that is invisible to the programmer, as well as the DAU
`accumulators a0-a3 (including guard bits), all DAU
`flag status information, and the dauc register.
`internal
`states that are visible to the programmer are saved
`and restored by the interrupt service routine. To return
`to the interrupted program, the interrupt service routine
`restores the user-visible state of the 08193210 (that
`was saved) and then executes the ireturn instruction.
`This single-cycle interrupt return automatically restores
`the entire DAU state saved during interrupt entry.
`Quick interrupt entry/exit/context save is critical to real—
`time multimedia tasks.
`
`Low-Power, Powerdown Mode
`
`To address the needs of portable computer platforms,
`the DSP3210 is equipped with a powerdown mode that
`lowers power consumption to below 300 mW (from the
`typical power dissipation of 750 mW). This mode is
`implemented with a wait-for-interrupt instruction that
`stops internal execution in the DAU and CAD sections
`of the DSP8210. External memory and internal
`memory operations execute to completion and then
`wait. To ensure maximum system functionality, the
`D8P3210 bus arbitration logic remains active in this
`mode, and all peripheral units (serial l/O, DMA
`controller, timer, and BIO) remain active to perform l/O
`events. The interrupt handler is also active to sense
`interrupt requests. The DSP3210 exits the powerdown
`
`Boot ROM Code
`
`F12 Silicon Revision
`
`The boot ROM code in F12 silicon revision DSPSZIO
`
`devices otters the user three different processor start-
`up options plus a self-test routine. The processor self-
`test routine performs a limited functional test of both
`on-chip arithmetic execution units (DAU and CAU).
`This routine is user—callable as described in the
`Detailed Description of Self~tesi Routine section.
`
`Additionally, the 2048-word count limitation in the Fit
`EPROM boot routine has been removed. See the
`EPROM boot section . The F12 boot ROM code is
`upward compatible with F11 boot ROM code;
`subsequently, changes in design software or hardware
`are not needed when migrating to the F12 silicon
`revision.
`
`Start—Up Options
`
`Since the DSP3210 is intended (or a variety of
`environments, three ditierent start~up options are
`provided for maximum flexibility. Although the
`DSP3210 contains an on—chip boot ROM, the first and
`simplest start-up option doesn‘t use this ROM. This
`start—up option works as follows:
`
`I The DSPSZiO begins execution at external
`memory location 0 immediately following reset.
`
`The other two boot options are controlled by the on-
`chip boot ROM of the DSPSZTO. These two routines
`work as follows:
`
`I The DSPBZiO loads a 32-bit address from external
`location 0 and begins executing code at the
`location indicated by the 32—bit address. This
`technique, useful in systems where the DSP3210
`shares me