Trials@uspto.gov
`Tel: 571-272-7822
`
`
`
`
`
`Paper 53
`Entered: January 4, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`HTC CORPORATION and HTC AMERICA, INC.,1
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`
`____________
`
`Case IPR2015-01501
`Patent 7,777,753 B2
`____________
`
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`1 Samsung Electronics Co., Ltd.; Samsung Electronics America, Inc.; and
`LG Electronics, Inc. were terminated from this proceeding. See Papers 28
`and 42.
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`I. INTRODUCTION
`In its Petition requesting inter partes review, HTC Corporation and
`HTC America, Inc. (collectively, “Petitioner”) asserted the unpatentability of
`claims 1–4, 7–10, and 12 of U.S. Patent No. 7,777,753 B2 (Ex. 1001,
`“the ’753 patent”), owned by Parthenon Unified Memory Architecture LLC
`(“Patent Owner”). Paper 1 (“Pet.”), 1. The Petition identifies HTC
`Corporation; HTC America, Inc.; LG Electronics, Inc.; LG Electronics
`U.S.A., Inc.; LG Electronics MobileComm U.S.A., Inc.; Samsung
`Electronics Co., Ltd.; and Samsung Electronics America, Inc. as real parties-
`in-interest. Id. at 2. We have jurisdiction under 35 U.S.C. § 6, and this Final
`Written Decision, issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R.
`§ 42.73, addresses issues and arguments raised during the review. For the
`reasons discussed below, we determine that Petitioner has met its burden to
`prove, by a preponderance of the evidence, that claims 1–4 (“the challenged
`claims”) of the ’753 patent are unpatentable on the grounds upon which we
`instituted inter partes review.
`
`A.
`
`Procedural History
`On June 24, 2015, Petitioner filed a Petition to institute an inter partes
`review of claims 1–4, 7–10, and 12 of the ’753 patent. Pet. 1. Petitioner
`asserted grounds for unpatentability based on the following references and
`declarations:
`
`Exhibit
`1002
`1003
`
`References and Declarations
`File History of Patent No. US 7,777,753 B2
`Patent No. US 5,546,547 (“Bowes”)
`
`2
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`Exhibit
`1004
`
`1007
`1008
`1019
`
`References and Declarations
`International Organization for Standardization, “ISO/IEC
`11172-2: Information technology—Coding of moving
`pictures and associated audio for digital storage media at up
`to about 1,5 Mbit/s—Part 2: Video,” (1st ed. Aug. 1, 1993)
`(“MPEG”)
`Patent No. US 5,774,676 (“Stearns”)
`Declaration of Santhana Chari, Ph.D.
`T. Shanley et al., “PCI System Architecture,” Addison-
`Wesley Publ’g Co. (3rd ed. Feb. 1995) (“Shanley”)
`H. Stone, “Microcomputer Interfacing,” Addison-Welsey
`Publishing Co. (1982)
`Declaration of Harold S. Stone, Ph.D. (the “Stone Decl.”)
`1030
`Pet. vi–vii. Patent Owner filed a Preliminary Response (Paper 7). On
`January 6, 2016, we issued an Institution Decision (Paper 12, “Inst. Dec.”),
`instituting inter partes review on the following grounds:
`References
`Basis
`Claim(s) challenged
`Bowes and MPEG
`35 U.S.C. § 103(a)
`1 and 2
`Bowes, MPEG, and Stearns 35 U.S.C. § 103(a)
`3
`Bowes, MPEG, and Shanley 35 U.S.C. § 103(a)
`4
`Inst. Dec. 8; see Pet. 5–6.
`After institution, Petitioner filed a Request for Rehearing (Paper 14),
`which we denied (Paper 17), seeking reconsideration of our denial of
`institution of review with respect to claims 7–10 and 12. Patent Owner then
`filed a Patent Owner Response to the Petition (Paper 21, “PO Resp.”), and
`Petitioner replied (Paper 32, “Reply”). A hearing for the instant proceeding
`and related Cases IPR2015-01500 and IPR2015-01502 was held on
`September 19, 2016. A transcript (Paper 52, “Tr.”) of that hearing is
`included in the record.
`
`1020
`
`3
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`B.
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`Related Proceedings
`The ’753 patent is involved in several cases pending in the U.S.
`District Court for the Eastern District of Texas. Pet. 2–3; Paper 5, 2–3.
`Petitioner also has filed other petitions seeking inter partes review of related
`patents in related Cases IPR2015-01500 and IPR2015-01502. Pet. 3.
`Further, an unrelated petitioner, Apple Inc., has filed a petition challenging
`claims of the ’753 patent. See IPR2016-01114, Paper 7, 2–3 & 42
`(instituting inter partes review of claims 1–4, 7–10, and 12).
`
`A.
`
`II. THE ’753 PATENT (EX. 1001)
`Subject Matter
`The ’753 patent relates generally “to the field of electronic systems
`having a video and/or audio decompression and/or compression device, and
`is more specifically directed to sharing a memory interface between a video
`and/or audio decompression and/or compression device and another device
`contained in the electronic system.” Ex. 1001, col. 1, ll. 36–41. As of the
`effective filing date of the ’753 patent,2 a typical decoder included a
`dedicated memory, which represented a significant percentage of the cost of
`the decoder and which went unused most of the time. Id. at col. 2, ll. 21–63,
`col. 4, ll. 43–60, Figs. 1a–1c.
`
`
`2 The ’753 patent claims the benefit of a string of earlier-filed U.S. patent
`applications, the earliest of which was filed on August 26, 1996. Ex. 1001 at
`[63]. Petitioner does not challenge the entitlement of the ’753 patent to this
`earliest filing date and argues that the ’753 patent expired in August of 2016,
`presumably based on this earliest filing date. Pet. 10–11. Patent Owner
`implicitly claims entitlement of the ’753 patent to the benefit of this earliest
`filing date and expressly states that the ’753 patent expired on August 26,
`2016. Paper 8, 1.
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`To address these and other concerns, the ’753 patent discloses an
`electronic system in which a first device and a video and/or audio
`decompression and/or compression device are coupled to a shared memory
`through a bus that may have bandwidth sufficient for the video and/or audio
`decompression and/or compression device to operate in real time. Id. at col.
`4, l. 64–col. 5, l. 7. Figure 2 of the ’753 patent is reproduced below.
`
`
`
`Figure 2 is a block diagram of an electronic system that contains a device
`with a memory interface and an encoder and decoder. Id. at col. 6, ll. 3–5.
`“First device 42 can be a processor, a core logic chipset, a graphics
`accelerator, or any other device that requires access to the memory 50 . . . .”
`Id. at col. 6, ll. 29–32. Both first device 42 and decoder/encoder 80 have
`access to memory 50 through memory interfaces 72 and 76, respectively,
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`coupled to fast bus 70. Id. at col. 6, ll. 27–29, col. 7, ll. 26–28, 48–51. Fast
`bus 70 may have at least the bandwidth required for decoder/encoder 80 to
`operate in real time and, preferably, has a bandwidth of at least
`approximately twice the bandwidth required for decoder/encoder 80 to
`operate in real time. Id. at col. 7, ll. 48–51, col. 8, ll. 28–33.
`During operation, decoder/encoder 80, first device 42, and refresh
`logic 58, if it is present, request access to memory 50 through arbiter 82. Id.
`at col. 12, ll. 53–56. Arbiter 82 determines which of the devices may access
`memory 50. Id. at col. 12, ll. 57–58. Decoder/encoder 80 may get access to
`memory 50 in the first time interval, and first device 42 may get access to
`memory 50 in the second time interval. Id. at col. 12, ll. 58–61. Direct
`Memory Access (DMA) engine 52 of decoder/encoder 80 determines the
`priority of decoder/encoder 80 for access to memory 50 and the burst length
`when decoder/encoder 80 has access to memory 50. Id. at col. 12, ll. 61–67.
`DMA engine 60 of first device 42 determines its priority for access to
`memory 50 and the burst length when first device 42 has access to memory
`50. Id. at col. 12, ll. 65–67.
`When decoder/encoder 80 or one of the other devices generates a
`request to access memory 50, the request is transferred to arbiter 82, and
`access to memory 50 is determined based on the state of arbiter 82 and on a
`priority scheme. Id. at col. 13, ll. 1–30. In particular,
`
`[t]he state of the arbiter 82 is determined. The arbiter typically
`has three states. The first state is idle when there is no device
`accessing the memory and there are no requests to access the
`memory. The second state is busy when there is a device
`accessing the memory and there is no other request to access the
`memory. The third state is queue when there is a device
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`accessing the memory and there is another request to access the
`memory.
`Id. at col. 13, ll. 3–10 (emphases added). The priority scheme can be any
`scheme that ensures decoder/encoder 80 gets access to memory 50 often
`enough to operate properly, but does not starve entirely other devices
`sharing memory 50. Id. at col. 13, ll. 31–37; see id. at col. 8, ll. 9–13
`(describing a “starvation period”).
`
`B.
`
`Illustrative Claim
`Of the challenged claims, claim 1 is independent. Ex. 1001, col. 15,
`ll. 32–59. Claims 2–4 depend directly from claim 1. Id. at col. 15, l. 60–col.
`16, l. 9. Claim 1 is illustrative and is reproduced below:
`1.
`An electronic system comprising:
`a bus;
`a main memory coupled to the bus having stored therein
`data corresponding to video images;
`a video circuit coupled to the bus, the video circuit
`configured to receive data from the main memory corresponding
`to a current video image to be decoded and to output decoded
`video data corresponding to the current video image to be
`displayed on a display device, the current video image to be
`displayed adapted to be stored in the main memory;
`a processor coupled to the main memory, the processor for
`storing non-image data in the main memory and retrieving non-
`image data from the main memory; and
`an arbiter circuit coupled to the processor and to the video
`circuit, the arbiter circuit configured to receive requests for access
`to the main memory from the video circuit and the processor and
`to control access to the main memory by:
`providing access to the main memory for a request for
`access to the main memory when the arbiter circuit is in an idle
`state;
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`queuing a request for access to the main memory when the
`arbiter circuit is in a busy state; and
`queuing a request for access to the main memory in an
`order based on a priority of the request and a priority of each of
`one or more other requests for access to the main memory that are
`currently queued when the arbiter circuit is in a queue state.
`Ex. 1001, col. 15, ll. 32–59.
`
`III. CLAIM CONSTRUCTION
`Petitioner argues that the ’753 patent expired in August of 2016. Pet.
`10–11. Patent Owner states that the ’753 patent expired on August 26, 2016.
`Paper 8, 1. Thus, the parties agree that the ’753 patent has expired.
`As a result, we construe the claims in accordance with the principles
`followed in district court. See Phillips v. AWH Corp., 415 F.3d 1303, 1314
`(Fed. Cir. 2005) (en banc). 37 C.F.R. § 42.100(b); see Toyota Motor Corp.
`v. Cellport Sys., Inc., Case IPR2015-00633, slip op. at 8–10 (PTAB Aug. 14,
`2015) (Paper 11); cf. In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012)
`(“While claims are generally given their broadest possible scope during
`prosecution, the Board’s review of the claims of an expired patent is similar
`to that of a district court’s review.”) (internal citation omitted). Although
`Petitioner proposed a construction of the term “decoder” under the broadest
`reasonable construction standard, Petitioner argues that its proposed
`construction will remain the same even if we apply the district court claim
`construction, consistent with the principles set forth in Phillips. Pet. 11
`(stating that “this change in standards would not affect any of the proposed
`grounds in this Petition, especially in view of Patent Owner’s interpretations
`of the claims under the Phillips standard.”).
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`In our Decision on Institution, we construed the term “decoder” to
`mean “hardware and/or software that translates data streams into video or
`audio information.” Inst. Dec. 9–10. Neither party disputes our
`determination. See Tr. 15:24–16:17, 51:19–52:20. Nevertheless, the term
`“decoder” is not recited in challenged claims 1–4.
`Neither Petitioner nor Patent Owner offers other constructions of any
`claim term in the challenged claims. See Pet. 8–11. Only terms which are
`in controversy in this proceeding need to be construed, and then only to the
`extent necessary to resolve the controversy. Wellman, Inc. v. Eastman
`Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011) (explaining that “claim
`terms need only be construed ‘to the extent necessary to resolve the
`controversy’” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d
`795, 803 (Fed. Cir. 1999))). For purposes of this Final Written Decision, no
`claim terms require express construction.
`
`IV. ANALYSIS
`Petitioner asserts that claims 1–4 of the ’753 patent are unpatentable
`under 35 U.S.C. § 103(a) as obvious over Bowes and MPEG, alone or in
`combination with Shanley or Stearns. See supra Section I.A. Petitioner also
`relies upon the declaration of its declarant, Dr. Stone. See Ex. 1030 ¶¶ 153–
`174 (claims 1 and 2), 175–179 (claim 3), 180–181 (claim 4).
`A. Obviousness Over Bowes and MPEG
`1. Overview
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are “such
`that the subject matter[,] as a whole[,] would have been obvious at the time
`the invention was made to a person having ordinary skill in the art to which
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`said subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
`406 (2007). The question of obviousness is resolved on the basis of
`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of skill in the art;3 and (4) objective evidence of
`nonobviousness, i.e., secondary considerations.4 Graham v. John Deere
`Co., 383 U.S. 1, 17–18 (1966).5 For the reasons set forth below, we
`determine that Petitioner has shown by a preponderance of the evidence that
`claims 1 and 2 of the ’753 patent are unpatentable under 35 U.S.C. § 103(a)
`as obvious over Bowes and MPEG.
`
`
`3 Petitioner proposes an assessment for a person of ordinary skill in the art.
`Pet. 11 (citing Ex. 1030 ¶¶ 78–81); see Ex. 2009 ¶ 24. Patent Owner’s
`declarant, Dr. Thornton, proposes an alternative assessment for a person of
`ordinary skill in the art. Ex. 2009 ¶ 25. Nevertheless, Dr. Thornton testifies
`that “my analysis and conclusions would remain unchanged” regardless of
`which assessment is applied. Id. ¶ 26; see Tr. 40:8–42:11, 76:20–77:9. To
`the extent necessary and for purposes of this Final Written Decision, we
`adopt Petitioner’s assessment, which each party’s declarant meets or
`exceeds. See Ex. 1030 ¶¶ 2–6; Ex. 2009 ¶¶ 5–11.
`4 Patent Owner does not contend in the Patent Owner Response that such
`secondary considerations are present. See Paper 13, 6 (“Patent Owner is
`cautioned that any arguments for patentability not raised in the response will
`be deemed waived.”).
`5 There is no requirement to enumerate each Graham factor and to include
`findings specifically in terms of the factors as long as “the required factual
`determinations were actually made and it is clear that they were considered
`while applying the proper legal standard of obviousness.” Specialty
`Composites v. Cabot Corp., 845 F.2d 981, 990 (Fed. Cir. 1988).
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`a. Bowes (Ex. 1003)
`Bowes describes a memory bus arbiter for a computer system having
`a DSP co-processor. Ex. 1003, Title. According to Bowes,
`[i]n prior art computer systems, because of the high bandwidth
`required for real-time processing by a DSP, it has not been
`possible for the DSP to run off of the computer system’s
`[dynamic random access memory (DRAM)] in the way the
`[central processor unit (CPU)] 10 utilizes it without adversely
`affecting the rest of the computer system. Thus, there has been
`provided a large block of [static random access memory
`(SRAM)] 24 for use by the DSP 20. . . .
`A significant disadvantage to the prior art computer architecture
`of FIG. 1 is the requirement of a substantial block of static
`random access memory 24. SRAMs are significantly more
`expensive than DRAM which greatly increases the cost of
`computer systems which incorporate SRAM.
`Id. at col. 2, ll. 36–48. Thus, it is an object of Bowes “to provide a
`mechanism and method for arbitrating the memory bus bandwidth to
`efficiently allow the use of a digital signal processor and a CPU over a
`common memory bus sharing the system’s dynamic random access
`memory subsystem without requiring an expensive block static
`random access memory.” Id. at col. 2, ll. 57–63 (emphasis added).
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`Figure 2 of Bowes is reproduced below.
`
`
`Figure 2 illustrates a block diagram of a computer architecture incorporating
`the arbitration scheme described in Bowes. Id. at col. 3, ll. 62–64. “The
`scheme is implemented such that the DSP is provided with sufficient
`bandwidth to perform real-time digital signal processing using the system’s
`[DRAM] and not requiring the incorporation of an expensive block of
`[SRAM].” Id. at col. 4, ll. 55–60. As shown in Figure 2, the system
`includes CPU 10, memory controller and arbiter (MCA) 200, main memory
`subsystem 14, and DSP 20. Id. at Fig. 2. “Unlike prior art computer
`systems, the [system of Bowes] provides for the DSP 20 to reside on the
`system’s memory bus and operate from the computer systems’ main
`memory subsystem 14.” Id. at col. 6, ll. 22–26. “[T]his greatly reduces
`system cost by eliminating the need for an expensive block of SRAM.” Id.
`at col. 6, ll. 26–29. In a preferred embodiment, MCA 200 “is an
`application[] specific integrated circuit (ASIC) for arbitrating memory bus
`110 between the various bus masters subject to the constraints each imposes
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`to provide optimal bandwidth for each, particularly the DSP which is
`responsible for a significant amount of real-time signal processing.” Id. at
`col. 6, ll. 46–52.
`
`b. MPEG (Ex. 1004)
`MPEG describes the coded representation of video for digital storage
`media and specifies the decoding process for the MPEG-2 standard.
`Ex. 1004, 1. The MPEG standard was known and accessible at least as of
`August of 1993. Ex. 1008 ¶ 8.
`
`2. Analysis
`We are persuaded by Petitioner’s arguments and cited evidence that
`the combination of the teachings of Bowes and MPEG teaches or suggests
`all of the recited limitations of challenged claims 1 and 2. Pet. 38–47; see
`Inst. Dec. 24–29. In particular, Bowes discloses supporting video
`applications (Ex. 1003, col. 1, ll. 24–41), and specifically discloses video
`controllers 131 coupled to memory bus 110 (id. at col. 6, ll. 6–18). Pet. 39.
`Moreover, DSP 20 performs “image processing.” Id. (citing Ex. 1003, col.
`6, ll. 33–38). Thus, Petitioner argues that Bowes discloses that both CPU 10
`(i.e., the “processor” of claim 1) and DSP 20 (i.e., the “video circuit” of
`claim 1) are attached to memory bus 110, from which they access main
`memory subsystem 14. Pet. 39. In addition, Petitioner argues that Bowes
`discloses an arbiter (i.e., MCA 200) and each of the arbiter functions of
`“providing access” in an idle state (Ex. 1003, col. 7, l. 64–col. 8, l. 10, col. 8,
`ll. 28–35), “queuing a request for access” in a busy state (id. at col. 8, ll. 50–
`55, 63–65), and “queuing a request for access . . . in an order based on a
`priority “ in a queue state (id. at col. 8, ll. 50–55, col. 9, ll. 2–6, 11–14). Pet.
`44–46 (citing Ex. 1030 ¶¶ 168–170). We agree.
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`Petitioner further contends that a person of ordinary skill in the art
`would have found it obvious to combine the teachings of Bowes and MPEG
`to achieve the systems, methods, and circuits limitations recited in the
`challenged claims.
`Bowes discloses
`that DSP 20 performs “image
`processing,” id., 6:33-38, which MPEG Standard (see generally
`Ex. 1030 at ¶ 83) discloses includes video image decoding. Ex.
`1004 at 7-8 (“0.4 Decoding”), 42 (“2.4.4. The video decoding
`process”). In MPEG video decoding, MPEG Standard teaches,
`some currently decoded video images are stored for decoding
`subsequent video images. See, e.g., Ex. 1004 at 8 (§ 0.4) (“After
`all the macroblocks in the picture have been processed, the
`picture has been reconstructed. If it is an I-picture or a P-picture
`it is a reference picture for subsequent pictures and is stored,
`replacing the oldest stored reference picture.”).
`Bowes contemplates supporting video applications, Ex.
`1003 at 1:24-41, and discloses video controllers 131 coupled to
`memory bus 110, id., 6:6-18. One of ordinary skill in the art
`would have been motivated to modify Bowes’ DSP 20 in view of
`MPEG Standard to perform MPEG video decoding. At the time
`of the alleged invention of the ’753 patent, the MPEG-1 and
`MPEG-2 standards were “currently in use.” Ex. 1001, 1:53-58.
`Indeed, the ’753 patent admits that “[t]he MPEG standards
`[were] currently well accepted standards.” Ex. 1001, 2:6-9. Thus,
`modifying Bowes’ DSP 20 to perform MPEG video decoding per
`MPEG Standard would constitute a combination of familiar
`elements according to known methods to yield predictable
`results. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 401
`(2007); see also Ex. 1030, Stone Decl. ¶¶ 157-61. Indeed, the
`MPEG Standard “was developed in response to the growing need
`for a common format representing compressed video on various
`digital storage media,” which would have motivated on skilled
`in the art to modify Gulick’s multimedia engine 112 to perform
`MPEG video decoding. Ex. 1004 at 4 (§ 0.1)[; see Pet. 29]. In
`fact, it was well known in the art at the time of the alleged
`invention to employ a DSP for MPEG video processing. See Ex.
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`1017, 5:15-21; Ex. 1007, 1:62-67, Fig. 5. One of ordinary skill
`in the art would have understood that Bowes’s DSP 20, as
`modified by MPEG Standard, would be configured to receive
`data from main memory subsystem 14 corresponding to a current
`video image to be MPEG-video decoded and to output video data
`corresponding to the current video image to be displayed via
`video controllers 131, the current video image to be displayed
`adapted to be stored in main memory subsystem 14. Ex. 1030,
`Stone Decl. ¶¶ 162-63.
`Pet. 40–42. In contrast, Dr. Thornton testifies that
`the fact that Bowes not once mentioned the implementation of
`the MPEG standard or for that matter, any implementation
`involving video decoding, further indicates that a [person of
`ordinary skill in the art (POSA)] would not have been motivated
`to combine Bowes with the MPEG Standard as the Petitioner
`suggests.
`Ex. 2009 ¶ 86. We find Dr. Thornton’s testimony unpersuasive. See Reply
`21–22. The challenged claims also do not mention the MPEG Standard.
`The question is not whether Bowes expressly teaches use of the MPEG
`Standard, rather the question is whether a person of ordinary skill in the art
`would have combined the teachings of Bowes and the MPEG Standard in
`the manner recited in the challenged claims. KSR, 550 U.S. at 424 (“The
`proper question to have asked was whether a pedal designer of ordinary
`skill, facing the wide range of needs created by developments in the field of
`endeavor, would have seen a benefit to upgrading Asano with a sensor.”).
`We are persuaded that a person of ordinary skill in the art would have had
`reason to incorporate the known MPEG Standard into Bowes’s system and
`that doing so would have yielded predictable results, in order to satisfy the
`“growing need for a common format representing compressed video on
`various digital storage media.” Pet. 41–42; Reply 17; see Ex. 1032
`¶¶ 84–88.
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`Patent Owner contends that Petitioner fails to demonstrate by a
`
`preponderance of the evidence that claims 1 and 2 of the ’753 patent are
`obvious over the applied art for four reasons. PO Resp. 3–42. Specifically,
`Patent Owner contends that (a) the combination of the teachings of Bowes
`and MPEG does not teach “providing access to the main memory for a
`request for access to the main memory when the arbiter circuit is in an idle
`state” (id. at 3–5); (b) the combination of the teachings of Bowes and MPEG
`does not teach “wherein the video circuit is further configured to receive
`data from the main memory corresponding to at least one previously
`decoded video image” (id. at 5–26); (c) the combination of the teachings of
`Bowes and MPEG does not teach “an arbiter that controls access to the main
`memory” (id. at 26–32); and (d) a person of ordinary skill in the art would
`not have had reason to combine the teachings of Bowes and MPEG (id. at
`32–41). We address each contention in turn.
`
`a. “providing access to the main memory for a request for access
`to the main memory when the arbiter circuit is in an idle
`state”(Claim 1)
`Patent Owner contends that the combined teachings of Bowes and
`MPEG do not teach or suggest this limitation of challenged claim 1 because
`“the arbiter of Bowes does not have an ‘idle state.’” Id. at 3 (citing Ex. 2009
`¶ 33). We disagree.
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`As noted above, claim 1 recites that the arbiter “provid[es] access to
`the main memory for a request for access to the main memory when the
`arbiter circuit is in an idle state.” Ex. 1001, col. 15, ll. 46–53. In the “idle
`state,” “there is no device accessing the memory and there are no requests to
`access the memory.” Id. at col. 13, ll. 4–6. Petitioner argues that Bowes
`teaches a “default” state during which no other devices are requesting access
`to the memory bus, MCA 200 is idle, and memory bus 110 is assigned by
`default to, i.e., “remains parked on,” CPU 10, until some other device
`requests memory bus 110. Pet. 44 (quoting Ex. 1003, col. 8, ll. 28–35).
`Further, Petitioner argues that, when MCA 200 is in this default state, MCA
`200 may provide access to CPU 10 by default or to some other device, such
`as DSP 20, upon receipt of a request. Id. As discussed below, we are
`persuaded that access to the memory bus is tantamount to access to the main
`memory.
`Patent Owner contends, however, that, because Bowes’s system
`assigns access to CPU 10 by default; “in Bowes, even if there are no requests
`to access the memory, the CPU is given access to the memory.” PO Resp. 4
`(citing Ex. 2009 ¶ 34). According to Patent Owner, because CPU 10 is
`given access by default, it is not the case in Bowes that no device is
`accessing the memory. Id. Nevertheless, Patent Owner conflates the
`concepts of being given access, e.g., the memory bus being assigned to a
`device, and accessing. Reply 3; see Tr. 45:5–46:10, 82:17–84:23
`(discussing the difference between assignment and accessing). Although
`Bowes’s system assigns access to CPU 10 in the default state, this does not
`mean that CPU 10 accesses the memory bus. See Ex. 1032 ¶ 91. Thus,
`Bowes’s default state does not preclude the situation in which CPU 10 has
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`been assigned access to the memory bus, but currently is not accessing the
`memory bus. Reply 2; see Ex. 1001, col. 8, ll. 29–30 (“the CPU 10 does not
`issue bus request signals”), 32–34 (“The CPU is also provided with one time
`slot in the priority scheme . . . in which it is granted the memory bus.”).
`For these reasons, we are persuaded that Petitioner has demonstrated
`by a preponderance of the evidence that Bowes and MPEG teach this
`limitation of challenged claim 1.
`
`b. “the video circuit is further configured to receive data from the
`main memory corresponding to at least one previously decoded
`video image” (Claim 2)
`Patent Owner contends that the combined teachings of Bowes and
`MPEG do not teach or suggest this limitation of challenged claim 2 for three
`reasons. First, Bowes does not teach a video circuit that is linked to a main
`memory, rather than a dedicated memory. PO Resp. 5–8, 11–19. Second,
`Bowes does not teach that its DSP receives a previously decoded video
`image from the main memory. Id. at 8–11, 19–24. Third, Bowes does not
`teach that the DSP reads data from and writes data to a main memory. Id. at
`24–26. Again, we disagree with each of Patent Owner’s reasons.
`
`i. Whether Bowes’s DSP Teaches a “Video Circuit”
`Patent Owner asserts that Bowes’s DSP does not teach a “video
`circuit,” as recited in the challenged claims. Id. at 11–19. In particular,
`Patent Owner contends that Bowes only mentions the word “video” four
`times and only once in relation to its system. Id. at 11. Bowes only uses the
`word “video” in relation to the NuBus peripheral bus video controller and
`not in relation to DSP 20. Id. Consequently, Patent Owner contends that
`“Bowes does not state that the DSP is suitable for video compression and
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`decompression applications such as the MPEG Standard” (id. at 11 (citing
`Ex. 2009 ¶ 47)), and that “a [person of ordinary skill in the art] would
`recognize that audio processing, speech processing and modem emulation
`are clearly distinct from video compression and decompression. The same is
`true with respect to ‘image processing.’” (id. at 11–12 (citing Ex. 2009
`¶ 47)). See Tr. 62:11–65:4.
`Although Bowes explicitly teaches the use of DSP 20 for “image
`processing” (Ex. 1003, col. 6, l. 35), Bowes does not teach explicitly the use
`of DSP 20 for video compression and decompression. The grounds of
`unpatentability, however, are based upon a modification of the teachings of
`Bowes’s DSP 20 to perform video decoding according to the MPEG
`Standard. Pet. 41 (“Bowes contemplates supporting video applications,
`Ex. 1003 at 1:24-41, and discloses video controllers 131 coupled to memory
`bus 110, id., 6:6-18. One of ordinary skill in the art would have been
`motivated to modify Bowes’ DSP 20 in view of MPEG Standard to perform
`MPEG video decoding.”); see Ex. 1030 ¶¶ 162–63. Dr. Stone testifies that
`“Bowes discloses that DSP 20 performs ‘image processing,’ Ex. 1003 at
`6:33-38, which MPEG Standard discloses includes video image decoding,
`Ex. 1004 at 7-8 (§ 0.4 Decoding), 42 (§ 2.4.4. The video decoding process).”
`Ex. 1030 ¶ 158. Bowes further teaches that DSP 20 “may be an off-the-shelf
`DSP.” Ex. 1003, col. 2, ll. 21–22.
`As noted above, neither party has proposed a construction for “video
`circuit.” See supra Section III. Moreover, neither the challenged claims nor
`the Specification of the ’753 patent requires that the “video circuit” must be
`suitable for video decompression, and “neither Patent Owner nor its expert
`dispute that the prior art included ‘off the shelf’ DSPs capable of video
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`compression and decompression pursuant to the MPEG Standard or that a
`skilled artisan could have implemented the Bowes/MPEG combination using
`such prior art DSPs.” Reply 4 (citing Ex. 1032 ¶¶ 8–10); see also Ex. 1032
`¶ 10 (“[A] person of skill would understand Bowes to be pointing out that
`any available DSP could potentially be used in the system of Bowes”)(citing
`Exs. 1006, 1035, 1036, 2008); Ex. 1023, col. 6, ll. 20–22 (“digital system
`chip 112 also preferably includes a general purpose DSP engine 206 which
`is programmable to perform various functions such as MPEG decoding.”
`(emphasis added)). Thus, even assuming that Bowes’s “image processing”
`does not teach video decompression expressly, we, nevertheless, are
`persuaded that “off the shelf” DSPs existed that were capable of
`decompressing MPEG video, and that it was within the level of ordinary
`skill in the art to use, in the system of Bowes, such a DSP as DSP 20 to
`operate in accordance with the well-known MPEG standa