Paper No. __
`Filed: June 24, 2015
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`HTC Corporation,
`HTC America, Inc.,
`LG Electronics, Inc.,
`Samsung Electronics Co., Ltd., and
`Samsung Electronics America, Inc.
`Petitioners
`
`v.
`
`
`
`Parthenon Unified Memory Architecture LLC
`Patent Owner
`
`INTER PARTES REVIEW OF U.S. PATENT NO. 7,321,368
`Case IPR No.: To Be Assigned
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,321,368
`UNDER 35 U.S.C. §§ 311-19 AND 37 C.F.R. § 42.100 et seq.
`
`
`
`
`
`
`
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`

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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`
`TABLE OF CONTENTS
`
`V.
`
`
`I.
`INTRODUCTION ........................................................................................... 1
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(b) .............................. 2
`A.
`Real Parties-in-Interest .......................................................................... 2
`B.
`Related Matters ...................................................................................... 2
`C.
`Lead and Back-Up Counsel ................................................................... 3
`D.
`Service Information ............................................................................... 4
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 5
`III.
`IV. CERTIFICATION OF GROUNDS FOR STANDING UNDER
`37 C.F.R. § 42.104(a) ...................................................................................... 5
`IDENTIFICATION OF CHALLENGES UNDER 37 C.F.R.
`§§ 42.22 AND 42.104(b) ................................................................................. 5
`A.
`Statutory Grounds of Challenge ............................................................ 5
`B.
`The Proposed Grounds are Not Redundant ........................................... 6
`VI. THE ’368 PATENT ......................................................................................... 7
`VII. CLAIM CONSTRUCTION ............................................................................ 8
`A.
`Claim Terms To Be Construed .............................................................. 8
`1.
`“decoder” .................................................................................... 8
`2.
`“fast bus” ................................................................................... 10
`3.
`“decoder directly supplies a display device with an
`image” ....................................................................................... 11
`Expiration of the ’368 Patent .............................................................. 12
`B.
`VIII. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 13
`IX. SPECIFIC GROUNDS OF CHALLENGE ................................................... 13
`A. Ground A: Rathnam Anticipates, under 35 U.S.C. § 102,
`claims 1-3, 5, 7, 13-15, 17-21, and 23-25 ........................................... 13
`Ground B: Bowes in view of MPEG Standard renders
`obvious, under 35 U.S.C. § 103, claims 1, 5, 7, 13, 15,
`18, 20, 24, and 25 ................................................................................ 35
`
`B.
`
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`
`C.
`
`Ground C: Bowes, in view of MPEG Standard and
`Rathnam, renders obvious, under 35 U.S.C. § 103, claims
`17, 19, and 23 ...................................................................................... 51
`D. Ground D: Bowes, in view of MPEG Standard, and
`Stearns, renders obvious, under 35 U.S.C. § 103, claims
`2, 3, 14, and 21 .................................................................................... 55
`CONCLUSION .............................................................................................. 60
`
`
`X.
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`
`ii
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
`
`
`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Federal Cases
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) .......................................................................... 38, 54, 58, 59
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ................................................ 8, 12, 13
`
`Parthenon Unified Memory Architecture LLC v. Apple, Inc.,
`No. 2:15-cv-00621-JRG-RSP (E.D. Tex.) ............................................................ 3
`
`Parthenon Unified Memory Architecture LLC v. HTC Corp. et al.,
`No. 2:14-cv-00690-RSP (E.D. Tex.) .................................................................... 3
`
`Parthenon Unified Memory Architecture LLC v. Huawei Techs. Co.,
`Ltd. et al.,
`No. 2:14-cv-00687-JRG-RSP (E.D. Tex.) ............................................................ 3
`
`Parthenon Unified Memory Architecture LLC v. LG Elecs., Inc. et al.,
`No. 2:14-cv-00691-JRG-RSP (E.D. Tex.) ............................................................ 3
`
`Parthenon Unified Memory Architecture LLC v. Motorola Mobility,
`Inc.,
`No. 2:14-cv-00689-JRG-RSP (E.D. Tex.) ............................................................ 3
`
`Parthenon Unified Memory Architecture LLC v. Qualcomm Inc. et al.,
`No. 2:14-cv-00930-JRG-RSP (E.D. Tex.) ............................................................ 3
`
`Parthenon Unified Memory Architecture LLC v. Samsung Elecs. Co.,
`Ltd. et al.,
`No. 2:14-cv-00902-JRG-RSP (E.D. Tex.) ............................................................ 3
`
`Parthenon Unified Memory Architecture LLC v. ZTE Corp. et al.,
`No. 2:15-cv-00225-JRG-RSP (E.D. Tex.) ............................................................ 3
`
`In re Rambus, Inc.,
`694 F.3d 42 (Fed. Cir. 2012) .............................................................................. 12
`
`iii
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`

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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
`
`
`STMicroelectronics, Inc. v. Motorola Inc. et al.,
`No. 4:03-cv-00276-LED (E.D. Tex.) .................................................................... 3
`
`Toyota Motor Corp. v. Hagenbuch,
`IPR2013-00483, Paper No. 37 (Dec. 5, 2014) .................................................... 12
`
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................ 8
`
`In re Yamamoto,
`740 F.2d 1569 (Fed. Cir. 1984) ............................................................................ 8
`
`In re Zletz,
`13 USPQ2d 1320 (Fed. Cir. 1989) ....................................................................... 8
`
`Federal Statutes
`
`35 U.S.C. 102(a) ........................................................................................................ 6
`
`35 U.S.C. 102(b) ........................................................................................................ 6
`
`35 U.S.C. 102(e) ........................................................................................................ 6
`
`35 U.S.C. § 103 .................................................................................................passim
`
`35 U.S.C. § 112 .......................................................................................................... 8
`
`35 U.S.C. § 311 ........................................................................................................ 60
`
`Regulations
`
`37 C.F.R. § 42.6(e) ..................................................................................................... 1
`
`37 C.F.R. § 42.8(b) .................................................................................................... 2
`
`37 C.F.R. § 42.15(a) ................................................................................................... 5
`
`37 C.F.R. § 42.22 ....................................................................................................... 5
`
`37 C.F.R. § 42.101 ................................................................................................... 54
`
`37 C.F.R. § 42.104(a) ................................................................................................. 5
`
`37 C.F.R. § 42.104(b) ................................................................................................ 5
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`iv
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`77 Fed. Reg. 48,756 (Aug. 14, 2012) ........................................................................ 8
`
`Other Authorities
`
`Office Patent Trial Practice Guide ............................................................................. 8
`
`
`
`
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`v
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`

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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
`
`LIST OF EXHIBITS
`
`International Organization for Standardization, “ISO/IEC 11172-2:
`Information technology—Coding of moving pictures and associated
`audio for digital storage media at up to about 1,5 Mbit/s—Part2:
`Video,” (1st ed. Aug. 1, 1993) (“MPEG Standard”)
`
`S. Rathnam et al., “An Architectural Overview of the Programmable
`Multimedia Processor, TM-1,” IEEE Proceedings of COMPCON ’96,
`pp. 319-326 (1996) (“Rathnam”)
`
`R.J. Gove, “The MVP: A Highly-Integrated Video Compression
`Chip,” Proceedings of the IEEE Data Compression Conference (DCC
`‘94), pp. 215-224 (March 29-31, 1994).
`
`Ex. 1007 U.S. Patent No. 5,774,676 (“Stearns”)
`
`Ex. 1008 Declaration of Dr. Santhana Chari (“Chari Decl-”)
`
`Ex. 1009
`
`International Organization for Standardization, Website of ISOHEC
`1 1 172-2
`
`Ex. 1010 WorldCat Entry for Rathnam
`
`Ex. 1011
`
`Patent Owner Claim Construction Brief in Case No. 2: 14-cv-690,
`April 7, 2015
`
`Ex. 1012
`
`Patent Owner Claim Construction Brief in Case No. 2: 14-cv-902, June
`
`18, 2015
`
`Ex. 1019
`
`Shanley, et al., “PCI System Architecture,” Addison-Wesley
`Publishing Company, 1995 (3rd ed.) (“Shanley”)
`
`Ex. 1020
`
`Stone, H., “Microcomputer Interfacing,” Addison-Wesley Publishing
`
`vi
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`

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`Petition for Inter Partes Review of U_S_ Pat. No. 7,3213 68
`
`2
`
`Ex. 1023
`
`U_S_ Patent No. 5,797,028 (“Gulick 028”)
`
`Ex. 1024
`
`“Accelerated Graphics Port Interface Specification,” Intel
`Corporation, July 31, 1996 (Revision 1.0) (“AG ”)
`
`Ex. 1025 VESA Unified Memory Architecture Hardware Specifications
`Proposal,” Version 1_0p (“VUJI/IA”)
`
`vii
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
`
`
`I.
`
`INTRODUCTION
`Petitioners1 respectfully request inter partes review of claims 1-3, 5, 7, 13-
`
`15, 17-21, and 23-25 (the “Challenged Claims”) of U.S. Patent No. 7,321,368 (“the
`
`’368 patent”) (Ex. 1001). This Petition shows, by a preponderance of the evidence,
`
`that there is a reasonable likelihood that Petitioner will prevail on the Challenged
`
`Claims of the ’368 patent.
`
`The ’368 patent concerns arbitrating access to a memory shared between a
`
`video decoder and another device, such as a central processing unit (CPU). See Ex.
`
`1001, Abstract, 5:20-27. Conventionally, the ’368 patent alleges, a video decoder
`
`would have its own dedicated memory to allow it to operate in real time. See id.,
`
`2:51-59, 3:21-28. The dedicated memory would remain unused most of the time
`
`and significantly increase costs. See id., 2:51-59. To eliminate the problem of a
`
`dedicated memory, the ’368 patent proposes having the video decoder share
`
`memory with other devices. See id., 5:9-64. The ’368 patent accomplishes this
`
`using an arbiter, which arbitrates between the video decoder and the device when
`
`one of them requests access to the shared memory. See id.
`
`But by the ’368 patent’s priority date, others had solved the same problem of
`
`1 “Petitioners” refers collectively to HTC Corporation, HTC America, Inc., LG
`
`Electronics, Inc., Samsung Electronics Co., Ltd., and Samsung Electronics
`
`America, Inc.
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`a dedicated memory using the same arbitration scheme. For example, Rathnam
`
`(Ex. 1005) describes a shared memory multimedia processing system that
`
`arbitrates access to the memory between an MPEG decoder and multiple other
`
`components including microprocessors. In addition, Bowes (Ex. 1003) eliminates
`
`the need for dedicated SRAM memory for its digital signal processor (DSP) 20 by
`
`arbitrating between DSP 20 and the computer system when one of them requests
`
`access to the shared memory (main memory subsystem 14); see also Stone Decl.,
`
`Ex. 1030, ¶¶ 1-69 (discussing Exs. 1019, 1020, 1023, 1024, 1025, 1026, 1027,
`
`1028, and 1029).
`
`As such, the ’368 patent describes nothing new. As explained below, the
`
`prior art anticipates and/or renders obvious each of the Challenged Claims.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(b)
`A. Real Parties-in-Interest
`The real parties-in-interest are HTC Corporation, HTC America, Inc., LG
`
`Electronics, Inc., LG Electronics U.S.A., Inc., LG Electronics MobileComm
`
`U.S.A., Inc., Samsung Electronics Co., Ltd., and Samsung Electronics America,
`
`Inc.
`
`B. Related Matters
`The following would affect, or be affected by, a decision in this proceeding:
`
`1.
`
`U.S. district court actions in which Patent Owner asserted the ’368
`
`patent: Parthenon Unified Memory Architecture LLC v. Huawei Techs. Co., Ltd. et
`
`-2-
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`al., No. 2:14-cv-00687-JRG-RSP (E.D. Tex.); Parthenon Unified Memory
`
`Architecture LLC v. Motorola Mobility, Inc., No. 2:14-cv-00689-JRG-RSP (E.D.
`
`Tex. ); Parthenon Unified Memory Architecture LLC v. HTC Corp. et al., No.
`
`2:14-cv-00690-RSP (E.D. Tex.); Parthenon Unified Memory Architecture LLC v.
`
`LG Elecs., Inc. et al., No. 2:14-cv-00691-JRG-RSP (E.D. Tex.); Parthenon Unified
`
`Memory Architecture LLC v. Samsung Elecs. Co., Ltd. et al., No. 2:14-cv-00902-
`
`JRG-RSP (E.D. Tex.); Parthenon Unified Memory Architecture LLC v. Qualcomm
`
`Inc. et al., No. 2:14-cv-00930-JRG-RSP (E.D. Tex. ; Parthenon Unified Memory
`
`Architecture LLC v. ZTE Corp. et al., No. 2:15-cv-00225-JRG-RSP (E.D. Tex.);
`
`and Parthenon Unified Memory Architecture LLC v. Apple, Inc., No. 2:15-cv-
`
`00621-JRG-RSP (E.D. Tex).
`
`2.
`
`STMicroelectronics, Inc. v. Motorola Inc. et al., No. 4:03-cv-00276-
`
`LED (E.D. Tex.), in which Patent Owner’s predecessor-in-interest asserted U.S.
`
`Patent No. 5,812,789, which is related by subject matter to the ’368 patent.
`
`Petitioners have filed, or will file shortly, inter partes review petitions
`
`against four other patents that are part of the same continuation family: U.S. Patent
`
`Nos. 7,542,045; 7,777,753; 8,054,315; and 8,681,164. Because these patents are
`
`substantively similar, Petitioners request, for efficiency and consistency, that the
`
`same panel be assigned to all five petitions.
`
`C. Lead and Back-Up Counsel
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
`
`Powers of attorney are submitted with this Petition. For Petitioners HTC
`
`Corporation and HTC America, Inc., lead counsel is Joseph A. Micallef (Reg. No.
`
`39,772, jmicallef@sidley.com), and back-up counsel is Cameron A. Zinsli (Reg.
`
`No. 70,028, czinsli@sidley.com). The mailing address
`
`for all PTAB
`
`correspondence is Sidley Austin LLP, 1501 K Street, N.W., Washington D.C.
`
`20005 (Telephone: 202-736-8000 / Facsimile: 202-736-8711).
`
`For Petitioner LG Electronics, Inc., lead counsel is Rajeev Gupta (Reg. No.
`
`55,873, LGE_Finnegan_PUMAIPR@finnegan.com), and backup counsel is Darren
`
`M. Jiron (Reg. No. 45,777). The mailing address for all PTAB correspondence is
`
`FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP, 901
`
`New York Avenue, N.W., Washington, D.C. 20001-4413 (Telephone: 202-408-
`
`4000 / Facsimile: 202-408-4400).
`
`For Petitioners Samsung Electronics Co., Ltd. and Samsung Electronics
`
`America, Inc., lead counsel is Allan M. Soobert (Reg. No. 36,284, Samsung-
`
`PUMA-IPR@paulhastings.com), and back-up counsel is Naveen Modi (Reg. No.
`
`46,224, Samsung-PUMA-IPR@paulhastings.com). The mailing address for all
`
`PTAB correspondence is Paul Hastings LLP, 875 15th Street NW, Washington DC
`
`20005 (Telephone: 202-551-1700 / Facsimile: 202-551-1705).
`
`Service Information
`
`D.
`Counsel for Petitioners consent to service by electronic mail and hand
`
`-4-
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`delivery to the postal mailing addresses of respective lead counsel designated
`
`above.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The required fees are submitted herewith. The PTO is authorized to charge
`
`any additional fees due at any time during this proceeding to Deposit Account No.
`
`50-2613.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING UNDER
`37 C.F.R. § 42.104(a)
`Petitioners certify that the ’368 patent is available for inter partes review,
`
`and that Petitioners are not barred or estopped from requesting inter partes review
`
`challenging the claims on the grounds identified in this Petition. Each Petitioner
`
`was served a complaint asserting infringement of the ’368 patent no earlier than
`
`June 24, 2014. No Petitioner, real party-in-interest, or privy of a Petitioner was
`
`served before that date. The Petitioners and real parties-in-interest have not
`
`initiated a civil action challenging the validity of the ’368 patent.
`
`V.
`IDENTIFICATION OF CHALLENGES UNDER 37 C.F.R. §§ 42.22
`AND 42.104(b)
`A.
`The Challenged Claims are unpatentable on the following grounds:
`
`Statutory Grounds of Challenge
`
`Ground A. Under pre-AIA 35 U.S.C. § 102, Rathnam (Ex. 1005) anticipates
`
`claims 1-3, 5, 7, 13-15, 17-21, and 23-25 (see Section IX.A)
`
`Ground B. Under pre-AIA 35 U.S.C. § 103, Bowes (Ex. 1003) in view of MPEG
`
`-5-
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`Standard (Ex. 1004) renders obvious claims 1, 5, 7, 13, 15, 18, 20, 24,
`
`and 25 (see Section IX.B)
`
`Ground C. Under pre-AIA 35 U.S.C. § 103, Bowes (Ex. 1003), in view of MPEG
`
`Standard (Ex 1004) and Rathnam (Ex. 1005), renders obvious claims
`
`17, 19, and 23 (see Section IX.C)
`
`Ground D. Under pre-AIA 35 U.S.C. § 103, Bowes (Ex. 1003), in view of MPEG
`
`Standard (Ex 1004) and Stearns (Ex. 1007), renders obvious claims 2,
`
`3, 14, and 21 (see Section IX.D)
`
`Rathnam was published during the IEEE COMPCON ’96 Conference in
`
`February 1996 (see Ex. 1005 at 4), was available at the Library of Congress at least
`
`as of April 4, 1996 (see id. at 2), and was indexed in the WorldCat library on April
`
`23, 1996 (Ex. 1010 at 1), and thus qualifies as prior art at least under pre-AIA 35
`
`U.S.C. 102(a). Bowes was filed on January 28, 1994, and thus qualifies as prior art
`
`at least under pre-AIA 35 U.S.C. 102(e). MPEG Standard was published in August
`
`1993, and thus qualifies as prior art at least under pre-AIA 35 U.S.C. 102(b). Ex.
`
`1004 at 1-2; Ex. 1008, ¶¶ 4-8; Ex. 1009 at 1. Stearns was filed on October 3, 1995,
`
`and thus qualifies as prior art at least under pre-AIA 35 U.S.C. 102(e).
`
`The Proposed Grounds are Not Redundant
`
`B.
`Ground A and Grounds B-D both challenge claims 1-3, 5, 7, 13-15, 17-21,
`
`and 23-25 of the ’368 patent. However, the grounds are not redundant because of
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`-6-
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`several significant differences. For example, Ground A and Grounds B-D
`
`challenge the claims under different statutory bases. Therefore, Patent Owner may
`
`be entitled to different defenses for the references applied in those grounds.
`
`Additionally, as an example, Rathnam, the only reference in Ground A, addresses
`
`the claimed “decoder” in a different way than Bowes, the primary reference in
`
`Grounds B-D (as explained below, Ground A relies on two components working in
`
`tandem, whereas Ground B relies on a single component). Therefore, for at least
`
`these reasons, Petitioners respectfully request the Board adopt all proposed
`
`Grounds in this petition, particularly because not adopting one of the grounds may
`
`potentially affect how Petitioners may later challenge the validity of the ’368
`
`patent.
`
`VI. THE ’368 PATENT
`The ’368 Patent, entitled “Electronic System and Method for Display Using
`
`a Decoder and Arbiter to Selectively Allow Access to a Shared Memory,” issued
`
`on January 22, 2008. The ’368 Patent is a continuation of application no.
`
`09/539,729, filed on March 30, 2000, which is a continuation of application no.
`
`08/702,910, filed on August 26, 1996. The ’368 Patent has 25 claims, including
`
`independent claims 1, 5, 7, 8, 13, and 20.
`
`Rathnam, Bowes, and MPEG Standard were not considered during
`
`prosecution of the ’368 patent. See, e.g., Ex. 1001 at 1-5 (References Cited); see
`
`-7-
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
`
`
`generally Ex. 1002.
`
`VII. CLAIM CONSTRUCTION
`inter partes review,
`In
`the Board applies the broadest reasonable
`
`interpretation (“BRI”) standard to construe claim terms of an unexpired patent.2
`
`Under the BRI standard, terms are given their “broadest reasonable interpretation,
`
`consistent with the specification.” In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir.
`
`1984); Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,764 (Aug. 14,
`
`2012). Claim terms are “generally given their ordinary and customary meaning,”
`
`which is the meaning that the term would have to a person of ordinary skill in the
`
`art. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (quoting
`
`Phillips v. AWH Corp., 415 F.3d 1303, 1312, 1313 (Fed. Cir. 2005) (en banc)).
`
`A. Claim Terms To Be Construed
`For purposes of this proceeding only, Petitioners propose BRI constructions
`
`for the following terms. All remaining terms should be given their plain meaning.
`
`1.
`
`“decoder”
`
`
`2 Because the standards applied in litigation differ from PTO proceedings, any
`
`interpretation of claim terms herein is not binding upon Petitioners in any related
`
`litigation. See In re Zletz, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989). Petitioners
`
`reserve their rights to make all arguments in the district court with respect to claim
`
`construction and on other grounds (e.g., 35 U.S.C. § 112).
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`-8-
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`Proposed BRI Construction: “hardware and/or software that translates data
`
`streams into video or audio information”
`
`The term “decoder” appears in claims 1, 2, 4, 5, 7, 8, 12-14, 16, 17, and 19-
`
`23. The ’368 patent generally refers to a decoder as a “video and/or audio
`
`decompression device.” Ex. 1001, 2:5-7. According to the specification, “[a]ny
`
`conventional decoder including a decoder complying to the MPEG-1, MPEG-2,
`
`H.261, or H.261 standards, or any combination of them, or any other conventional
`
`standard can be used as the decoder/encoder.” Id., 15:51-54 (emphasis added). A
`
`conventional decoder around the time of the alleged invention of the ’368 patent
`
`was understood to include “any hardware or software system that translates data
`
`streams into video or audio information.” Ex. 1014 at 3.
`
`Consistent with
`
`this understanding of a decoder,
`
`the ’368 patent
`
`acknowledges that a decoder can be implemented as hardware or software. See,
`
`e.g., Ex. 1001, 6:66-7:6. In one example, the specification explains that video
`
`decoding can be performed by hardware and audio decoding can be performed by
`
`software. Id., 7:2-10. Similarly, claim 7 of the ’368 patent discloses a scenario in
`
`which a “first bus interface” is associated with both a decoder and a central
`
`processing circuit (the central processing circuit presumably performing some of
`
`the software-based functionality of the decoder), and a “second bus interface” is
`
`only associated with the central processing circuit. Id., 16:63-64, 17:9-13.
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`-9-
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
`
`and
`
`’368
`
`patent
`
`specification
`
`Therefore,
`
`consistent with
`
`the
`
`contemporaneous dictionary definitions, the BRI of the term “decoder” is
`
`“hardware and/or software that translates data streams into video or audio
`
`information.”
`
`“fast bus”
`
`2.
`The term “fast bus” appears in independent claim 7. The ’368 patent
`
`describes a “fast bus” as “any bus having a bandwidth sufficient to allow the
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`system to operate in real time.” Ex. 1001, 5:42-45 (emphasis added); see also id.,
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`8:1-9 (explaining how to determine whether a bus’s bandwidth is sufficient for
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`such operation). The specification provides examples of fast buses that purportedly
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`permit “real time” data transfers between a decoder and a memory under at least
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`some bandwidth calculations, including the industry standard PCI bus. Id., 5:42-45.
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`In contrast, during prosecution of U.S. Patent No. 8,681,164 (“the ’164 patent”), a
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`child of the ’368 patent (see Ex. 1015 at 1), Applicants argued (1) a bus’s latency,
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`irrespective of bandwidth, determines whether a bus satisfies a “real time”
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`requirement, and, as a result, (2) a PCI bus does not satisfy a “real time”
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`requirement. Ex. 1016 at 8; see also Microsoft Corp. v. Multi-Tech Sys., Inc., 357
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`F.3d 1340, 1350 (Fed. Cir. 2004) (finding an applicant’s statement to the USPTO
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`in a later application is relevant to the scope of the claimed invention in an earlier
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`issued patent); In re Katz Interactive Call Processing Patent Litig., 639 F.3d 1303,
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`1325 (Fed. Cir. 2011). The discrepancy between the description of “real time” in
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`the ’368 patent and the prosecution history of the ’164 patent would have caused
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`one of ordinary skill in the art not to be informed, with reasonable certainty, about
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`the scope of a bus that satisfies the “real time” requirement. Nautilus, Inc. v. Biosig
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`Instruments, Inc., 134 S. Ct. 2120, 2123 (2014). Therefore, the ’368 patent’s
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`description of a “fast bus” as “any bus having a bandwidth sufficient to allow the
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`system to operate in real time,” Ex. 1001, 5:42-45, would have also been
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`indefinite.
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`In related litigation, Patent Owner has argued that the term “fast bus” is a
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`“bus with a bandwidth equal to or greater than the required bandwidth to operate in
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`real time.” Ex. 1011 at 18; Ex. 1012 at 16. Therefore, while Petitioners submit that
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`claim 7’s recitation of a “fast bus” is indefinite, Petitioners have applied Patent
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`Owner’s interpretation of “fast bus” when applying the prior art to claim 7.
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`“decoder directly supplies a display device with an image”
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`3.
`The term “decoder directly supplies a display device” appears in dependent
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`claims 14 and 21. Petitioners submit that the ’368 patent does not describe any
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`decoder that directly supplies a display device with an image, let alone how a
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`decoder would directly supply a display device with an image. However, Patent
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`Owner may argue that in the ’368 patent, a decoder directly supplies display
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`adapter with an image, and the display adapter is considered to be a part of the
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`display device. See, e.g., Ex. 1001, 5:46-49 (“the decoder directly supplies a
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`display adapter of the screen with an image under decoding which is not used to
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`decode a subsequent image”), 10:65-66 (“[t]he display adapter then supplies these
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`data to a display device such as a screen”). In related litigation, Patent Owner has
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`argued that an image is “directly supplied” if it is supplied without being stored in
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`main memory for purposes of decoding subsequent images. Ex. 1011 at 19; Ex.
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`1012 at 22; see also Ex. 1013 at 1. Therefore, while Petitioners submit that claims
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`14 and 21 lack written description support, Petitioners have applied Patent
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`Owner’s interpretation when applying the prior art to claims 14 and 21.
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`Expiration of the ’368 Patent
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`B.
`In addition to the BRI analysis above, Petitioners recognize that the ’368
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`patent appears set to expire in September 2016, which will be subsequent to the
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`requested institution of trial in this proceeding, but may precede a final decision. In
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`such cases, the Board has held (citing In re Rambus, Inc., 694 F.3d 42, 46 (Fed.
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`Cir. 2012)), that it will construe patent claims, once expired, according to the
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`standard applied by the district courts by applying the principles set forth in
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`Phillips, 415 F.3d at 1312. See, e.g., Toyota Motor Corp. v. Hagenbuch, IPR2013-
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`00483, Paper No. 37 at 5 (Dec. 5, 2014). Petitioners respectfully submit that this
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`change in standards would not affect any of the proposed grounds in this Petition,
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`especially in view of Patent Owner’s interpretations of the claims under the
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`Phillips standard.
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`VIII. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art at the time of the alleged invention of
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`the ’368 patent would have had an accredited Bachelor’s degree in Electrical
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`Engineering and/or Computer Science and/or Computer Engineering and had three
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`years’ experience in the fields of data compression and overall computer system
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`architecture. This person would have been capable of understanding and applying
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`the prior art references described herein. Ex. 1030, ¶ 78-81.
`
`IX. SPECIFIC GROUNDS OF CHALLENGE
`A. Ground A: Rathnam Anticipates, under 35 U.S.C. § 102, claims 1-
`3, 5, 7, 13-15, 17-21, and 23-25
`1.
`1[pre]: “An electronic system comprising:”
`Rathnam discloses an electronic system. See, e.g., Ex. 1005, Rathnam at 12-
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`Rathnam anticipates claim 1
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`a.
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`13; see also Ex. 1030, Stone Decl. at ¶ 86. For example, Rathnam describes the
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`TM-1, which “is the first in a family of programmable multimedia processor from
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`the Trimedia product group of Philips Semiconductors.” Ex. 1005 at 12 (emphasis
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`added). Furthermore, Rathnam adds “More than just an integrated microprocessor
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`with unusual peripherals, the TM-1 microprocessor is a fluid computer system
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`controlled by a small real-time OS kernel that runs on the VLIW processor core.
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`TM-1 contains a CPU, a high bandwidth internal bus, and internal bus-mastering
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`Petition for Inter Partes Review of U-S. Pat. No. 7,321,368
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`DMA peripherals-” Id. at 12-13 (emphasis added); see also id. at Fig- 1 (annotated
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`below).
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`Main memory
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`ain memory interfac -.
`
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`
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`
`"‘3%&."&2
`
`Fcbuuo
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`
`icroprocessor syste
`
`Figure 1. TIM block diagram.
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`.
`
`mmu-4-coda Video Out
`connection to a
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`display device
`
`Microprocessor syste
`Example #2
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`b.
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`1[a]: “a main memory having stored therein data corresponding to
`images to be decoded and also decoded data corresponding to images
`that have previously been decoded;”
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`Rathnam discloses this element. See Ex. 1030, Stone Decl. at 111] 87-95. For
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`example, as shown in the armotated Figure 1, Rathnam discloses an SDRAM as its
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`main memory. Ex. 1005 at Figure 1. Rathnam discloses: “Figure 1 shows a block
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`diagram of the TM-1 chip,” which includes “a block of synchronous DRAM
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`(SDVG). .
`
`.
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`Id. at 13 (emphasis added). Further indicative that this SDRAM is
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`“main memory” is that the interface to this SDRAM is referred to as the “Main
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`Memory Interface.” See, e.g., id. at Figure 1 (armotated above).
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`Encoded (i.e., compressed) video image data is stored in this SDRAM
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`memory. See, e.g., id. at 14 (“The CPU compresses the video data in software
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`(using a set of powerful data-parallel operations) and writes the compressed data to
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`a separate area of SDRAM.”) (emphasis added).
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`
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`This compressed (i.e., encoded) video image data stored in the SDRAM, and
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`in particular MPEG encoded data may be decompressed (i.e., decoded) by the TM-
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`1 disclosed in Rathnam. See, e.g., id. at 17 (“The variable-length decoder
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`(VLD) . . . can be used to help decode MPEG-1 and MPEG-2 video streams. The
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`VLD is a memory-to-memory coprocessor.”). One of ordinary skill in the art at the
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`time of the alleged invention of the ’368 patent would have understood that
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`performing either MPEG-1 or MPEG-2 decoding would necessarily have involved
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`receiving data corresponding to images that have been previously decoded and data
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`corresponding to current images to be decoded. See, e.g., Ex. 1030, Stone Decl. at
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`¶¶ 93-95, 46, and 49; see also Ex. 1004 at 5, 24-25, 62, and 66.
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`c.
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`1[b]: “a bus coupled to the memory;”
`Rathnam discloses this element. See, e.g., Ex. 1005 at 15, Figure 1
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`(annotated above); see also Ex. 1030, Stone Decl. at ¶¶ 96-98. For example,
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`Rathnam discloses that “The internal data bus connects all internal blocks together
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`and provides access to internal control registers (in each on-chip peripheral
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`units), external SDRAM, and the external PCI bus.” Ex. 1005 at 15 (emphasis
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`added).
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`d.
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`Petition for Inter Partes Review of U.S. Pat. No. 7,321,368
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`1[c] “a decoder coupled to the bus for receiving compressed images