IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`PATENT
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`Applicants
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`Application No.
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`Filed
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`For
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`Jefferson Eugene Owen et al.
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`13/655,152
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`October 18, 2012
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`ELECTRONIC SYSTEM AND METHOD FOR
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`SELECTIVELY ALLOW'ING ACCESS TO A SHARED
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`MEMORY
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`Examiner
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`Art Unit
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`Docket No.
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`Date
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`Hau H. Nguyen
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`2677
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`850063.553C8
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`September 3, 2013
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`Mail Stop Amendment
`Commissioner for Patents
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`PO. Box 1450
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`Alexandria, VA 22313-1450
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`Commissioner for Patents:
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`AMENDMENT
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`In response to the Office Action dated April 1, 2013, please extend the period of
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`time for response two months, to expire on September 1, 2013. Enclosed are a Petition for an
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`Extension of Time and the requisite fee. Please amend the application as follows:
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`Amendments to the Claims are reflected in the listing of claims which begins on
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`page 2 of this paper.
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`Remarks begin on page 5 of this paper.
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`Page 1 of 12
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`HTC-LG-SAMSUNG EXHIBIT 1016
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`Page 1 of 12
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`HTC-LG-SAMSUNG EXHIBIT 1016
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`Amendments to the Claims:
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`This listing of claims will replace all prior versions, and listings, of claims in the
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`application:
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`1.
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`(Currently Amended) A computing device, comprising:
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`a central processing unit (CPU);
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`core logic coupled by a first bus to the CPU, the core logic having a first memory
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`interface coupleable to a shared main memory;
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`a cache memory coupled to the CPU by the first bus;
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`a decoder/encoder coupleable to the shared main memory via a second memory
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`interface;
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`an arbiter configured to receive shared memory access requests from the CPU and
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`the decoder/encoder, the arbiter configured to arbitrate access to the shared main memory; and
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`a memory bus coupled to the first memory Wienjmefiafimand the second
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`memory~eentreller interface, the memory bus configured to pass first data in real time between
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`the shared main memory and the CPU via the first memory interface, the memory bus configured
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`to pass second data in real time between the shared main memory and the decoder/encoder.
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`2.
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`(Original) The computing device according to claim 1 wherein the
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`computing device is a computer.
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`3.
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`(Original) The computing device according to claim 1 wherein the core
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`logic comprises:
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`a Peripheral Component Interconnect (PCI) core logic device.
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`4.
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`(Original) The computing device according to claim 1 wherein the core
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`logic comprises:
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`an Accelerated Graphics Port (AGP); and
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`an Enhanced Integrated Device Electronics (EIDE) interface.
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`5.
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`(Original) The computing device according to claim 4, comprising:
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`a hard disk drive; and
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`an optical disk drive, wherein the hard disk drive and the optical disk drive are
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`coupled to the core logic via the EIDE interface.
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`6.
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`(Original) The computing device according to claim 1 wherein the
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`memory bus is capable of having a bandwidth at least two times greater than the amount of data
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`carried to the decoder/encoder when the decoder/encoder decodes in real time.
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`7.
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`(Original) The computing device according to claim 6 wherein the
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`memory bus is capable of carrying up to 400Mbytes/s.
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`8.
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`(Original) The computing device according to claim 1 wherein the arbiter
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`is coupled to the second memory interface and the arbiter and second memory interface are
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`integrated with the decoder/encoder.
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`9.
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`(Original) The computing device according to claim 1 wherein the
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`decoder/encoder includes a DMA engine coupled to the second memory interface, the DMA
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`engine configured to control data bursts between the decoder/encoder and the shared main
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`memory via the second memory interface.
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`10.
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`(Original) The computing device according to claim 9 wherein the DMA
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`engine controls priority of data bursts between the decoder/encoder and the shared main memory
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`via the second memory interface.
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`11.
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`(Original) The computing device according to claim 1, comprising:
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`refresh logic coupled via a memory interface, the refresh logic configured to
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`maintain the contents of the shared main memory.
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`Application No. 13/655, 152
`Reply to Office Action dated April 1, 2013
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`12.
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`(Currently Amended) The computing device according to claim 11
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`wherein the refresh logic, the arbiter, and the second memory controller—interface are
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`monolithically integrated into the decoder/encoder.
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`13.
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`(Original) The computing deVice according to claim 4, comprising:
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`a graphics accelerator coupled to the core logic Via an Accelerated Graphics Port
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`(AGP) bus and a Peripheral Component Interconnect (PCI) bus; and
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`a local area network (LAN) controller coupled to the core logic Via the PCI bus.
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`14.
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`(Original) The computing deVice according to claim 13, comprising:
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`a frame buffer coupled to the graphics accelerator Via a frame buffer memory bus;
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`and
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`an audio codec coupled to the graphics accelerator.
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`15.
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`(Currently Amended) The computing deVice according to claim 124—13
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`wherein the frame buffer memory bus is memory bus coupled to the first memory controller
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`interface and the second memory—eontreller interface.
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`16.
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`(Original) The computing deVice according to claim 13 wherein the
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`graphics accelerator is configured to perform Video scaling and color space conversions.
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`17.
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`(Original) The computing deVice according to claim 1 wherein the
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`decoder/encoder is a cell in an integrated circuit and the CPU is a cell in the integrated circuit.
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`REMARKS
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`This communication is being filed in response to an Office Action having a
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`mailing date of April 1, 2013. Claims 1, 12, and 15 are amended. No new matter is added, and
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`all claims are believed in condition for allowance. Upon entry of the amendments herewith,
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`claims 1-17 remain pending.
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`I.
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`Information Disclosure Statement ngSg
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`An IDS submitted on December 28, 2012 was considered by the Examiner except
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`for one reference to Hsz’ng, “The Challenge of VLSI Technology to Low Bit Rate Video,” pages
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`164-168 because there was no date or year provided.
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`The Hsz’ng reference was published on pages 164-168 of VLSI Technology,
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`Systems and Applications, 1989. Proceedings of Technical Papers from the 1989 International
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`Symposium on May 17-19, 1989. A copy of the reference is resubmitted herewith along with an
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`IDS providing a date of the reference and the requisite fee. It is kindly requested that an initialed
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`copy of the IDS be provided with the next communication so as to confirm that the reference
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`listed therein has been entered and considered.
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`II. Telephone Interview Summary
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`A telephone interview was held between the attorney of record (Thomas J.
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`Satagaj) and the Examiner on August 29, 2013. The substance of the interview is provided
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`below:
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`Mr. Satagaj and the Examiner discussed certain cases in family of the present
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`case, references applied in the present case, and certain features in the claims of the present case
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`by telephone on August 29, 2013 in detail. The Examiner expressed a willingness to study the
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`Remarks made herein and further consider the case upon submission of a formal written reply to
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`the present final Office Action.
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`As discussed in detail herein, certain features of independent claim 1 are not
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`disclosed in the applied references. Accordingly, it is respectfully submitted that independent
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`claim 1 is patentable. Dependent claims 2-17 are patentably distinguished over the applied
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`references for at least the same reasons as their respective independent base claims, as well as for
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`other novel and non-obvious features recited therein. It is therefore kindly requested that the
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`rejections be reconsidered and withdrawn.
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`III. Objections to the Claims and Additional Minor Errors
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`Objections to claims 1 and 15 identify a lack of antecedent basis, respectively, for
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`the recitation, “the first memory controller and the second memory controller,” and the
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`recitation, “the frame buffer memory bus.” The informalities derive from typographical errors,
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`which are corrected in the Listing of Claims section herein. An additional informality
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`discovered in claim 12 is also corrected. Specifically, the word “interface” now replaces the
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`word “controller” in claims 1, 12, and 15. Claim 15 is also now properly dependent on claim 13.
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`Withdrawal of the objections is respectfully requested.
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`IV. Discussion of the claims and cited references
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`Claims 1-3, 8-10, and 17 are rejected under 35 U.S.C. § 103(a) as being
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`unpatentable over Gulick et al. (US. Patent No. 5,812,800) in view of Bowes et al. (US. Patent
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`No. 5,546,547).
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`Claims 4, 5, and 13-15 are rejected under 35 U.S.C. § 103(a) as being
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`unpatentable over Gulick and Bowes in view of Kikinis et al. (US. Patent No. 5,805,921) in
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`further view ofA GP Spec, (Accelerated Graphics Port Interface Specification, Version 1.0, Intel
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`Corporation).
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`Claim 16 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Gulick
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`in view of Bowes in view of Kikim's in view ofA GP Spec and in fiarther view of Potu (US.
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`Patent No. 5, 977,947).
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`Claim 6 and 7 are rejected under 35 U.S.C. § 103(a) as being unpatentable over
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`Gulick in view of Bowes and in fiarther view of LaBerge (US. Patent No. 5,771,358).
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`Claim 6 and 7 are rejected under 35 U.S.C. § 103(a) as being unpatentable over
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`Gulick in view of Bowes and in fiarther view of Derrick et al. (US. Patent No. 5,983,025).
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`In the discussion presented herein, pages, columns, line numbers, paragraphs, and
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`the like of the present application and applied references will be identified in abbreviated form.
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`For example, Page 1 (or Column 1), Lines 3-15 of an applied reference will be called out as
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`Reference 1:3-15. Similarly, the twenty-fifth paragraph of an applied reference will be called out
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`as Reference [0025].
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`Disclosed embodiments of the invention are discussed herein in comparison to the
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`applied references. The discussion of the disclosed embodiments and the discussion of the
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`differences between the disclosed embodiments and the subject matter described in the applied
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`references do not define the scope or interpretation of any of the claims. Instead, such discussed
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`differences merely help the Examiner to appreciate important claim distinctions discussed
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`thereafter. For the reasons set forth below, these rejections are respectfully traversed. It is
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`therefore kindly requested that the rejections be reconsidered and withdrawn.
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`V. Non-obviousness of Independent Claim 1
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`Turning to the claims, the structure of independent claim 1 is not rendered
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`obvious by Gulz’ck and Bowes because the applied references fail to implicitly or explicitly teach
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`or suggest every element and feature recited in claim 1. MPEP § 2143.03 instructs that a claim
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`cannot be obvious when a limitation of the claim is entirely absent from the prior art. Rather
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`than establishing that each recitation of claim 1 is taught, the Office Action merely draws
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`elements from the references and combines them in a way contrary to the suggestions in the
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`references themselves.
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`Claim 1 recites, inter alia, a CPU coupled to a shared memory via a memory bus
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`and a decoder/encoder coupled to the same shared memory via the same memory bus. The
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`memory bus is configured to pass data in real time between the shared memory and the CPU via
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`a first memory interface. The memory bus is configured to pass data in real time between the
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`shared memory and the decoder/encoder via a second memory interface.
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`The Office Action identifies the Gulz'ck reference, which describes a computer
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`system having a real-time bus and a multimedia memory. Gulz'ck at Title. As discussed herein,
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`however, Gulz’ck falls short.
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`In FIG. 1, Gulz'ck illustrates a CPU 102, a main memory 110, and three PCI
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`devices 142, 144, 146 coupled to each other via a real-time (multimedia) bus 130. In the FIG. 1
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`case, since there is only a single memory, multimedia data for Gulz'ck’s PCI devices and code and
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`data for Gulz'ck’s CPU will all be stored in the main memory 110. In order to retrieve the
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`multimedia data, Gulz'ck’s PCI devices must communicate with the main memory using PCI bus
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`120, which is n_ot a real time bus. Gulz’ck at 5:29-38. Instead, the PCI devices 142, 144, 146
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`must obtain bus mastership, which consumes PCI cycles. Id. The PCI devices in Gulz'ck’s FIG.
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`1 may communicate data between each other in real-time using the multimedia bus 130, but this
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`is different from claim 1, which calls out a memory bus configured to pass data in real time
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`between a shared main memory and a decoder/encoder.
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`In FIG. 3, Gulz'ck illustrates an alternative to his embodiment of FIG. 1. In FIG. 3,
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`Gulz’ck adds a second bus from his chipset logic 106A so that his CPU will have access to the
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`real time bus 130A. Gulz’ck at 6:36-58. Even though the embodiment of FIG. 3 permits Gulz'ck’s
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`CPU to communicate directly with his PCI Devices 142A, 144A, and 146A, the PCI devices
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`must still obtain non-real-time bus mastership in order to receive data from main memory 110.
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`Thus, Gulz'ck’s embodiment of FIG. 3 also falls short and fails to teach a memory bus configured
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`to pass data in real time between a shared main memory and a decoder/encoder.
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`Gulz’ck illustrates his final embodiment in FIG. 5. In FIG. 5, Gulz’ck adds a
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`dedicated multimedia memory 160. Multimedia data can be stored in either main memory 110
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`or multimedia memory 160. Gulz’ck at FIG. 8, 502, 9:38-45, and 10:26-29. In addition, CPU
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`code and data may be stored in either main memory 110 or multimedia memory 160. Gulz'ck at
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`9:52-67. Accordingly, there are some situations where Gulz’ck uses stores both multimedia data
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`and CPU code and data in main memory 110, and there are other situations where Gulz'ck stores
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`both multimedia data and CPU code and data in multimedia memory 160.
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`The first situation of FIG. 5 where multimedia data and CPU code and data are
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`stored in the main memory 110 has already been addressed. That is, the situation in FIG. 5 when
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`multimedia data and CPU code and data are stored in the main memory 110 is identical to the
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`situation in Gulz'ck’s FIG. 1. Claim 1 is not taught in FIG. 5 when multimedia data and CPU
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`code and data are stored in the main memory 110 because there is no memory bus configured to
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`pass data in real time between shared main memory 110 and a PCI device 142B, 144B, 164B.
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`With respect to the second FIG. 5 situation, where multimedia data and CPU code
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`and data are stored in the multimedia memoryl60, Gulz’ck describes two schemes to supply data
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`to his CPU and his PCI devices; neither of which teaches the features of claim 1. In a first
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`scheme, Gulz’ck uses two busses to access the multimedia memory. A first bus (not named)
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`couples Gulz'ck’s PCI bridge 106B to a PCI bus 120 to the multimedia memory 160. A second
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`bus (not named) couples Gulz'ck’s multimedia memory 160 to the real time bus 130B to the
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`multimedia devices 142B, 144B, 146B. Claim 1 is not taught in this scheme because Gulz’ck
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`requires two busses — a first bus to pass data between the shared memory and the CPU and a
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`second bus to pass data between the shared memory and a PCI device.
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`In a second scheme, Gulz’ck uses arbitration logic 107B to arbitrate access to the
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`multimedia memory. Gulz'ck at 9:52-67. In this case, Gulz’ck expressly states, with emphasis
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`added, that “the CPU 102 is only granted access to the multimedia memory 160 during idle times
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`or after a certain starvation period.” Thus, not only does Gulz'ck fail to illustrate the claimed
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`memory bus, Gulz’ck expressly teaches away from claim 1 by implementing either two memory
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`busses or permitting at least one of his devices to be starved when he uses only a single memory
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`bus.
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`As pointed out in the Office Action at Page 3 and with respect to Gulz'ck,
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`“multimedia memory 160 is not entirely part of the main memory.” To address this
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`shortcoming, the Office Action applies Bowes at 2:52-3:2 and 4:49-67. This is incorrect because
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`Bowes, like Gulz'ck, also fails to teach a memory bus configured to pass data in real time between
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`a shared memory and a CPU and further configured to pass data in real time between the shared
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`memory and a decoder/encoder.
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`The Bowes reference teaches a memory bus arbiter for a computer system having
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`a DSP co-processor. Bowes at Title. In Bowes’ system, a DSP 20 resides on a computer
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`system’s memory bus 110 and shares a main memory system 14 with three devices — a CPU 10,
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`an I/O interface 30, and a NuBus controller 40. Bowes at Abstract and FIG. 2. In contrast to
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`claim 1, however, Bowes only teaches a single device operable in real time.
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`The problem solved by Bowes is not targeted at bandwidth, it is targeted toward
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`cost. Bowes at 2:37-42. Bowes’ system addresses the cost problem by eliminating an expensive,
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`dedicated SRAM. Bowes at 2:52-56. Eliminating the dedicated SRAM, however, and sharing a
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`single main memory, causes other problems for Bowes’ system. When Bowes eliminated the
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`dedicated SRAM, his system lost the ability to service both his DSP and his other devices in real-
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`time. Instead, the system created by Bowes must be “finely tuned” and can only run one of his
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`devices in real-time. Bowes at 7:61-64. Bowes chose to prioritize his DSP, and rather than run
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`his other devices in real-time, Bowes gives the other devices only a “reasonable” access to the
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`memory. Bowes at FIG. 3 and 8:36-45.
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`In FIG. 2, Bowes illustrates a memory controller and arbiter (MCA) 200. The
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`MCA 200, which is illustrated in more detail in FIG. 4, follows a priority scheme illustrated in
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`FIG. 3. Bowes at 8:24-56. In the priority scheme, the bandwidth to the main memory 14 is
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`divided into 10 slots. Id. Since DSP 20 requires the largest amount of bandwidth, the DSP is
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`give 5 of the 10 slots to support real-time operation. Id. The remaining 5 slots are divided
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`amongst the CPU, the I/O Interface 30, and the NuBus controller 40. Rather than having real-
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`time operation in these other devices, Bowes expressly states that these other devices are merely
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`given “reasonable bandwidth.” Id.
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`At 9:21-53, Bowes goes on to describe a further problem created by the
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`elimination of his dedicated SRAM. That is, in Bowes ’ system, “it is necessary to limit the
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`overall total DSP bus ownership period in a given arbitration loop so as not to starve the other
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`bus masters who need to own the memory bus.” Id. Bowes implements this limit with a DSP
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`watchdog timer 241, which only permits the DSP 20 to perform a finite number of back-to-back
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`cycles in each DSP arbitration slot. Id. When a predetermined time limit is reached where the
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`DSP has owned the memory bus and where the other devices (CPU 10, I/O interface 30, NuBus
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`controller 40) have not been allowed to occur, the watchdog timer 241 will fire, and the DSP will
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`be blocked for the remainder of the present arbitration loop. Bowes at 9:45-53 and 10: 41-51.
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`Thus it is shown that not only does Bowes teach a system where 3 of his 4 devices
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`cannot run in real-time (z'.e., they are merely “not starved), Bowes does not even fiJlly let his
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`prioritized DSP 20 device run in true real time. Instead, Bowes finely tunes his system by
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`prioritizing his DSP over all of the other devices. And even though the DSP has priority, the
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`DSP may still lose its access to the shared bus when a watchdog timer fires and the other devices
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`are granted “sufficient” access to the memory to keep them from being starved. Accordingly,
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`Bowes also fails to teach a memory bus configured to pass data in real time between a shared
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`memory and a CPU; the memory bus also configured to pass data in real time between the shared
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`memory and a decoder/encoder.
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`For at least the reason that claim 1 recites a memory bus having limitations absent
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`from both Gulz’ck and Bowes, claim 1 is patentable over the applied references. Reconsideration
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`and withdrawal of the rejection to claim 1 is respectfully requested.
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`VI. Dep_endent Claims in General
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`Each dependent claim inherits the limitations of its respective base claim and all
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`intervening claims. Therefore, allowance of the respective base claim compels allowance of all
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`dependent claims. See, e.g., In re Fine, 837 F.2d 1071 (Fed. Cir. 1988); MPEP § 2143.03.
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`Accordingly, all dependent claims, including those that were referenced in the Office Action and
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`not specifically referenced in the present response, are allowable for at least reasons of their
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`respective base claims, as well as for the specific limitations recited in the dependent claims, and
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`the rejections should be withdrawn.
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`VII. M
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`It is respectfully submitted that the pending claims are in condition for allowance.
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`Any remarks in support of patentability of one claim should not be imputed to any other claim,
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`even if similar terminology is used. Any remarks referring to only a portion of a claim should
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`not be understood to base patentability on that portion; rather, patentability must rest on each
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`claim taken as a whole. No acquiescence is made to any of the Examiner’s rejections or any of
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`Application No. 13/655,152
`Reply to Office Action dated April 1, 2013
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`the Examiner’s assertions regarding what the applied reference shows or teaches, even if not
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`expressly discussed herein.
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`If the undersigned attorney has overlooked a relevant teaching in any of the
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`references, the Examiner is requested to point out specifically where such teaching may be
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`found. In light of the above amendments and remarks, Applicants respectfully submit that all
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`pending claims are allowable. Applicants, therefore, respectfully request that the Examiner
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`reconsider this application and timely allow all pending claims. The Examiner is encouraged to
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`contact Mr. Satagaj by telephone at (206) 622-4900 to discuss the above and any other
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`distinctions between the claims and the applied references, if desired. If the Examiner notes any
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`informalities in the claims, the Examiner is encouraged to contact the undersigned by telephone
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`to expediently correct such informalities.
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`The Director is authorized to charge any additional fees due by way of this
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`Amendment, or credit any overpayment, to our Deposit Account No. 19-1090. All of the claims
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`remaining in the application are now clearly allowable. Favorable consideration and a Notice of
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`Allowance are earnestly solicited.
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`All of the claims remaining in the application are now clearly allowable.
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`Favorable consideration and a Notice of Allowance are earnestly solicited.
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`Respectfully submitted,
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`SEED Intellectual Property Law Group PLLC
`
`/Thomas J. Satagaj/
`Thomas J. Satagaj
`Registration No. 62,391
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`TJS:sg
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`701 Fifth Avenue, Suite 5400
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`Seattle, Washington 98104-7092
`Phone: (206) 622-4900
`Fax: (206) 682-6031
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`244357271.DOC
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