UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION, HTC AMERICA, INC.,
`LG ELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.,
`and SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01500
`Patent 7,321,368
`____________
`
`Affidavit of Mitchell A. Thornton, Ph. D., P.E.
`
`Before me, the undersigned notary, on this day personally appeared Mitchell
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`
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`
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`A. Thornton the affiant, a person whose identify is known to me. After I
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`mentioned an oath to affiant, affiant testified:
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`1.
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`I am over the age of eighteen (18) and otherwise competent to make
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`this declaration.
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`2.
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`I earned a Bachelor of Science degree in Electrical Engineering from
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`Oklahoma State University in 1985. In 1990, I earned a Masters of Science degree
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`in Electrical Engineering from the University of Texas at Arlington. In 1993, I
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`earned a Masters of Science degree in Computer Science from Southern Methodist
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`University. I earned a Ph.D. in Computer Engineering from Southern Methodist
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`University in 1995. I am a Licensed Professional Engineer in the states of Texas,
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`Mississippi, and Arkansas. I also hold a Commercial General Radiotelephone
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`Operator License (GROL) with Ship Radar endorsement issued by the Federal
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`Communications Commission (FCC).
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`3.
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`I am currently the Cecil H. Green Chair of Engineering and Professor
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`in the Department of Computer Science and Engineering and in the Department of
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`Electrical Engineering at Southern Methodist University. Prior to 2002, I served as
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`a faculty member at Mississippi State University in the Department of Electrical
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`and Computer Engineering from 1999 through 2002. I served as a faculty member
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`at the University of Arkansas from 1995 through 1999 in the Department of
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`Computer Systems Engineering. In my university positions, my responsibilities
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`are research, teaching, and providing service in my profession. My teaching and
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`research area of expertise is generally in the area of computer engineering where I
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`specialize in hardware design for information processing systems.
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`4.
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`In addition to my academic rank of professor, I am also the Associate
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`and Technical Director of the Darwin Deason Institute for Cyber Security at
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`Southern Methodist University. The Institute mission is to advance the science,
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`policy, application and education of cyber security through basic and problem-
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`driven, interdisciplinary research. As Associate and Technical Director, I am
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`responsible for the coordination and oversight of all research projects within the
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`auspices of this multi-million dollar endowed research Institute that is comprised
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`of 11 principal investigators and their associated research teams. In this role, I am
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`routinely involved with several different state-of-the-art projects regarding the
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`technical aspects of information processing system processes, methods, software,
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`and hardware.
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`5.
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`Prior to my academic career, I was employed in the commercial sector
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`as an engineer. I was employed full-time at E-Systems, Inc. (now L3
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`Communications) in Greenville, Texas from 1986 through 1991 and resigned from
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`my position as Senior Electronic Systems Engineer in 1991 to pursue full-time
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`graduate studies in Computer Science and Computer Engineering. My duties at E-
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`Systems involved the design, analysis, implementation, and test of a variety of
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`different electronic systems including various information processing systems
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`centered around signal processing, data transmission and processing, and
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`communications systems. The communications systems I was involved with
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`processed a variety of different types of signals including data, audio, and video
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`systems. These systems were comprised of components such as receivers,
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`transmitters, computers, and special purpose circuitry.
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`6.
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`During the time I was in graduate school pursuing the Ph.D. degree, I
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`also worked part-time and full-time during the summer of 1992 at a commercial
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`integrated circuit (IC) design company named the Cyrix Corporation. At Cyrix, I
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`was a member of a design team that ultimately produced a microprocessor that is
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`compatible with the Intel Pentium. My duties included the design of the bus
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`controller and memory interface circuitry for this IC.
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`7. My practice and research covers a range of topics centered around
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`hardware design and analysis including secure circuit and embedded system
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`design, electronic design automation (EDA) methods, and algorithms for quantum,
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`classical digital systems, and large systems design. I have also maintained an
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`independent professional engineering practice since 1993 as a sole proprietor that
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`is a registered engineering firm in the state of Texas.
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`8.
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`I am a named inventor on three (3) issued patents and two (2) patent
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`applications under consideration at the USPTO. I have authored or coauthored over
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`200 scholarly publications in the fields of electrical engineering and computer
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`science.
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`9. My curriculum vitae is attached as Exhibit A to this declaration,
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`which more fully sets forth my qualifications.
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`10. Exhibit 2005 is a document titled “Developer Note Macintosh Quadra
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`840AV and Macintosh Centris660AV Computers” which bears a copy right date of
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`1993. This document is also referenced as Exhibit 2005 in my declaration which
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`was submitted in the above referenced IPR in conjunction with the Patent Owner’s
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`Response.
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`11. Based on my analysis of this document, Exhibit 2005 is in a condition
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`that creates no suspicion about its authenticity because: (1) it bears the Apple logo
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`and a copy right date of 1993 which is consistent with the period during which the
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`Quadra 840AV product was sold by Apple Computers, Inc.; (2) it was published
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`by Apple’s Developer Press which typically publishes such documents; (3) it bears
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`the trademark information from Apple Computer, Inc.; (4) it states that it was
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`published using the Apple Publishing System; and (5) it contains information that
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`is typically included in such Developer Notes by manufacturers.
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`12. Additionally, I compared the functional diagram (Figure 2-1) of
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`Exhibit 2005 with photographs which I was informed show the layout of
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`components on the circuit board of a Quadra840AV product from 1993 purchased
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`from Ebay. As shown in Exhibit B, the layout of components shown in the
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`functional diagram of Figure 2-1 matches the layout of the components on the
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`actual Quadra840AV product. This further confirms that Exhibit 2005 is in a
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`condition that creates no suspicion about its authenticity.
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`13. Further, I found this document in a place where, if authentic, such a
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`document would
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`likely be. Specifically, I found
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`this document on
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`the
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`HigherIntellect database which includes an archive of such documents, at the
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`following
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`link:
`
`tl%.E§§_§.§:{5§i§TE,;§_¥f§§?§.{i?_%§.@.§%§§}fif€5§.§?§§§:ff§§?fi§?.%§Eé§E§§§£%§§§3..a§§§§‘si‘r‘T.§§§.-£3§tE«f.*iC§§%~f§zi':§:§§§f}§§§ii‘?%§:?£§§f3§§.§§§%35:
`
`§“t2:.é_%ii%:;%§E§%§Z%t§§;:s§;t%f
`
`14.
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`I declare that all statements made herein of my knowledge are true,
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`and that all statements made on information and belief are believed to be true, and
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`that these statements were made with the knowledge that willful false statements
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`and the like so made are punishable by fine or imprisonment, or both, under
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`Section l00l of Title 18 of the United States Code.
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`“FURTHER AFFIANT SAYETH NAUGHT.”
`
`l,_
`
`5
`
`ell A. Thornton
`
`
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`SUBSCRIBED AND SWORN TO BEFORE ME by Michell A. Thornton on this
`Bl
`day of max 1"§ \/x
`, 2016, to certify which witness my hand and official seal.
`
`Notary Public in and for the State of Texas
`
`M
`
`A
`
`4826-8383-3135, V.
`
`I
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`Page 6 of 33
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`Page 6 of 33
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`
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`EXHIBIT A
`
`EXHIBIT A
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`                                       
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`Page 7 of 33
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`Page 7 of 33
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`Mitchell Aaron Thornton
`10118 Woodlake Drive
`Dallas, Texas 75243
`mitcht@ieee.org
`EDUCATION
`• Ph.D., computer engineering, Southern Methodist University, Dallas, Texas (1995)
`• M.S., computer science, Southern Methodist University, Dallas, Texas (1993)
`• M.S., electrical engineering, University of Texas at Arlington, Arlington, Texas (1990)
`• B.S., electrical engineering, Oklahoma State University, Stillwater, Oklahoma (1985)
`
`
`LICENSES AND CERTIFICATIONS
`• Licensed Professional Engineer: Texas (70202), Mississippi (14477), and Arkansas (9255)
`• Registered Engineering Firm in State of Texas: Mitchell A Thornton, PE; F-6940
`• FCC Licenses: Commercial General Radiotelephone Operator License (GROL) with ship radar
`endorsement, call sign PG00028247; Amateur Radio Operator, Extra Class License, call sign
`KE5CDJ; General Mobile Radio License, call sign WQBX350
`• Electronic Technician diploma, graduate of two-year technical electronics program in the Tulsa
`area Vocational Technical School (1981)
`
`
`EMPLOYMENT
`•
`2002-present: Cecil H. Green Chair of Engineering, (since Feb. 2015), Professor (Sept. 2006 –
`Jan. 2015), Associate Professor (2002-2006), Department of Computer Science and Engineering,
`and by courtesy, Department of Electrical Engineering, Southern Methodist University.
`Appointed with tenure in August 2002.
`2015-present: Associate Director, Darwin Deason Institute for Cyber Security, Southern
`Methodist University.
`2014-present: Technical Director, Darwin Deason Institute for Cyber Security, Southern
`Methodist University.
`1999-2002: Associate Professor, Department of Electrical and Computer Engineering, Mississippi
`State University, awarded tenure in May 2001.
`1995 to 1999: Associate Professor (1999), Assistant Professor (1995-99), Department of
`Computer Systems Engineering, and by courtesy, the Department of Electrical Engineering and
`the Department of Computer Science, University of Arkansas, awarded tenure in May 1999.
`1991 to 1995: Teaching Assistant (1991-93), Research Assistant (U.S. Superconducting
`Supercollider laboratories & NSF) (1993-95), Department of Computer Science and Engineering,
`Southern Methodist University
`1992: Design Engineer, Cyrix Corporation (full-time in summer, part time in Fall’92/1993)
`1986-1991: Sr. Electronic Systems Engineer (1990-91), Electronics Systems Engineer (1987-90),
`Engineer Analyst (1985-87), E-Systems, Inc, (now L-3 Communications Systems)
`1982-1984: Research Technician, Amoco Research Center (full-time in summers)
`
`•
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`•
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`•
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`•
`
`•
`
`•
`•
`
`•
`
`
`RESEARCH INTERESTS
`
`EDA/CAD methods and algorithms for quantum, classical digital systems, and large systems
`design including synthesis, verification, asynchronous, security, and disaster and fault tolerant
`circuit techniques. Emphasis on modeling and method development for information technology
`hardware/software security design/verification and the mathematical basis of conventional,
`asynchronous, reversible, and quantum logic. Practice areas include computer architecture,
`peripheral design, embedded systems, signal processing, and ASIC/FPGA design and
`implementation. Hardware, software, and firmware design and analysis. Deep familiarity with
`standards, various high-level software languages, numerous assemblers, EDA/CAD tools, and
`hardware description languages (both Verilog and VHDL).
`
`Page 8 of 33
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`•
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`•
`
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`AWARDS AND RECOGNITION
`•
`IEEE Computer Society, Certificate of Appreciation, for service as Chair of the Technical
`Committee on Multiple-Valued Logic, June 2010.
`•
`IEEE-USA Citation of Honor, December 2009.
`•
`Inventor Recognition Award, Semiconductor Research Corporation, April 2009.
`• Outstanding Graduate Faculty Award, Department of Computer Science and Engineering,
`awarded by the Graduate Student Council of Southern Methodist University, April 22, 2008.
`2006 Outstanding Professor of the Year Award, Department of Computer Science and
`Engineering, Southern Methodist University, awarded by the Student Engineering Joint Council
`(SEJC is composed of undergraduate students).
`• HOPE (Honoring Our Professors Excellence) Professor, three times in Spring 2006, Fall 2006,
`and Fall 2009 awarded by students on behalf of the SMU student residence organization.
`•
`2005 Gerald J. Ford Senior Research Fellow at Southern Methodist University
`• Outstanding Graduate Faculty Award, Department of Computer Science and Engineering,
`Southern Methodist University, awarded by the Graduate Student Council of the School of
`Engineering, April 21, 2005.
`• Appointed as J. Lindsey Embrey Chair Associate Professor of Computer Science and Engineering
`at Southern Methodist University for the period 1/1/04 through 12/31/05
`• Outstanding Researcher in the Department of Computer Systems Engineering at the University of
`Arkansas, (1998-1999)
`• Texas Instruments Outstanding Researcher in the Department of Computer Systems Engineering
`at the University of Arkansas, (two times in 1996-1997 and 1997-1998)
`1994 Frederick R. Terman Research Assistant Award, Department of Computer Science and
`Engineering, Southern Methodist University
`• Best paper award in the 1994 IEEE International Verilog HDL Conference
`• Honor Society Membership: Eta Kappa Nu, Sigma Xi, Upsilon Pi Epsilon, and Phi Kappa Phi
`• Listing in several editions of Who's Who in America, Who's Who in the South and Southwest,
`Who's Who in America Science and Engineering, Dictionary of International Biography, Who’s
`Who in Sciences Higher Education for over ten years
`
`
`PROFESSIONAL ACTIVITIES
`• Editorships:
`o Book series editor of the Digital Circuits and Systems series for Morgan-Claypool
`Publishers (since October 2005).
`o Member of the editorial board, International Journal of Reliable Electronic System
`Design (2007-2009).
`IEEE Computer Society Technical Committee on Multiple-Valued Logic (TCMVL), Chair
`(elected position within IEEE, 2010-2011), Member (elected position within IEEE, 2010-2011)
`(2007-2009), Responsible for coordinating all technical and research activities of the IEEE with
`respect to Multiple-Valued Logic.
`• NCEES Electrical and Computer Engineering PE examination preparation committee for the
`National Council of Examiners for Engineering and Surveying, Full Committee Chair, (2008-
`2011), Vice-chair and Computer subcommittee Chair (2002-2008), Member (1997-2002 and
`2012-present). (Problem writing/reviewing and examination assembly for the national electrical
`and computer engineering PE test)
`IEEE-USA Licensure and Registration Committee, Vice-Chair (2011-present), Chair (appointed
`by IEEE-USA President), (2009-2010), Member (2003-2008), Responsible for advising IEEE-
`USA Board of Directors on issues regarding licensure and registration of professional engineers.
`IEEE Computer Society Technical Activities Board (TAB), Member (elected position within
`IEEE) (2010-2011), the TAB is a body composed of all IEEE CS technical committee chairs.
`IEEE Computer Society Educational Activities Board, Task Force on Computer Engineering
`Curriculum, Member (appointed by IEEE-CS Vice-President) (2010-2015), Responsible for
`reviewing and updating the joint IEEE/ACM CE2004 document that contains model curriculum
`
`•
`
`•
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`•
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`•
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`Page 9 of 33
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`

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`for all undergraduate computer engineering programs in the US. This document is used by
`universities and the ABET accrediting agency.
`• AAES/NCEES Professional Licensure Group, IEEE-USA Liaison, (appointed by NCEES
`President) (2010-present), liaison to the President of IEEE-USA for the professional licensure
`group jointly coordinated by the American Association of Engineering Societies (AAES) and the
`National Council of Examiners for Engineering and Surveying. This group is advisory to the
`National Academy of Engineering.
`• Book Reviewer: Kluwer Academic, McGraw-Hill, and DaVinci Book Publishers
`• Government Research Proposal Reviewer: NSF, NASA, NSERC (Canada), and BSF (Israel)
`• Paper Reviewer for various IEEE, ACM, and IEE Journals and Conference Proceedings
`
` Professional Society Memberships:
`o
`IEEE, senior member, (Institute of Electrical and Electronics Engineers), Technical
`Committee on Multiple-Valued Logic, Computer Society, Circuits and Systems Society,
`Reliability Society, Computational Intelligence Society
`o ACM, senior member, (Association of Computing Machinery), Special Interest Group on
`Design Automation
`o ASEE, (American Society of Engineering Educators)
`o NSPE, (National Society of Professional Engineers)
`o TSPE, (Texas Society of Professional Engineers)
`• External Faculty Tenure/Promotion-case Reviewer for Several Universities, both US and foreign
`• External Ph.D. Examiner and Committee Member:
`o Luleå Institute of Technology, Luleå, Sweden, 1999
`o University of Victoria, Victoria, B.C., Canada, 2003
`o University of Victoria, Victoria, B.C., Canada, 2006
`o National Institute of Technology, Tiruchirappalli, India, 2007
`o University of Alberta, Edmonton, Canada, 2012
`o University of Texas at Austin, USA, 2014-2015
`• External M.S. Examiner and Committee Member, University of Tulsa, Tulsa, Oklahoma, 2006
`• Conference and Workshop Leadership Positions:
`o General Chair 2008 IEEE Symposium on Multiple Valued Logic, Dallas, Texas
`o General Co-Chair 2007 IEEE Dallas Workshop on Circuits and Systems
`o General Chair 2001 Workshop on Reed-Muller Circuit Design, Starkville, Mississippi
`o Program Committee Chair, 2015 Workshop on Reed-Muller Circuit Design, Waterloo,
`Canada
`o Program Committee 2014, 2013 IEEE International Systems Conference
`o Program Committee 2013 IEEE Symposium Series on Quantum Computing and
`Computational Intelligence
`o Program Committee Member 2012 Special Session on Quantum Computing and
`Evolutionary Computation, IEEE Congress on Evolutionary Computation
`o Program Committee Member 2008 IEEE Dallas Workshop on Circuits and Systems
`o Program Committee Member 2016, 2015, 2014, 2013, 2012, 2011, 2010, 2007, 2006
`IEEE Symposium on Multiple Valued Logic
`o Program Committee Member 2006 IEEE Dallas Workshop on Circuits and Systems
`o Program Committee Member 2006, 2007, 2008 IEEE Annual Symposium on VLSI
`o Program Committee Member 2006 Workshop on Future Computing Technologies
`o Member, 2006 WSEAS Working Group on Computers
`o Program Committee Member 2002 IEEE Midwest Symposium Circuits & Systems
`o Program Committee Member 1999, 2003, 2005, 2009, 2011, 2013 Reed-Muller
`Workshop
`o Publicity Chair 1999 Int. Workshop Parallel and Dist. RT Systems, IPPS-SPDP-
`WPDRTS'99
`o Program Committee Member 1998 IPPS-SPDP-WPDRTS'98
`o Session Chair, numerous different conferences and workshops
`o
`
`
` •
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`Page 10 of 33
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`• University Service:
`o
`(SMU) Chair, Lyle School Promotion and Tenure Committee, (2015-2016)
`o
`(SMU) Member, CSE Departmental Faculty Search Committee (2015-2016)
`o
`(SMU) Member, OE2C IT Initiative Academic Sub-Team (2015)
`o
`(SMU) Member, SMU Center for Scientific Computation (CSC) Governance Committee
`(2013-present)
`o
`(SMU) Chair, Lyle School Academic Computing Committee, (2013)
`o
`(SMU) Member, Intellectual Property Committee, (2013-2014)
`o
`(SMU) Member, President’s Scholar Reading Team, (2013)
`o
`(SMU) Member, Hunt Scholar Interviewing Team, (2013)
`o
`(SMU) Participant, Provost’s Emerging Leaders Seminar Series, (2013)
`o
`(SMU) Board Member, High Performance Computing Research Initiative, (2013)
`o
`(SMU) Senator, Lyle Engineering School position, (2009-2012)
`o
`(SMU) Senate Academic Policy Committee (2009-2012, Chair: 2011-2012)
`o
`(SMU) Chair, Provost’s Information Technology Advisory Council (2011-2012, and
`former Research Group Chair, 2009-2011)
`o
`(SMU) Provost’s Quality Enhancement Plan Selection Committee (2009)
`o
`(SMU) Provost’s Committee on Tenure and Promotion, (2008-2011)
`o
`(SMU) Member, Lyle School Promotion and Tenure Committee, (2012, 2013)
`o
`(SMU) Member, CSE Departmental Faculty Search Committee (2011-2012)
`o
`(SMU) Chair, CSE Departmental Faculty Search Committee (2010-2011)
`o
`(SMU) Chair, CSE Department Faculty Search Committee (2009-2010)
`o
`(SMU) Coordinator, ABET Computer Engineering B.S. Program Reaccreditation, 2008
`o
`(SMU) Senator, at-large position, (2004-2007)
`o
`(SMU) Member, University Intellectual Property and Patents Committee (2004-2008)
`o
`(SMU) Member, All-University Finance Committee (2005-2008)
`o
`(SMU) Chair, School of Engineering Academic Affairs Committee (2007-2008)
`o
`(SMU) Member, School of Engineering Academic Affairs Committee (2003-2007)
`o
`(SMU) Member, CSE Department Research Committee (2006-2008)
`o
`(SMU) Member, CSE Department Undergraduate Program Committee (2007-2008)
`o
`(SMU) Chair, CSE Department Undergraduate Program Committee (2005-2007)
`o
`(SMU) Chair, CSE Department Faculty Affairs Committee (2004-2005)
`o
`(SMU) Chair, CSE Faculty Search Committee (2004-2005)
`o
`(SMU) Member, CSE Faculty Search Committee (2005-2006)
`o
`(SMU) Member, CSE Department Graduate Program Committee (2002-2005)
`o
`(SMU) Member, EE Faculty Search Committee (2008-2009)
`o
`(SMU) Member, CSE Industrial Advisory Board (IAB) Committee on Curriculum and
`Technology (2005-Present)
`o
`(SMU) Founding Faculty Advisor, CSE Upsilon Pi Epsilon honor society (2004-2009)
`o Participation in 4 different ABET accreditation visits under the new criteria
`o Active involvement in Senior Design Classes
`o Numerous other University committee assignments in past at SMU, Mississippi State
`University, and the University of Arkansas
`
`JOURNAL ARTICLES
`• A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System, IEEE
`Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, iss. 1, 2016,
`IEEEXplore pre-publication, iss. 99, February 2016, (with S.D. Gupta).
`• QMDDs: Efficient Quantum Function Representation and Manipulation, IEEE Trans. CAD, vol.
`35, no. 1, pp. 86-99, January 2016, (with P. Niemann, R. Wille, D.M. Miller, and R. Drechsler).
`
`
`PERSONAL INFORMATION
`Born in Chandler, Oklahoma in 1963. Married to Misty Thornton with sons Micah and Henry.
`Attended High School in the Tulsa, Oklahoma area (Glenpool) from 1972-1985. Dallas, Texas
`resident for 24 years.
`
`
`PUBLICATIONS AND MEDIA
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`Page 11 of 33
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`
`• Simulation and Implication using a Transfer Function Model for Switching Logic, IEEE Trans. on
`Computers, vol. 64, no. 12, pp. 3580-3590, December 2015.
`• Quantum Multiple-valued Decision Diagrams: The Case of Skipped Variables, Journal of
`Multiple-Valued Logic and Soft Computing, vol. 24, no. 1-4, 2015, pp. 93-108, (with D.Y.
`Feinstein).
`• Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision
`Diagrams, Journal of Multiple-Valued Logic and Soft Computing, vol. 24, no. 1-4, 2015, pp. 135-
`149, (with T.W. Manikas and D.Y. Feinstein).
`• On Optimization of Edge-Valued MDDs for Fast Analysis of Multi-State Systems, IEICE Trans.
`on Information and Systems, vol. E97-D, no. 9, September, 2014, pp. 2234-2242, (with S.
`Nagayama, T. Sasao, J.T. Butler, and T.W. Manikas).
`• Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach, Journal of
`Multiple-Valued Logic and Soft Computing, vol. 22, no. 1-2, 2014, pp. 21-39, (with R.P. Menon).
`• A Principles and Practices Exam Specification to Support Software Engineering Licensure in the
`United States of America, Software Quality Professional, December 2012, vol. 15, iss. 1, pp. 4-15,
`(with P.A. Laplante and B. Kalinowski).
`• Professional Licensure for Software Engineers: An Update, IEEE Computing in Science and
`Engineering, IEEE Computer Society Press and American Institute of Physics, September-
`October 2012, vol. 14, iss. 5, pp. 325-339.
`• Reversible Logic Synthesis Based on Decision Diagram Variable Ordering, Journal of Multiple-
`Valued Logic and Soft Computing, vol. 19, no. 4, 2012, pp. 325-339, (with D.Y. Feinstein).
`• Business Process Development through the use of a Modified Axiomatic Design Methodology,
`Journal of International Business Management & Research, vol. 2, issue 4, May 2011, (with D.M.
`Easton).
`• An Axiomatic Approach for Large-scale Disaster-Tolerant Systems Modeling, IIIS Journal of
`Systematics, Cybernetics and Informatics, vol. 19, no. 1, 2011, pp. 89-93, (with T. W. Manikas,
`L.L. Spenner, P.D. Krier, S. Nair, and S.A. Szygenda).
`• To PE or not to PE…The Sequel, IEEE Computing in Science and Engineering, IEEE Computer
`Society Press and American Institute of Physics, July/August 2010, vol. 12, no. 4, pp. 62-65, (with
`Steven F. Barrett).
`• Minimization of Quantum Multiple-valued Decision Diagrams using Data Structure Metrics,
`Journal of Multiple-Valued Logic and Soft Computing, vol. 15, no. 4, pp. 361-377, 2009, (with
`D.Y. Feinstein and D.M. Miller).
`• A Redundant Signed Binary Addition Based Digital-to-Frequency Converter, IEE Electronics
`Letters, vol. 45, no. 2, pp. 824-826, July 2009, (with W. Chen and P. Gui).
`• A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup
`Structures, IEEE Transactions on Computers, vol. 58, no. 2, Feb. 2009, pp. 163-174, (with A. Fit-
`Florea, L. Li, and D.W. Matula).
`• A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design, IIIS Journal
`of Systemics, Cybernetics and Informatics, vol. 6, no. 4, 2008, (with D. Easton, V.S.S. Nair, and
`S.A. Szygenda).
`• Components of Disaster Tolerant Computing: Analysis of Disaster Recovery, IT Application
`Downtime & Executive Visibility, International Journal of Business Information Systems, Issue 2,
`Volume 3, 2008, (to appear, with C.M. Lawler, M.A. Harper, and S.A. Szygenda).
`• QMDD Minimization through Variable Reordering and Sifting, Journal of Multiple-Valued Logic
`and Soft Computing, vol. 13, no. 4-6, 2007, pp. 537-552, (with D.M. Miller and D.Y. Feinstein).
`Integrated Design Validation: Combining Simulation and Formal Verification for Integrated
`Circuit Design Validation, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 4, no. 2,
`2006, (with L. Li and S. Szygenda).
`• A Coarse-grain Phased Logic CPU, IEEE Transactions on Computers, vol. 54, no. 7, July 2005,
`pp. 788-799, (with R. Reese and C. Traver).
`• Early Evaluation for Performance Enhancement in Phased Logic, IEEE Transactions on Computer
`Aided Design, vol. 24, no. 4, April 2005, pp. 532-550, (with R.B. Reese, C. Traver, and D.
`Hemmendinger).
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`•
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`Page 12 of 33
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`• Addition-Based Exponentiation Modulo 2k, IEE Electronics Letters, vol. 41, no. 2, January 2005,
`pp. 56-57, (with A. Fit-Florea and D.W. Matula).
`• Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k, IEE Electronics Letters, vol.
`41, no. 2, January 2005, pp. 57-59, (with A. Fit-Florea and D. W. Matula).
`• Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs, Journal of
`Multiple Valued Logic and Soft Computing, vol. 2, no. 2, 2004, pp. 189-202, (with D. M. Miller).
`• Mixed-radix MVL Function Spectral and Decision Diagram Representation, Automation and
`Remote Control, vol. 65, issue 6, June 2004, pp. 1007-1017, (invited paper).
`• A Two-phase Micropipeline Control Wrapper with Early Evaluation, IEE Electronics Letters, vol.
`40, issue 6, March 2004, pp. 365-266, (with R.B. Reese and C. Traver).
`• A Fast Two-phase Micropipeline Control Wrapper for Standard Cell Implementation, IEE
`Electronics Letters, vol. 40, issue 4, February 2004, pp. 19-20, (with R.B. Reese and C. Traver).
`• Performance Evaluation of a Parallel Decoupled Data Driven Multiprocessor, Parallel Processing
`Letters, vol. 13, no. 3, September 2003, pp. 497-507.
`• A Signed Binary Addition Circuit Based on an Alternative Class of Addition Tables, Computers &
`Electrical Engineering, vol. 29, no. 2, March 2003, pp. 303-315.
`• Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation,
`Canadian Journal of Electrical and Computer Engineering, vol. 27, no. 4, October 2002, pp. 159-
`164, (invited paper, with M. Kerttu, P. Lindgren and R. Drechsler).
`• Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs, VLSI
`Design, vol. 14, no. 1, February 2002, pp. 53-64, (with R. Drechsler and W. Günther).
`• Boolean Function Representation and Spectral Characterization Using AND/OR Graphs,
`Integration-the VLSI Journal, vol. 29, September 2000, pp. 101-116, (with A. Žužek and R.
`Drechsler).
`• Behavioral Synthesis of Combinational Logic Using Spectral Based Heuristics, ACM Transactions
`on Design Automation of Electronic Systems, vol. 4, no. 2, April 1999, pp. 219-230, (with V. S. S.
`Nair).
`• Resource Estimation for Parallel Architectures with Distributed Processor/Memory Nodes,
`Journal of Computing and Information Technology, vol. 6, no. 4, December 1998, pp. 359-371
`(with D. L. Andrews).
`• Signed Binary Addition Circuitry with Inherent Even Parity Outputs, IEEE Transactions on
`Computers, vol. 46, no. 7, July 1997, pp. 811-816.
`• BDD Based Spectral Approach for Reed-Muller Circuit Realisation, IEE Proceedings-Computers
`and Digital Techniques, vol. 193, issue 2, March 1996, pp. 145-150, (with V. S. S. Nair).
`• Efficient Calculation of Spectral Coefficients and their Application, IEEE Transactions on
`Computer Aided Design, vol. 14, no. 11, November 1995, pp. 1328-1341, (with V. S. S. Nair).
`• Efficient Calculation of Spectral Coefficients of Combinational Circuits, Digital Signal
`Processing: A Review Journal, October 1994, pp. 245-254, (with V. S. S. Nair).
`
`PATENTS
`• Single Clock Distribution Network for Multi-Phase Integrated Circuits, U.S. Patent No. 8,847,625,
`Serial No. 13/769,313, September 30, 2014, Application No. 13/769,313, Filed 16 February 2013,
`Claiming Priority from U.S. Provisional Patent, Serial Number 61/599,598, Filed 16 February,
`2012, (Co-inventor with R. Menon).
`• Design of Lookup Table Structures for Integer Valued Functions, U.S. Patent No. 7,962,537 B2,
`June 14, 2011, Filed June 26, 2007, (Co-inventor with D.W. Matula, A. Fit-Florea, and L. Li).
`• Method for Early Evaluation in Micropipeline Processors, U.S. Patent No. 7,043,710 B2,
`Published May 9, 2006, Filed Feb 10, 2004, Claiming Priority from U.S. Provisional Pub. No. US
`2004/0225699 A1 filed Nov. 11, 2004, (Co-inventor with R. B. Reese).
`• Method for Authentication Using a Pattern Recognition Keyboard, Notice of Allowance received
`March 23, 2016, Application No. 13/279,279, Serial No. US 2012/0098750 A1, Filed October 22,
`2011, Claiming Priority from U.S. Provisional Patent, Application No. 61/405988, Filed October
`22, 2010, (Co-inventor with J.D. Allen and J.J. Howard).
`
`
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`Page 13 of 33
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`
`• Squaring Circuit, Patent Pending, Application No. 13/601,709, Filed August 31, 2012, (Co-
`inventor with S. Gupta).
`
`•
`
`
`BOOK CONTRIBUTIONS
`• Boolean Function Spectra and Circuit Probabilities, Section 4.1, Chapter 4 in Problems and New
`Solutions in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, 2015, Bernd
`Steinbach, editor, (to appear, with Micah A. Thornton).
`• A Vector Space Method for Boolean Networks, Section 1.1, Chapter 1 in Problems and New
`Solutions in the Boolean Domain, Cambridge Scholars Publishing, Cambridge, UK, 2015, Bernd
`Steinbach, editor, (to appear).
`• The Best of IEEE-USA Insight: On Licensing Software Engineers, several reprinted articles by
`M.A. Thornton included, compiled by P. A. Laplante, IEEE-USA Publishing, 2015.
`• Modeling Digital Switching Circuits with Linear Algebra, Morgan & Claypool Publishers, San
`Rafael, California, April 2014, ISBN 9781627052337 (hardcopy), ISBN 9781627052344 (eBook).
`• Quantum Computing Approach for Alignment-free Sequence Search and Classification, Book
`Chapter, Multidisciplinary Computational Intelligence Techniques: Applications in Business,
`Engineering, and Medicine, S. Ali, N. Abbadeni, and M. Batouche, Editors, IGI-Global Press,
`pp. 279-300, May 2012, ISBN 978-1-4666-1830-5 (hardcopy), ISBN 978-1-4666-1831-2 (eBook),
`(with R.M. Kotamarti and M.H. Dunham).
`• Licensing Professional Software Engineers in the United States of America, Article in the
`Encyclopedia of Software Engineering, Taylor & Francis, New York, DOI: 10.1081/E-ESE,
`ISBN 1-4200-5977-7, eISBN 1-4200-5978-5, Published online: April 24, 2012, pp. 1-8, (with P.A.
`Laplante).
`• Keystroke Dynamics, Article in the Encyclopedia of Cryptography and Security, 2nd Edition,
`H.C.A. van Tilborg and S. Jajodia, Editors, Springer Publishers, pp. 688-691,