LIQUID CRYSTAL
`FLAT PANEL
`DISPLAYS
`
`
`
`MANUFACTURING
`SCIENCE &
`
`TECHNOLOGY
`
`C.;.v,W~mm«,w.,.mw.EmW¢.MV..W_,,«.,,..,MC_.._.._,..mw._,M__,.,__,,_M-,___,,,,N
`
`WILLIAM C. O’MARA
`
`VAN NOSTRAND REINHOLD
`'
`‘
`A
`'
`New York
`
`Samsung v. Gold Charm
`|PR20‘|5-01417
`
`
`1
`
`Gold Charm Ex. 2026
`
`Gold Charm Ex. 2026
`Samsung v. Gold Charm
`IPR2015-01417
`
`1
`
`

`
`Copyright © 1993 by Van Nostrand Reinhold
`
`Library of Congress Catalog Card -N rtib.er'92+13lA1;9i ‘
`ISBN0442-01428-7
`~
`‘ -22‘
`
`All rights reserved. No part of‘ this work covered by the copyright
`hereon may be reproduced or used in any form or by any means-—'- .
`graphic, electronic, or mechanical, including photocopyingrrecord-l
`ing, taping, or information s_torage_aI'1d retrieval systentsewifliout '
`the written permission of thepjublisher.
`-
`‘
`~'
`
`A
`
`@P Van Nostrand Reinhold
`
`Thomson Publishing. I'l',l?.';logo. is a trademark under~lic.e;nse.
`
`a diviisioniofInternational it
`
`I
`
`
`
`Printed in the United States of Aiimgica
`
`Van Nostrand Reinhold
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`
`lg:
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`International Thomson Publishing
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`
`16151413121110987654321
`
`Library of Congress Cataloging in Publication Data
`O'Mara, William C.
`Liquid crystal flat panel displays: manufacturing sciece &
`technology I William C. O'Mara.
`p.
`cm.
`Includes index
`ISBN 0-442~01428-7
`
`1. Liquid crystal display. I. Title
`TK7872.L56046 1993
`621 .38——dc20
`
`9243119
`CIP
`
`V
`
`
`
`2
`
`

`
`CHAPTER ONE: PRODAIICT APPl|._C.AATI0NS-
`
`LIQUID CRYSTAL FLAT PANEL DISPLAYS
`
`Table 1-7 Processing and Relative Cost ofActive and Passi1A2eADisplays
`
`
`‘Atelatiye
`Thin: Film ARA'AelAatAiVe
`AMaskiAngn
`A
`lA)Aisplay’ Type
`
`
`A AS ‘ Operations. Depositions " Array Cost Total (Zest
`
`
`
`7-8
`
`3-4
`
`
`
`8-9
`
`"
`
`100 '_
`A
`50
`
`T
`
`‘
`
`‘
`
`A
`
`AA100
`A
`75
`
`A
`
`v
`
`'
`
`
`
`
`
`Thinfilm
`A
`transistor A
`3-4)
`Thin film diode
`.
`‘
`(MIM, PIN)
`
`
`A 1_ ‘ -STN 15
`
`1.6.2 AMORPHOUS SILICON TRANSISTORS
`Two types of TFT structures are usedfor amorphous silicon (a-Si) devices. One
`is the inverted stagg‘ered (IS) type,Awhich can’ be either back channel etched
`(IS—BCE) or tri-layered (IS—TL). The other is called a normal staggered (NS)
`device. These three transistors (IS—BCE, IS—TL, and NS) are shown in cross—section
`in Figure 1-15. They ‘are currently being used for LCD TVs or other products in
`Japan as shownin Table 1-8.
`.
`V -
`-
`
`Table. 1-8 TFTArray Process and Specifications
`
`
`
`
`
`
`
`
`
`_v H6S-hiA- A‘
`den
`
`shita
`
`. M
`
`anufacturer
`
`Toshiba
`
`Tflitachil
`
`' Sharp -
`
`I
`
`‘
`
`S
`
`AAA3—inchA ‘ A10-inch
`3-inch
`A5—inchA
`4A—Ainch‘
`Screensize ‘
`IS—TL AA NS A
`1
`IS—TL
`IS-BACEA
`IS—BCE
`A
`type A
`9"
`I
`8
`" 8,
`9
`A
`6s
`A
`Numberofmasks
`500A"
`300A
`200’0AAA
`500A
`3000A H
`aA—S'i thickness
`A
`STAN)
`SA'iNA
`SiN
`I
`SIN/Tao A
`SAiAN/SiO
`Gateinsulator
`A1/Cr
`Ta A
`A
`A MAoSAiA/Cr
`AIAAA A
`AIMAo-Ta
`Gateline
`Al
`ITO/Ti A
`‘A A1
`A
`A
`ITO/Cr
`A1/Mo
`Signal line
`
`
`
`
`AA Yes A Yes Yes) A,») Yes“ Storage'Acapacitor A Yes A
`
`
`
`
`The peI“foiA’manceAof 21 TFT as well as the manufacturing yield and throughput
`depend on the transistor’s construction. The inverted staggered back channel
`etched transistor, (IS—BCE); can be fabiicated with the minimum number of six
`masks, whereas the inveAI'tedAAstaggereAdA tn"-layered transistor, (IS-TL)AArAequires
`nine; On the other hand, the IS-TL type has only a 5003 a~Si.A1ayAer, minimizing
`
`3
`
`

`
`
`
`
`
`CHAPTER ‘ONE: PRODUCT APPLICATIONS -
`LIQUID ‘CRYSTAL FLAT PANEL DISPLAYS
`
`SiNx/SiOx
`Mo-Ta(Gate)
`,_ g_
`(a) Inverted Staggered (Back Channel-Etched)
`
`_
`
`. SiNx
`Ta_,_O_5
`Ta(Gate)
`(b) Inverted Staggered (Trl-Layered)
`
`
`
` A
`
`..;SiOx ‘
`
`(c) Normal Staggered
`Figure 1-15: Cr0ss~sectio_n view of three» FT c0nfigurations[I5]
`
`thedeposition time for this layer. This is important because amorphous silicon
`depositiongis very slow, and can constitute a manufacturing bottleneck when thick
`layers are required.
`’
`" l
`l
`V
`
`Double layer gate insulator structures such‘ as SiNx/SiOxior SiN.x/TaOx are com?
`monly used to minimize yield loss due to line or point defects which cause
`crossover shorts. These kinds of shorts are difficult or impossible to repair; 1
`«
`
`‘Specific resistivities of tantalum‘. (Ta); ehromium ‘(crjpr molybdenum—tantalurn
`alloy (Mo-Ta) films used for gate linesand gate “electrodes in some of these
`structures ranges from 20 to 40 Q—cm. These values are too high forlargescreen
`TF1"-L”CDs, since the high resistance and capacitance ofthe gate line leads to gate
`pulse delay. For ail2 inch TFT—LCD with 1:O24x768; pixels and a‘ 16 level grey
`sca1e,,the resistivity of the gate line should be less than
`tt §2—cm. Aluminum is
`the only app1'opriate material for such high density displays.
`if
`if
`A
`A
`
`One of the difficulties in transistor design and manufacturing‘ is the need for a
`storage capacitor to improve theimage quality. The storage capacitor adjoins the
`TFT and has an ITO top plate. Charging this capacitor requires that the TFT be
`relatively large, and the increased area at each pixel: devoted to thetransistor
`reduces theamount of lightwhich can be transrnitted (aperture ratio). If a second -
`transistor is added at each pixel for 1‘edundancy, transmitted light can drop‘ to less
`than 5% in a finished display.
`'
`'
`‘N l
`'
`A
`‘
`i
`l
`
`/32
`
`4
`
`

`
`
`
`
`
`CIIAPTERIONE: PRODUCT APPLICATIONS
`LIQUID CRYSTAL FLAT PANEL DISPLAYS
`
`desirable. Amore complex two gate transistor structurecan reduce the leakage
`considerably.
`’
`it
`’
`i
`*
`T
`r
`‘
`
`These devices are compared in Table 1412.
`
`e
`
`A
`
`V Table 1-12‘ Comparisonof TFT,.PIN Diode, andJMIM Di0deDisplays
`
`
`
` Property a-Si TFT a-Si PIN Ta2O5 MIM SiNx MIM g
`
`On/Off current ratio
`
`‘
`
`-T109107»
`
`103 *
`
`‘l03—=lO“
`
`-
`
`‘l«04‘--105‘
`
`Number of masks
`(active substrate)
`
`-
`
`A
`
`6—8
`L,
`
`V
`
`Number of film depositions
`(active substrate)
`
`Number of leads required
`for M x N matrix
`
`‘ino crossovers.
`
`r
`
`V
`
`6-7
`-
`
`-
`
`7~8i
`
`t
`
`3
`
`3 .
`
`'
`
`~
`
`~ 6-8
`
`—
`
`M+N
`
`2M+N
`
`_ M+N*
`
`.
`
`2-3 .
`"
`
`'
`
`3‘-
`1 -
`
`M+N*
`7 r
`-
`
`*
`
`Poly-Si TFT
`0 Advantages: higher mobility, transistorperformance. CMOS circuit capability -
`for on—b0ard drivers.
`
`0 Disadvantages: higher process temperature, ion implantation requirement. '
`
`"
`
`Table 1-13 compares the CMOS poly—Si TFT with a—Si:H TFT. There are two‘
`types of poly—Si processes; HT CMOS describestheprocess forhigh temperature
`
`CVD of polysilicon, while LT CMOS employs a 600°C maximum deposition
`
`temperature.
`
`—
`
`3
`
`~.
`
`;‘
`
`::
`
`A
`
`.~ g
`
`-r
`
`The advantage of developing a CMOS poly Si process is the fact that on—board
`drivers can be fabricated, cutting down on the number of interconnects to the
`
`outside world. However, the LT CMOS process shown above, while it produces
`transistors with much higher mobility than a-Si devices, cannot operate at a speed
`high enough for on-board shift registers for high information content displays, at
`least not yet.
`‘
`“
`‘
`‘
`r
`T
`-
`-A
`
`The relative cost of the three processes, tamorphoussilicon, high temperature
`polysilicon, and low temperaturepolysilicon, is shown as a function of display
`
`40
`
`5
`
`

`
`
`
`
`
`Threshold Voltage
`(Volts,"n—channel)‘
`
`‘
`
`‘
`
`‘
`
`21.0.4:
`“
`
`‘
`
`2.0
`
`'
`
`T 15* A‘
`“
`
`V0.75‘
`100 ‘
`Mobility
`A
`.
`AA
`V
`-
`.
`(cm2/V- s, n-channel),A
`Shift register
`15V; L=l0ttm
`ZOMHAZ
`O.lMHz
`SMHZ
`
`
`40
`
`A
`
`A
`
`*=NMOS~ ‘“=-3_l'ight.shie1d
`
`size in Figure 1-20. The cost is estimated in arbitrary AuAnits.’For smallAdispAlays,
`high temperature polysilicon is low -in cost, even when the cost of a quartz
`substrateis included. This indicates that small displays such as video cAamAeras and
`projection TVs will be built with this technology, to display sizes of 2'-3‘~’inch
`diagonal. Amorphous silicon. is much lower in c‘o‘st‘for‘large displays. The future
`A oflow temperature polysilicon lies in this large display area. As mentioned above,
`low cost relative to amorphous silicon requires a very high yield process,
`integraAtionAofdriver circuits onto the glass substrate.,NAevv manufacturing procAesses.
`and equipment for CVD, implantation, and recrystallization will be required.
`
`A brief discussion of some of the circuit types is shown in Table 1-1 Thebasic
`typesof integrated circuits that can be considered for driving the active matrix r
`devices include D/A converters, sampled ramp, and l-of—n selector for digital
`input, On the other hand, for viAdeo ,inpAut,A multiplexer, sample and hold, and
`double sample and hold are available. The tablqshows the comparison.
`
`
`
`CHAPTER.ONE: PRODUCT APPIICATIONS
`LIQUID CRYSTAL FLAT PANEL DISPLAYS
`
`Table 1-13 CMOS poly-ASi TFT and a~ASi:HA TAFTAComparis0I:z
`
`
`
`‘
`
`
`
`A ~
`‘
`
`_
`
`.
`
`TAFAT
`CMSA ,1A:r CMOSALAA
`
`NMOA;S.§2
`
`.
`
`
`
`
`fuAs;edAAAAuartz
`_
`hard lass
`hard
`AA
`.
`.
`,
`Substrate
`
`
`
`~l()0O‘?CA"*é _
`600°C‘
`A
`AA
`.. 300°C A
`Maximum process. temperature AA
`A
`Numberof masI<A.stAe ‘s
`.
`*
`A
`‘A
`‘A
`A
`A
`‘-:.:.fe5A‘°-7AA.A-2.:
`.
`A 5-6" A
`
`Dielectric depositions‘
`,
`A
`A 3
`.
`4' " “
`.
`2
`(LPCVD or PEACVD)
`‘
`
`/A
`
`A,
`
`‘ 5
`
`.
`
`.
`
`A
`
`‘
`
`_
`*
`‘ 3 v D
`3
`‘Yes
`
`A,
`
`‘A *
`
`3A
`2
`A
`‘ Yes
`
`A
`
`*
`A
`
`A
`
`*
`
`’
`
`3
`N/A
`‘ AN/AA
`
`AA
`
`
`
`(LPCVD or PECVD)A'A t
`Metal sputtering
`t
`Ion Implantation
`Hydrogenation
`
`A
`A
`
`AA
`
`6
`
`

`
`cnnpfm mo: nI§mY“AmAiIurAc1unInG
`
`LIQUID CRYSTAL FLAT PANEL DISPLAYS
`
`tion for some —steps~,’as men-
`tioned previously for ITO
`
`etching.‘ Reactive etching
`many offer advantages of
`linewidth controland repro-
`ducible end point detection.
`However, for the time being,
`throughput ""¢011Sid€‘rati0nS
`ensure thatmost etching steps
`
`will be performed in wet sys—
`tems.
`‘
`A‘
`
`.
`
`1
`
` processing is ‘under‘e3v‘a1u'a-
`
`Transistor Processes
`
`.
`
`Two types of TFT structures
`are used for amorphous sili-
`con (a—Si) devices. one is the
`inverted staggered. (IS) type;
`which can be either back
`channel etche_d-(IAS—:BC.E) or
`tri-layered(IS-TL).The other
`is called a normal staggered
`(NS)*device. These, three.‘
`transistors‘ ‘(IS-‘BCE, IS—TL,
`and NS) are shown in.cro‘ss—
`
`sectionin Figure 2-11.‘ A
`
`Figure 2-’1A1j€ross-section
`view of three TFT configu-
`mt..l.0nS[13]..
`_\
`.
`
`Al
`
`F,
`
`‘ Mo
`A
`
`efNx 7 a-Si(n+)
`A
`‘
`V
`‘
`
`‘
`
`‘
`
`a-iSi(i)
`'
`
`'
`
`SiNx/SiOx
`'
`
`A
`
`
`
`‘
`
`.
`
`_
`
`'
`
`-
`
`'
`»»»»»»»»»»»»» ~
`
`To
`5
`.
`
`«
`
`c
`
`MoTa(Gate)‘”A
`I
`taitunvenea staggered (sackgeeanrne.-eiei.ea;
`
`V
`
`4 "
`
`‘
`
`"a-Si(n+)i
`
`
`
`.
`.. g.$.iNX‘j.
`T3205
`T§(G.a‘el
`—
`(b) Inverted Staggered (Tri-Layered)
`<
`AA
`A
`'
`A
`A
`A
`A
`
`A
`
`‘
`
`A
`
`.
`
`.
`
`' Amate)
`
`
`
`‘
`
`A (c) Normal Staggered
`
`A
`
`‘79
`
`7
`
`

`
`
`
`CHAPTERHN03. .P.|5.H-.AY MhN"fl¢TuR.l“5
`
`LIQUID“ CRYSTAL FLAT PANEL DISPLAYS
`
`The process flowfor each of these transistors is shown here, with indications of
`photolithography and other processing operations. The first flow chart, shown in
`Table 2-8, is for the inverted—staggered- backchanneli etched (IS:-BCE)‘ device.
`
`g
`‘
`A
`Table 258 APraAcess::AFloW
`Inverted-Staggered Back Channel Etched TFT
`
`
`Gate definition
`2
`A
`.
`
`.A
`-A
`-
`~
`.
`Sputter
`Mo-Ta
`Photolithography, etching
`E
`1st masking step.
`p
`«
`A
`a-Si island definition
`V
`Plasma CVD’
`Si‘()/SiN//a-Sji,'(‘i)/«fi‘+ESi(jn'+) ;
`:Photolithography,etching.
`< 2nd n1‘asking3AsA”t”ep~. 5
`;
`\‘
`g
`5 it
`t
`V‘
`T
`‘
`.
`A
`.Disp1ay....e1e‘ctrode formation
`.. wisputter
`.
`A 31%-ITO deposition.
`.
`,
`Photolithography, etching N
`..,f,.,..,..;.,..3rdmaskingustep - - F
`
`Thiru-hole formation
`V
`A
`.
`.
`.
`t
`.
`I
`T
`‘
`A
`4th masking step
`- Photolithography, etching:
`Source,/Drain/Signal Line definitio
`.
`s
`[ Mo—A1 deposition
`A
`‘ 5th masking step
`_
`—BaC_k. Channel definition _
`‘
`1
`I1’f 21.-Si etching A
`‘
`Passivation-.
`- ~
`
`
`'
`
`L
`
`A
`
`‘
`
`.
`
`'
`
`‘
`T‘
`
`.
`
`..
`
`_
`
`T
`
`L
`
`i
`
`T
`
`»
`
`‘
`
`5
`
`V
`
`’
`
`. . .-
`e
`.
`.
`..
`Sputter
`Photolithography,etching.-
`_
`.
`A
`'2 1 av;
`éif
`Wet, dry etching-.
`
`..
`
`.....P1§1.Sm§i CVD
`
`AAAAAolgithography, etching?
`
`‘
`”
`‘6‘th‘ffiEiSkifi‘g”‘StCp.
`rAr1~ayco:ap1¢tear‘r "
`
`V
`
`The process
`2-9.
`
`staggered trilayered (IS—TL) device is sho-wn Table A
`
`80
`
`
`
`8
`
`

`
`
`
`CHAPT_ERATW0,i{ DISPIAY ‘MANUFACTURING-
`LIQUID CRYSTAL, FLAT PANEL DISPLAYS: ‘
`
`Table 2-9 Inverted-Staggered Trilayered TFT Process
`
`Material/Feature
`
`‘
`
`Process
`
`Gate definition
`‘ Ta deposition
`1st mask step
`Gate oxide formation a
`
`M
`
`.
`
`a
`
`7
`Sputter
`t Photolithography, etching
`1
`~
`~;
`.
`
`‘
`
`L
`
`
`
`
`anodization withpmask”
`oxidation
`‘
`:
`a—Si TFT de ositiong
`
`SiN/a-Si(i)/SiN
`Plasma CVD
`deposition
`2nd mask step
`a—Si island definition
`
`
`
`
`
`
`
`
`Photolithography, etching it
`
`_
`
`L 3rd mask step
`
`Source/drain definition .
`a-Si(n*) deposition
`4th mask step
`
`.
`
`(sou1‘ce/drai-n)
`5thimask;:st‘ep-
`(thruhole)
`
`‘
`
`‘
`
`I
`'l“idepositi‘o‘n = -
`2 6th mask step (metal)
`
`Display electrode formation
`ITO deposition
`‘
`»7th mask step:
`Passivation
`SiN deposition
`8th'maskistepi
`Array Completed
`
`»
`
`A
`
`A
`
`.
`
`‘A
`
`t
`
`‘
`
`-3
`
`"
`
`A‘
`
`‘
`
`‘
`
`i
`
`.
`
`V‘
`
`, Photolithography, etching
`
`.
`Plasma CVD A
`" Photolithography’, etching ‘
`
`.
`
`*
`l
`.
`? Photolithography,‘etchings
`‘
`‘
`‘
`
`'
`
`..
`‘
`
`1 3 Sputter
`Photolithography, etching‘ '
`
`.
`
`A
`
`‘
`
`V
`
`~
`
`‘
`
`-
`
`N
`A
`:fi~
`‘Z Sputter
`* Photolithography, etching -
`H
`-
`‘-
`)»
`- Plasma CVD
`1 Photolithography, etching
`‘
`
`’
`
`A
`
`A
`
`L
`
`-
`z
`
`‘
`
`‘
`
`g
`
`.
`
`M
`
`The process flow chart for the normalzstaggered (NS) device is shown in‘Tab1e 2-10 ‘.
`
`e
`
`p
`
`
`
`\
`
`
`
`
`
`
`
`
`9
`
`

`
`CHAPTER TWO: DISPLAY MANUFACTURING
`LIQUID CRYSTAI: FLAT PANELDISPLAYS
`
`Table 2-10 Process Flow for Normal Staggered TFT
`
`/
`
`T
`
`~
`
`‘
`
`Material/Feature
`
`Process
`
`
`Light shield and signal line
`formation
`
`Cr deposition
`1st mask step
`Insulator D_eposition
`SiOx deposition
`2nd mask step
`(thru hole)
`Display electrode, signal line P
`formation
`ITO deposition
`3rd mask step
`TFI‘ formation
`
`»
`
`a—Si (nt) deposition t
`Source/Drain formation
`
`~
`L
`Sputter
`Photolithography,» etchings.
`_
`Plasma CVD or Sputter
`c
`~
`A
`
`‘
`
`'
`
`A
`
`.
`
`.
`
`.
`
`7'
`*
`~
`Sputter
`Photolithography, etching
`A
`’
`A
`
`Plasma CVD
`
`Photolithography, etching
`Plasma CVD
`a
`= Photolithography, etching
`A
`7
`
`'
`
`*
`
`-
`"Plasma CVD
`Photolithography, etching *
`
`4th masking step.
`a-Si (i) deposition
`5th masking step
`(island)
`,
`Gate dielectric formation
`SiN deposition
`6th mask step
`Gate electrode definition
`Al deposition
`7th mask step:
`Passivation
`_SiN deposition
`8th mask step
`Array Completed
` g
`
`.
`_,
`Sputter T
`Photolithography, etching
`A
`-
`
`;
`
`Plasma CVD
`.i Photolithography; etching
`
`The transistors whose process sequence has been described above are currently
`being used for LCD TVs or other products in Japan as shown in Table 2-1 1.
`
`W82
`
`
`
`10
`
`

`
`cumin: 1jw‘o‘;t DISPLAY: .MA‘nurAcrumuo'
`“L1QUIi)”CRYsTAL FLAT PANEL DISPLAYS
`
`Table 2-11 TFT‘Airray Process’-and Specifications
`
`‘Manufacturer
`
`-Toshiba
`
`‘Hitachi Sharp ‘
`
`« oMaz~msiiita Hoshiden
`
`Screen size
`A
`A TFT type
`Number of masks
`a-Si thickness
`T
`
`‘
`
`4-inch
`IS,-BCE
`6 i
`T
`. 3000A.
`
`‘» 5-inch
`IS—BCE
`9
`A 2000A s
`
`3-inch
`IS—TL
`8i
`‘
`‘
`500A
`
`5‘-3-inch
`IS—TL
`3
`A‘ 9‘
`500A >
`
`‘
`
`10-inch
`NS’
`A18“ 5
`300A-
`
`Gate insulator
`
`SiN/SiO
`
`SiN
`
`SiN/TaO-- SiN
`
`A ‘SiN~ A
`
`Gate ‘line .
`
`‘
`
`Mo—Ta
`
`—‘Al/Cr‘
`
`Ta‘
`
`-
`
`.MoSi/Cr
`
`A1
`
`Signal line
`S’to1'a‘geA'caPacito1'
`
`All/Mo:
`3 Yes
`
`A1
`Yes‘ “
`
`TITO/Ti
`Yes i
`
`i
`
`‘
`’ Al
`‘Yes ‘
`
`‘ITO/Cr
`Yes
`
`«
`
`A
`
`-
`
`Someprevious ‘comments: about TFTirnanufacturi‘n‘g: are repeatedhere for
`reference. The performance of a‘”TFT as well ‘as the man‘ufacturin~g yield and
`
`throughput depend-onthe‘ transistor’s ‘construction. The inverted staggered ‘back
`‘ Tchannelietched‘transistor, (IS-BCE), can be fabricated with the minimum number
`
`of six masks, whereas the inverted staggered tn’-layered transistor, (IS-TL)
`requires nine. On the other hand, the IS—TL type has ‘only a 500A a-Si layer,
`minimizing the deposition? time for thislayer; This is important because amort-
`phoussiliicon /‘deposition is very slow, and ‘can’ constitute a ‘manufacturing
`bottleneck when thick layers are reqzuired.
`‘
`
`Double layer gate insulator structures such as SiNx/SiOX or SiNx/TaOx are com-
`monly used to minimize yield loss due to line or point defects which cause
`crossover shorts. These Kinds of shorts are difficult or. impossible to repair.
`-
`
`chromium (Cr), or molybdenum-tantalum
`Specificuresistiviities of tantalum
`alloy (Mo-Ta) filmsused for gate lines and gate electrodes in some of these
`structures ranges from 20 to 40 ll. §2—cm. These values are too high for large screen i
`TF1“-LCDs, since the high resistance and capacitance ofthe g‘ate‘l-inc-leadsi togatie
`p'11ls‘e:'delay.'Fo'r' at 12 inch -LCD‘ with‘l02?4x768‘piXels‘and‘a 16 level grey
`«scale, the re‘sisti‘Vity ofthe gate‘1iiie“should beliess than 10 LL Q-cm. Aluminum is
`the only appropriiatematerial for such:-hi‘gh‘ densityidiisplaiys-.‘
`g"
`i
`1
`‘
`'
`
`Oneiof the difficulties in transistor design and imatiufacturing is the need for a
`storagecapacitor to improve the image quality; The s‘tor'age‘capaciitor3 adjoins the
`
`
`
`11