`Valeo v. Magna
`IPR2015-____
`
`VALEO EX. 1009_001
`
`
`
`A video camera has been built using this chip
`along with a 6 MHz clock source, a 5 volt
`power supply, plus one bipolar transistor and a
`small
`number
`of
`resistors
`and
`capacitors
`required to match the line impedance to the
`monitor and decouple the power supply. The
`picture quality is
`subjectively excellent, and
`compares well with commercially available cam-
`eras.
`
`2.
`
`Image Sensor Block
`
`The architecture of the image sensor is shown in
`Figure 2. The light sensing area consists of a
`312X287 diode array matrix, schematically indi-
`cated by the columns and rows of individual
`photodiodes. The pixel size is 19.6um X16p.m ,
`giving a light sensing area of 6.12mm X4.59mm .
`This corresponds to the standard 1/2" format.
`
`gain
`setting
`supplies
`clock
`[I
`
`auto-exposure
`control
`logic
`
`video format
`
`timing & control
`circuits
`
`horizontal addressing
`
`
`
`
`
`1
`
`
`
`verticaladdressing
`
`
`
`' CVO ~- composite video output
`
`Figure 2. Architecture of the image sensor
`
`The photodiodes are accessed on the basis of
`sequential selection of each row through a verti-
`
`IOI
`
`cal shift register. At the top of each column is a
`sense amplifier. The sensed information is read
`out sequentially along the x-direction under con-
`trol of a horizontal shift register. At the end of
`the path there is an output amplifier [1,2].
`
`The sense amplifier is a single-ended differential
`charge integrator. Its performance demands an
`accurate capacitor,
`formed by metall/metalZ
`and metall/poly. However, commodity ASIC
`CMOS technology sometimes can not guarantee
`the resulting capacitance values. We designed a
`gain-controllable integrator, shown in Figure. 3,
`which allows wide range of programmable varia-
`tion of the capacitance value.
`
`
`
`Figure 3.
`
`Integrator with programmable gain
`and self compensation
`
`The main concern in the output stage design is
`the read—out speed required to achieve high
`resolution. A 6 MHz clock was chosen for this
`
`design; this gives a horizontal resolution of 312
`pixels. The resultant picture quality is assured
`by a two stage output buffer with sample and
`hold function.
`
`3. Automatic Exposure Control
`
`The device automatically controls its exposure
`over a range of 40,000:1. Control
`is achieved
`by varying the integration time prior to reading
`each row of pixels. The integration time can be
`as long as one field, or as short as three cycles
`of the pixel clock(about 500ns).
`
`VALEO EX. 1009_002
`VALEO EX. 1009_002
`
`
`
`The exposure is set by monitoring the video
`stream and estimating the fractions of each pic—
`ture which are very white and very black. On
`the basis of this information, the device decides
`whether the picture contrast is acceptable, or too
`white, or too dark. If necessary,
`the exposure
`time is then changed, in the appropriate direc-
`tion.
`
`4. Generation of the Video Format Signal
`
`Figure 4 shows a block diagram for the genera-
`tion of
`the video formatted signal. The 7
`corrected image data is multiplexed with the
`sync-level and blanking-level, controlled by tim-
`ing control signals, which are provided from the
`video
`timing
`block.
`A bipolar
`transistor
`(emitter follower) is needed to provide a low
`impedance output.
`
`in Figure 5.
`
`Vdd
`
`Corrected
`
`output
`
`Linear
`input
`
`I—l
`
`Figure 5. Gamma corrector
`
`SPICE simulation was carried out and a simula-
`tion result is shown in Figure 6. A theoretical
`curve of ideal y correction ( 7 =0.45) is also
`shown in Figure 6.
`
`Vdd
`
`Image signal
`
`
`Video
`output
`
`
`
`IQXQIdIIIHW
`Image
`
`
`SCI] SOl'
`
`
`
`
`
`Blanking Sync
`level
`level
`
`0.8
`
`0.2
`
`\
`
`Vx
`
`’
`.
`Simulation result
`
` ideal curve
`0.6 0.4
`
`
`0.2
`
`0.4
`
`0.6
`
`0.8
`
`1.
`
`
`Figure 4. Generation of the video output
`
`5; Simple Solution for 7 Correction
`
`to be 7
`image data needs
`analogue
`The
`corrected, to compensate for the nonlinearity of
`monitor tubes [3]. This is usually implemented
`using discrete components e.g. a ladder—network
`of diodes,
`resistors
`and reference voltages.
`Unfortunately,
`this is not suitable for integra-
`tion.
`In this design 7 correction is achieved by
`a simple solution which uses the nonlinear I
`-
`VGS characteristic of an MOS FET, as shown
`
`Figure 6. Gamma correction curves
`
`6. Simple Solution for Test
`
`Special consideration has been given to make it
`possible to carry out digital wafer test which is
`as complete as possible. The analogue parts are
`also tested by making them produce digital out-
`puts, so avoiding a requirement for full analo—
`gue test. The test
`includes bit—line tests and
`word-line tests. Only a 0.78% increase in chip
`area was required to implement
`the on chip
`
`l02
`
`VALEO EX. 1009_003
`VALEO EX. 1009_003
`
`
`
`
`
`
`
`I
`
`51dB
`
`52dB
`
`300:1
`
`
`
`narameter
`
`for camera
`
`for chi .
`
`for camera
`
`
`
`
`
`hardware necessary If)? this 'fbi'ifl 6f IESIifig (Fig-
`ure 2). The individual photo pixels may be
`tested if a sufficiently long vector set is allow-
`able.
`
`The chip can also self-generate a checkerboard
`pattern which may be displayed on a monitor
`screen, or captured by a frame grabber. This
`pattern can be used not only to find defective
`pixels, but also to check analogue performance
`parameters, such as read out speed and unifor-
`mity.
`
`7. Eliminating Noise
`
`Complete guard rings are put around all analo-
`gue parts to minimize interference from the digi-
`tal parts. Routing is arranged with priority to
`analogue output and analogue power supplies.
`Analogue power supplies and digital supplies are
`separated, and supplies to different analogue
`parts are divided where necessary.
`
`There are two sources of fixed pattern noise:
`threshold variation in the MOS pixel access
`transistors causing speckles, and mismatches
`between the column sense amplifiers causing
`vertical stripes. The solution to the pixel thres-
`hold variation is to reduce the pixel reset voltage
`below (Vdd-Vt)
`so that
`the reset voltage is
`insensitive to the variation of the threshold Vt.
`
`Column fixed pattern noise arises mostly from
`offset mismatches in the column sense amplif-
`iers. We have successfully eliminated this prob—
`lem by automatically compensating each amplif-
`ier to give zero offset during each line synchron-
`ization interval.
`
`8. Characterization
`
`An optical test measurement set-up was used to
`characterize the camera. The following table
`summarize the measured results of the perfor-
`mance characterization experiments. The param-
`eters of typical monochrome CCD cameras are
`also given for comparison.
`
`40,000: 1
`CXIusurmran‘_e
`
`
`
`saturation level
`
`antibloomin ; factor
`
`
`
`* as fraction of saturation at room temperature,
`20msec integration time
`
`9. Conclusions
`
`We have developed several design techniques to
`achieve a single chip camera,
`in unmodified
`CMOS
`technology.
`which
`matches
`the
`performance of CCD cameras. The design has
`proven that three technical barriers which most
`greatly influence new product development;
`cost, power
`consumption and size,
`are all
`dramatically reduced over
`today’s
`solid—state
`camera technologies.
`
`10. Acknowledgements
`
`received from the
`We acknowledge support
`Science
`and Engineering Research Council
`(Grant GR/F 36538 IED2/1/1159).
`
`11. References
`
`[1] D. Renshaw, ct. a1., "ASIC Vision", Proc.
`IEEE
`Custom
`Integrated
`Circuits
`Conference, 1990, pp 3038-3041.
`
`[2]
`
`et.
`
`"ASIC Image
`31.,
`D. Renshaw,
`International
`IEEE
`Sensors",
`Proc.
`Symposium on Circuits and Systems, 1990,
`pp 73.1-73.4.
`
`{-3}
`
`Eugene Trundle, Television and Video
`Engineers Pocket Book, Heinemann, 1987.
`
`l0]
`
`VALEO EX. 1009_004
`VALEO EX. 1009_004
`
`