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`publication entitled Euro ASIC’9l Proceedings, Euro ASIC Conference, Palais des Congres,
`Porte Maillot, Paris, France, May 27 — 31, 1991, call number TK 7874.6.E87a 1991, and
`that the following pages — cover page, first title page, second title page, copyright page iv, page
`entitled “Welcome to Euro ASIC ’91” page V, page entitled, “Coordination Committee” page vi,
`page entitled, “Table of Contents” pages vii - xii, and pages 100—103 on which contain the
`following article, “CMOS Video Cameras" by Wang, Renshaw, Denyer and Lu - are a true
`representation from that work.
`
`THIS IS TO CERTIFY FURTHER, that work is marked with a Library of Congress
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`dL1plicaI:ionserviccs@locguv
`
`1
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`

`
`2
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`

`
`EURO ASIC '91
`
`1951-1991
`40 YEARS OF SERVICE
`-1
`
`53* E3
`1555 compunzn socnnv
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`In;n.-.n.- e< Eiecmcal mu E-.aa:.s r—-yum .-.-
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`3
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`EURO ASIC '91
`C‘(f,“,:;,,,~r"
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`In
`
`Palais des Congrés, Porte Maillot, Paris, France
`
`May 27 — 31, 1991
`
`Organized by
`Le Club Conception de Circuits 31 la Demande
`Institut National Polyteclmique de Grenoble
`
`In cooperation with
`IEEE Design Automation Technical Committee
`Association for Computing Machinery/SIGDA
`
`1951-1991
`
`IEEE Computer Society Press
`
`Los Alamitos, California
`
`Washington
`
`a
`
`Brussels
`
`o
`
`Tokyo
`
`4
`
`

`
`, ii;
`
`l ‘i Ci
`
`l
`
`The papers in this book comprise the proceedings otthe meeting mentioned
`on the cover and title page. They reflect the authors‘ 0pIl"I|Ol'lS and. in the
`interests of timely dissemination. are pubtished as presented and without
`change. Their inclusion in this publication does not necessarily constitute
`endorsement by the editors, the iEEE Computer Society Press. or the
`Institute of Electrical and Electronics Engineers. inc.
`
`1951-1991
`‘*“*'“*“*"“‘*
`
`lflfilfllfllflifi
`.
`nu-
`
`@ 10662 Los Vaqueros Circle
`
`Published by the
`IEEE Computer Society Press
`
`PO Box 3014
`Los Alamitos, CA 90720-1264
`
`© 1991 by the institute of Electrical and Electronics Engineers, Inc. All rights reserved.
`
`Copyright and Fleprinl Permissions: Abstracting is permitted with credit to the source.
`Libraries are permitted to photocopy beyond the limits of US copyright law. tor private
`use of patrons, those articles in this volume that carry a code at the bottom of the first
`page. provided that the per—copy fee indicated in the code is paid through the Copyright
`Clearance Center. 29 Congress Street. Salem. MA D1-970. Instructors are permitted to
`photoootii/i without fee. isolated articles for noncommercial classroom use. For other
`copying. reprint. or republication permission, write to the Directorof Publishing Services.
`IEEE. 345 East 47th Street. New York. NY 1001?.
`
`IEEE Computer Society Firess Orde Jil-ug
`_r 2185
`Library of Congress Num ‘
`
`IEEE Catalog Number 91T
`ISBN 0-8186-2185-0 (paper)
`ISBN 0-8186-6185-2 {microfiche}
`ISBN 0-3186-9185-9 {case}
`
`‘E55 CDTHPUIBT Society Press
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`© THE men-ru-rs or ELE{‘."TFlICAL AND eLeo‘rnomcs ENGINEEI-11!, mo.
`
`5
`
`

`
`WELCOME 'ro EURO ASIC '91
`
`Euro ASIC '91 is the annual European conference presenting state-of—the-art
`ASICs. Organized in 3 very impressive-site - Palais des Congres, Porte Maillot,
`Paris — the conference is held in conjunction with a large international industrial
`ASIC exhibition. The conference includes reports on ASIC design experiences,
`advances in design methods and tools, and on the evolution of ASIC technology,
`with a special focus on analog digital ASICs. It includes a user forum discussing
`the current status of industrial tools and design methodology. Twenty-eight
`ASICS will be presented to compete for the Euro ASIC '91 prizes given by the
`European electronic press.
`
`Euro ASIC '91 is the definitive place for companies to select the best choices for
`their designs, for vendors to meet potential customers, for small and medium
`size enterprises to share information, and for the academic community to
`exchange ideas.
`
`Finally, Euro ASIC '91 includes a program of high level tutorials on new and
`exciting topics.
`
`Professor Gabriele Saucfer
`Instftut National Polytechnique
`Grenoble, France
`
`6
`
`

`
`COORDINATION COMMITTEE
`
`T. Baker, £52
`I. Vie-ira Da Silva, MTA
`i.P. Feste, Group: Tests
`A. Lorenzl, Cetia
`M. Robert, University of Montpellier
`].C. Rosichini, VLSI Technology In.-:.
`G. Saucier, Institut Nnntmal Pofytechnique dc Grenoble
`E. Schfltz, Mietec-Aicatei
`J.M. Tissandier, SGS Thomson
`
`INTERNATIONAL PROGRAM COMMITTEE
`
`Belgium
`L. Claesen, IMEC
`
`Germany
`E. Hfirbt, Siemens AC.
`G. Zimmerman, University of Kaiserslmztarn
`K. Schliiter, ABC
`
`France
`
`I). Auvergne, University ofMonipeIh‘er
`M. Le Halley, Ecole Centrale de Lyon
`
`Italy
`I’. Capocelli, SGS Thamson Microefecrronfcs
`M.G. Sami, Pohtecnico di Miiano
`
`Iapan
`G. Goto,Fuj1'tsu Laboratories
`T. Yanagawa, NEC Corporation
`
`The Netherlands
`H. Van Nieien, Phflips
`
`Spain
`J. Aguilo, Un:*versI'fy of Barcelona
`I. Huertas, University of Sean’I.'a
`
`Switzerland
`1’. Aubert, CSEM
`].C. Marlin, Dectraswiss
`
`United Kingdom
`A. Ambler, Brunei’ University
`R. Cottrell, LSI Logic
`
`USA
`
`VD. Agrawal, AT£*T
`G. De Micheii, Stanford University
`
`7
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`INTERNAHDNAL PROGRAM cbiakixi-rizéfi ..
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`'
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`SESSION: MIXED ANALOG DEVICES I
`CHAIR: E. Scnfirz
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`Advances in High Speed ECL Technology and Interconnection Techniques .
`K.-I. Ohm
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`DBIMOS: The Mix in One Approach . . .
`E. Tack
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`SESSION: MIXED Amuoc Davrcas II
`CHAIR: LM. TISSANDIER
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`A Versatile Building-Block for High-Speed Current-Mode Analog {CS .
`R.B. Steak, A. Kostka, and K. Lchmanrt
`DSP-ASIC Based Voltage Feedback Switching Regulator Chip for
`Electromcchan.icalContactnr.
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`P. Salami, T. Karma, and H. Terdumen
`A Smart Power [C for High Side Driver Applications .
`Y. Drains!
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`AlgorithmicADCfor Use in AS_ICDesign.
`K. Dewy
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`SESSION: Dxcrrm. SIGNAL PROCESSING ASICS
`CHAIR: C. Prror
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`KISS-'16: Realization ofaDSP Optimized for Digital Mobile Radio Systems .
`H. Sahm, I. Schuck, H. Ebert, D. Weinsziehr.
`I. Pretksner, and G. Mnhfich
`AS[MDMacl1ineforBean1fomu'ngonaC11lp .
`I.-P. Giacalone and Y. Del Gnfla
`VLSIImp1ernentationola Cochlear Model ,
`N. Anellana, F. Ganida, I. Carmbfna,
`E. Valderrama, and P. Gdmez
`Single'Chip RNS Two-Port Parallel Adaptor for Wave Digital Filters .
`G.C. Cardarflli and 1-‘. Sargenf
`A16/24—BitDSP-ASIC Coprocessor for AC Motor Modelling.
`SJ. Ovaska, 0. Vainfo, and I. Pasanen
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`SESSION: CHI-P.ARCHI'I'ECI‘URE
`CHAIR: A. Lommzz
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`Processor Chip Design onsubmicron ASICS.
`H. Schleltef
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`Design and Implementation of a Dedicated Neural Network for
`I-IandwrittenDigitRecognition .
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`P.—Y. Alla; L. Massewxwette, I. Ouali, G. Saucier, S. Kmzrr,
`L. Personnaz, and G. Dreyfus
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`SICU‘RE0—AC1-yptoChipforkapidflncipherment.
`HM. Deppemzarm, j’. Gessnsr, S. Kffisfers, and S. Wuflsta
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`

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`:r_.,_._.———————?~~
`
`TABLE OF CONTENTS — EURO ASIC '91
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`WELCOME .
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`COORDINATION CDMMIITES.
`INTERNATIDNALPROGRAMCOMMITTHE.
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`SESSION: MIXED ANALOG DEVICES I
`CHAIR: E. ScHfi1'z
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`Advances in High Speed ECL Technology and Lnterconnection Techniques .
`K.—I. Ohm
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`DBIMOS: The Mix in One Approach .
`E. Tack
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`SESSION: MIXED ANALOG DEVICES II
`CHAIR: ].M. TISSANDIER
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`A Versalile Building—BlOck for High-Speed Current-Mocle Analog ECS .
`R.B. Slack, A. Kostim, and K. Lehmann
`D51’-LASIC Bawd Voltage Feedback Switching Regulator Chip for
`Electromechanical Contactor .
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`P. Solanfi, T. Karemrmmd H. Tenhunen
`A Smart Power IC for High Side Dl’iV€I_‘ Appiicalions .
`Y. Droinet
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`Algorithmic ADC for Use in ASIC Design .
`K. Dewy
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`SEssION: DIGITAL SIGNAL PROCESSING ASICS
`CHAIR: C. PITOT
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`. 53
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`l(.I5S~16: Realization ofa DSI’ Optimized for Digital Mobile Radio Systems.
`H. Sahm, J’. Schuck, H. Ebert, D. Weirxszieixr,
`I. Preissner, and G. Maitiich
`ASIMD Machine for Beamformingona Chip. .
`I.-P. Giacalone and Y. Del Gallo
`VLSI Implementation of a Cochlear Model .
`N. Aoellana, F. Garrido, J’. Carrabfna,
`E. Valderrama, and P. Gomez
`Singletfhip RNS Two-Port Parallel Adaptor for Wave Digital Filters .
`GE‘. Cardarflii and F. Sargenf
`A 16/2rl—Bit DSI’-ASIC Coprocessor for AC Motor Modelling .
`SJ. Omska, O. Vainfo, and I. Pa.-sanen
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`SESSION: CHIP ARCHITECTURE
`CHAIR: A. LORENZ!
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`Processor Chip Design on Submicron ASICS .
`H.Schlei:er
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`Design and Implementation of 3 Dedicated Neural Network for
`Handwritten
`ReCDgniti0n.
`n
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`I
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`I
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`I
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`I
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`P.-Y. Alia, L. Mrzsse—NRvette, I. Ouaii, G. Saucier, S. Knerr,
`L. Persormaz, and G. Dreyfus
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`5lCURE°—ACIypto Chip for Rapid Encipherment.
`HM. Deppermann, I. Gessner, S. Kdsfers. and S. Wallstab
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`.68
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`

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`Reduced Voltage Swing, High Speed CMOS Driver, Receiver Techniques for
`Multiple Chip 5-etAppl1catrons .
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`.74
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`SESSION: HIGH LEVEL LANGUAGES
`CHAIR: F. RAMMIG
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`VI-IDL in Logic Synthesis—An Applications Perspective .
`W. Ries amt K.M. Inst
`UDL/l Standardization Effort—Another Approach to HDL Standard .
`0. Kamtsu
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`SESSION: GRAPHIC Apmcanon mo IMAGE PROCESSING ASICs
`CHAIR: R.A. COTIRELL
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`An Image Decoding ASIC for Space—Baseci Applications .
`13.3. Krista and G. DeMt'r:helt'
`A Data—Fiow Processor for Real-Time Low—Leve1 Image Processing .
`G. Quénot and B. Zavidomique
`A Dedicated Circuit for Real-Time Motion Estimation .
`O. Colavin, A. Artieri, I.—l'-‘. Naviner, and R. Pacaiet
`CMOS Video Cameras.
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`G. Wang, D. Renshaw, P.B. Derryemtnd M. Lu
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`SESSION: Locic SYNTHESIS
`CHAIR: G. DUPENLOUP
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`A New Approach to Timing Driven Partitioning of Cornbinatiortal Logic .
`N‘. Weim and M. Gleaner
`Synthesis and Partitioning of Standard Cells for Fioorplan Optimization ,
`E. Chotin, T. Bessormznd G. Saucier
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`VLSI-Oriented Asynchronous Controller Synthesis Based on a
`Flip-Fiop Cell Array Str1.tct‘ure
`K.R. Cha, M. Ikeda, and K. Asada
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`.112
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`SESSION: HIGH VOLUME ASICS
`CHAIR: T. BAKER
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`.124
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`128
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`A Mixed~Mocle ASIC for Interface Controi of Smart-Card Parcrneter .
`E. Compagne and F. life
`A Doubie—Sourced ASIC for Contactiess Badges .
`R. Petigny and P. Cabot:
`VI_.SI ASIC Design for MAC Video Processing integration in SGS-Thomson
`Microelectronics Chip Set .
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`A. Lorenzi, G. Vannezwitie, V. Vzrfaille, N. Chntimartin, G. Gerot, and mi. riiafidé '
`SESSION: LOGIC Simrrnt-zsis II
`CHAIR: G. De Mrcnem
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`. 13]
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`An Efficient Program for Logic Synthesis of Mod-2 Sum Expressions .
`P. W. Besslich and M14’. Riege
`Automatic Synthesis of Boolean Functions on Xilinx and
`Actel Programmable Devices .
`P. S1'r:ard,M. Crasfes, K. Sakauti. and G. Srtucfgr'
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`I
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`‘
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`142
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`viii
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`10
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`

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`Algebraic Decomposition of MCNC Benchmark FSMS for Logic Synthesis .
`T. MiIlier—Wipperfi‘Jrth and M. Geiger
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`.146
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`SESSION: ASICS FOR DEDICATED Comeumnon AND ARCHITECTURES
`CHAIR: J. HUERTAS
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`.162
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`VLSI Chip Set for Floating Point Vector Processing .
`A. Laudenbach, M. Glesner, P. Windirsch, I. Plfli1i,flI1d W. Clemens
`VLSI Design of an 3-Bit Fixed Point Cordic Processor with
`Extended Operation Set .
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`D.E. Metafas, G.A. Krikis, and CE. Goufis
`Pipeline-Based Design for Numerically Controlled Oscillator .
`L. Ii, D. Li. S. Sheng, and Q. Liang
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`Design and Implementation of HRISC2 .
`A. Bouamoua, Y.I. cl-Hafiiif, and A. Amari
`Searching Processor .
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`LB. Barbosa, M.B. CcIlJ‘Ia,arId LC. Tefxeira
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`SESSION: HIGH LEVEL SYNTI-IESIS
`CHAIR: S. MARI
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`. 173
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`Resource Assignment with Different Target Architectures .
`A. Mignoite and M. Creates tie Pa-ulet
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`Flexible Datapath Compilation for Phideo .
`A. van der War)‘, 8.1‘. Mcsweeney, LL. em: Meerbergen,
`P.E.R. Lfppens, and W.F.,l. Verliaegh
`A New Method for the Minimization of Memory Area in High Level Synthesis .
`B. Rouzeyre and G. Sagnes
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`SESSION: SIMULATION
`CHAIR: D. AUVERGNE
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`High Precision SPICE Models for the Simulation of Analogue CMOS Circuits .
`B. Ankele and F. Schrarik
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`Power Calculation for High Density CMOS Gate Arrays .
`W. Eisenmann and M. Kalil
`ACC: Autoinatic Cell Characterization .
`K. Arishunzali’
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`SESSION: PLACE AND Room
`CHAIR: T. YANAGAWA
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`Timing Driven Pin Assignment in a. I-Iiera'rchicai Design Environment .
`G. Meixner and G. Zfmmermrmn
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`A Genetic Algorithm for the Routing of VLSI Circuits .
`M. Geraci, P. Orlando, G. Vassaiio, and F. Sorbelio
`A New Graph Theoretical Approach to the Selection Of Rip-UPS -
`M. Barthoimneus and M. Rnifh
`Optimal Module Orientation by Block Rotation and Wire Length Minimisation .
`PJ. Drenih. I.G.G.P. van Giisbergen. and M. Lmisberg
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`.212
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`.218
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`- 2?-4
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`.230
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`11
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`

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`Sesslow: ASICS IM.l’LEMEN'1'ED [N EUROCHIP
`Cmm: B. COURTOIS
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`.239
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`. 243
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`. 247
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`.251
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`Implementation of a Linear Array Element for Matrix Multiplication .
`MA. Mano-rte, L. San‘: tie Queoedo, P. Talmenca,
`ll. Martinez, and E. Villar
`Design of a Complex Cornbinat1'onalASIC with Educational Aims .
`P. Amblard, M. Hollett, S. Audié, E. Bitter, C. Chcmdy,
`P. Coulomb, S. LeMen, O. Ondoo, E. Piot, and F. Pogodalla
`Serial Data Interface for Telecommunication Satellites .
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`1. Varmeuvillefi. Manhaeve. and D. Geooert
`A Digital CMOS Fully Connected Neural Network with In-Circuit Learning
`Capability and Automatic Identification of Spurious Atiractors .
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`}'.-D. Gascuel, M. Weinfelcmnd S. Chakroun
`An ASIC For Image Dilation and Erosion .
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`Y. Terms, 1. Rampart, and M. Baataur
`Real Time Image Processing System: Design of an Area CCD
`Sensor Driving integrated Circuit .
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`E. Fauvet, M. Paindaooine, J.-F. Kirilenlco, M. Robert,
`D. Dascimchf, and D. Auvergne
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`SESSION: MULTIPUER DESIGN
`CHAIR: ].C.Ros1cHmI
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`.260
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`AFastDataPathMultiplier.
`C. Print and P. Magarshack
`On the Construction of Very Large Integer Multipliers .
`G. Hatz, P. Molitor, and W. Zimmer
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`SESSION: CAD FOR Tesr
`CHAIR: T. AMBLER
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`. 272
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`Test Generation Using Cross-Observability Calculations .
`E. Cemy. EM. Aboulhamid. C. Mamas, and P. Rioux
`Comprehensive CAD Support for Boundary Scan Implementation in ASICS .
`P. Lesiml. R. Leoeugle, and P. Mugarshack
`Test Generation of Controllers Using the Synthesis Specifications .
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`M. Karam, G. Saucier, and C. fay
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`. 273
`. 234
`
`SESSION: AS_lCs eon TELECOMMUNICATIONS AND COMMUNICATIONS
`CHAIR: C. AUBERT
`
`ASIC Cryptographtcal Processor Based on DB3
`I'.V"5"“‘”h“"5«P- H00?’?W1'U— VaudewaIle.':ri1:tl
`The Design of the PR1 ASIC
`_
`_
`F. C. Torre
`ASIC Chip Set Development to PCM 2 .5: 3-
`oemux with as Project
`I
`I.
`‘
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`6Bits Programmable VHF Amplifier.
`'
`'
`C. Vanhccke
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`High-Speed CMOS Operational Amplifier .
`S. Schwehr, T. Fuchs, K. Dzahini, B. Bouthermamd M. Le Halley;
`
`G
`my mp MUX and
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`.301
`.305
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`12
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`

`
`SESSION: DESIGN FOR Tes"r!QuALrnr
`CHAIR: R. SEDMAK
`
`.
`High-Quality Physical Designs of CMOS ICB .
`}'J.T. Sousa, FM. Goncalrzes, and LP. Teixeim
`Design of Highly Reliable VLSI Proces-sors Incorporating Concurrent
`Error Detection/Correcfion .
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`G. Russell and LD. Elliott
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`.316
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`Integrating Verification Testing and Logic Synthesis _
`W. Mu rzyn and A. Kmsniewski
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`_ 322
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`SESSION: Tesr MeAsum~:MsNTs Tscnmouss
`CHAIR: M. LE HELLEY
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`_
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`_
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`_
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`_ _323
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`Testing ASICs At-Speed .
`C. Gcmthron
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`Ultra-High Speed ICs Set for Test System Design .
`A. Balevskf, A. Shishkcrv, R. Elenkova, V. Soliakoo, and A. Adamov
`A Temperature and Voltage Measurement Cell for VLSI Circuits ,
`,
`GM. Quénet, N. Paris, and B. Zauidovique
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`_ 333
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`, 334
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`INDUSTRIAL APPLICATIONS
`SESSION:
`CHAIR: H. VAN NIELEN
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`. 340
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`Digitai Speed Regulation for a Washing Machine Motor .
`C. Ferrer and ].M. Aguirre
`Design of a Robust Analog/ Digital ASIC Interface for Hard Industrial Environment .
`I. Smrtari, H. Tmhuneri, and J. Nikola
`ASIC Design Considerations for Power Management in Laptop Computers ,
`‘(.44. Dubois and LI. Farrefllll
`An A! [)—Chip for Accurate Power Measurement .
`R. Rauscher and V. Gmpe
`Using a CMOS ASIC Technology for the Development of an Integrated ISFET Sensor ,
`K. Dzahini, F. Gafi‘iot,and M. LeHeHe_1;
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`SESSION: LAYOUTSYNTHESIS
`
`CHAIR: LFREHEL
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`. 362
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`.344
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`.348
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`Evaluation of VLSI Layout Style Implementations {or Efficiency .
`M. Robert, 1. Tmushessec, G. Cothebms. V. Bortzom, N. Azemard,
`D. Desclmchi, and D. Auuergne
`GZL: System for Converting Low-Level Geometrical Designs to a
`Higher Levei Representation .
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`E. Pczjarre, T. Rftoniemi, and H. Tenhtmert
`Branch—Based Digital Ceii Libraries ,
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`}.M. Masgonty
`Datapath Layout Generation with In-the-Cell Routing and
`Optimal Column Resequertcing .
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`R}. Drerttlt and C. Sfratenberg
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`. 366
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`13
`
`

`
`CMOS Video Cameras
`
`G. Wang. D. Renshaw, P. B. Dengrer and M. Lu
`
`University of Edinburgh
`Department of Electrical Engittecring
`Mayfield Road
`Edinburgh, EH9 3JL, UK.
`
`
`
`mmmyxa.M....
`
`AbsIJ'ac!
`
`A .s'r'.Hgi<* chip CMDS rider: camera it prmerrred.
`almrq u-it):
`t!e.t'ign lc-‘(.'hr::'qm= and z:lmr'r1creriza.'iorr
`.I'ca\‘:rh.r.
`‘Hie chip :-rm:pr'i.tv.\'.
`(I 312x287 pixel
`p.lmr(.Idr'rJc.’r.' m‘:'rty mgt.‘Hle':'
`at-*t3t}'I
`(IN the ner.‘cs.rur')-'
`._\'en.\'t'Jt_s,-‘.
`crd:r’r'c:.m'.=Jg mm‘
`:r::tpltfvt':tg c:'rcuirr_y. m.-
`tt-‘eli
`rm‘
`:1 1.000 gate fogic pI'l')L'l’.5'.5‘0f',
`1v!1i:r.‘It
`.*'.ll:|"IiPi£’J!l'.L’.'l.".':'
`.s_w2c!rrwtizatiort
`tintittg to deh'ver a
`ji:ll_1-'-_fw'ra:utrEd
`t'am,m.:.w'm video sigttal and (I
`f.w'rlter 1.000 _t{(t.'r.'
`:’o_t,>:'c pmce.r.rm‘, wIn'r;l:
`imple-
`.f.U('JH‘.\‘
`crm*‘un:m.*'r:
`e.'.‘pr2.m.*'e= catttrol over
`(I wide
`J‘r.i‘ll_t3'¢".
`TIwre are :rl.m .ri.mp.r‘e
`.\'o!mt'au.r for -y
`t.'ur'.='z'c*tr‘u.r.r amt’ text.
`
`I.
`
`Irilreducliml
`
`We ilttrutlucc :1 new canpabi|ity‘tl1at extends the
`CMOS ASIC marketplace in El sector of high
`gmwtlt rates. 'I'|tis In:lI'l<£!i sector is that uf image
`scltsing and DI‘t.'lL‘L'S5ill1_l_:. covering applications
`from ulectmnie cL'.n1uI':ls
`tn ‘smart’ visilm sys-
`ICITH.
`
`(Imneru uml vheinn .~:_\'.~:lel11.~s itdtlressetl by mLl:w'.~:
`("CD teelmnlngy u;':p_c:lr
`eumht:r>_‘.nn1t:.
`])t)\vcr—
`ltungry uml cmettsive. The experinicntul wurk
`|‘L‘}1r’rI'tL‘Ll
`here Llemmtstrates
`that hig|‘I-quality
`imznge :«'v.'.I1>:n|‘5 can he implemented entirely in
`uummndity ASIC Ch-1()S teclmelugy, operating
`frcmt sitt-glc Sv s1tppl'ic:-:.
`
`‘l'he repurtcd chip is :1 Iiighly-integrated CMO3
`VLSI Czlntem.
`.~:h()wn in Figure I. Most of the
`cure urea I2.‘
`:1 3I2><28'l‘ pixel image sensor array,
`tug4.:titcr with the I1L'cc5e+z1|'y sen'.<ing. addressing
`and :::np|il'yit1g circuitry. The output signal can
`be either linear or 1 cnrrccted.
`'y con-cc-iicm is
`mrlnevecl hy :1 simple solution which ugcg the
`I1UIt|111L=:tr
`[D-‘-/GS eltarzteteristic of an M03
`
`THO367-3l91!00O0!01 D0$01.o0 © 1991 "555
`
`tramtistor. The ln_\-‘nut of the :-zcnsnr is cttstnm
`designed to make it
`:1:-; enmpacl its pttssilalc.
`
`At the top ("Figure l] is the 2.000 gate logic pm-
`cessor,
`laid out
`ti:-:in_t_:
`at
`semi—<:L1sl-um standard-
`5
`cell-compiler.
`I--iulf of therst: gates gencnulc .\‘}-’n-
`cl1ro:1i?.uti0n
`timin_t_z.
`including litre-sync and '
`ft‘£iI1'lC-S}'|”l<.'
`signals
`In format
`21
`625Eine!.$lIllz
`Staitclard composite video output. The ntltcr
`half of the gates are included to electronically‘
`L‘t)I1[I‘0l exposure over a witlc range (40.(lllll:1].
`enz1hli11g the use ml"
`:1 single fixecl-ztpertttrc lens.
`The chip 111e;t_~;ut'r.-.r.- 7.58mm ><7.5($n:.=H. using l.5
`pun. 2 level mernl ('.fl\l{)S teclmnlugy.
`
`Figure 1.
`
`Plmtu-:11icrugrnplt nf .=‘.inglc Clllli
`vitluu culneru
`
`14
`
`

`
`A video eiiinetii has been built using this chip
`iIl0|l_i_1 with it
`6 MHZ clock source.
`ti 5 volt
`ptm-i.-r..~iipp|_v. plus tine hipolar traiisistor and a
`Rlllilll
`iiiiinlut-I‘
`of msisiiirs
`and
`eupacitors
`1'L‘t|llll'L'(l
`in iiiiileh the line l['l'lpCClil|'IL'i.‘.‘
`to the
`lli(J|llll‘l1'
`:intl
`ileetiiiple the power supply The
`piettiii:
`:.ll.t:lll.l_\‘
`is
`siili_|'ectivel_v cxcelleril.
`and
`t.'umpiii'es well with eoriiniereially available carri-
`eriis.
`
`2.
`
`Iimigi: Sensor Block
`
`The iircliileetiiric of the int:-ige sensor is shown in
`Figiti'e 2. The light sensing area consists of a
`.'ll2><2.\'7 Llintle ;irI'ti_v iiititrirt. schematically incli-
`(.'l|lL.'Ll by the Ci)lllll1l1H :inL.l
`rows of individtial
`plititotliiicles.
`'l'hi;: pixel size is 19.6ii.m><l6p.iii.
`giving :1 light sei1.\;ii1g eireti of 6.l2mm ><4.59mm.
`This eiirrespoiitls to the st.-iiidard H2" formal.
`
`iCVO
`
`l supplies
`
`clock I‘lUl'
`
`gain
`setting
`
`cal shift register. At the top of each column is ii
`sense ziniplifier.
`'l'lie sensed irifiirrn:-itioii
`is t'i’.!iItl
`our .«;eqiienti;i|l_v along the it-direciioii itiitler eon-
`Irnl of :1 l'lUl'lZUl1I&1l shill register. At the end til"
`the path there is an output iin1plit'ier|l.2].
`
`The sense iimplitier is ;i siiigle-eiiclt-ti Lliflereiilizil
`cliiirgc iiitegraitor.
`Its; perltirmaiitce Lleituiiuls an
`accurate eaipiicitor,
`furiiied by ittciailltmeliilil
`and itteiallfpoly. However. C{)|'Tlm(}(.lll‘_l‘ ASIC
`CMOS tecliniilogy sometimes can not gutiraiiitee
`the resulting eapaeitamee values. We designed it
`gziin-controllithle iitiegrzitor. sliniwn iii Figtire. 3.
`which allows wide raiigi: nf prtigrnmmtilnle \‘ill’lElv
`tion of the L‘£l|‘.|1lCllili'lL‘C Vtllltc.
`
`——i P
`'
`% C:
`|____._
`,\
`Tl l --I— gain oontrol transistors
`
`ai.ito—eicposuri2
`control
`
`video format
`liming & control
`circuits
`-
`
`‘J
`
`—- iiorizontal addressing
`.. r‘"::i_
`column sense amps
`I’
`
`
`
`
`
`auto-testpatterndecode
`
`
`
`verticaladdressing
`
`|igh_l
`sensing
`area
`
`auto test pattern generation
`
`...
`
`' CVO —— composite video output
`
`Fii_:m'i.' 2. Areliiteeltire of the image sensor
`
`£1CCt1liS{;‘d on the basis of
`'l‘lie plitatoiliocles 1111;‘
`seqiientiiil selcctiuit of each row through a verti-
`
`sell
`compensation
`
`_
`
`Figure 3.
`
`Integrator with progranimzihle gain
`and self cornpensation
`
`Thai: main concern in the output stage design is
`the read-iiut
`speed required to achieve high
`resoluiioit. A 6 MHz clock was cliosen for this
`
`design; this gives ii horizontal resolution of 312
`pixels. The rcsultaiit picture quality is assured
`by a two stage output buffer with sample and
`hold function.
`
`3. Automatic Exposure Control
`
`The device iiiitomaitietilly controls its exptisiire
`over 21 range of -'-l0.0{l0:l. Control
`is achieved
`by varying the inte_i_:raIioii
`time prior to rciiiliiig
`eacli row of pixels. The iiiiegrzitioii
`time can he
`as long as one l"ie|Ll. or as sliiiit as three i:_i=e|e::
`of the pixel clock(;ihniii Smfil-1S)l
`
`15
`
`

`
`in Figure 5.
`
`Vdcl
`
`Cortwtetl
`
`otllptll
`
`Linear
`
`input
`
`r——--l
`
`Figure 3..
`
`GEII'|'||'il1I L'f.’|'lT(.‘i.'-l(ll'
`
`SPICE 3~ilITllIl:lllE)I1 \.\';lS c:1:'i'ie:i nut and Li simulat-
`
`is .~ahnwn in Figtltwc (3. A titenrctic:ii
`tion result
`curve at itieail
`'y currcctioit
`(
`‘y =li_45} is £|i.\'ll
`HIIUWI1 in Figure 6,
`
`ideal L'|.ll‘\‘t'3
`
`Sin1I.1l:1tir)It result
`
`\ ‘
`
`Kc
`
`The exposure is set by monitoring the video
`strettm and estimating the frzlctimis of eaeli pic~
`tun: which are very white and very black. On
`the liasis of this information.
`the device decides
`whetlter the picture contrast is acceptable, or too
`white. or too dark.
`If necessary,
`the exposure
`time is lht-111 changed, in the appropriate direc-
`11011.
`
`4. Generation of the Vitiee Format Signal
`
`Fig__LIrt_' 4 shows a block diagratn for the genera-
`tion of
`the video formatted signal, The «,4
`currecreti
`image data is multiplexed with the
`s_vn::—Ic\-'el and hlanl;ing—lev::l, controlled by firm-
`ing mntrni signals, which are provided {mm the
`video
`timing
`hlcnck.
`A bipolar
`lI':tI'i3ilS¥(1t‘
`(urnitler
`rullnwcr)
`is needed It} provide it
`iuw
`irl’I|1L'(i.’lllE.‘C output.
`
`Video
`
`timing
`
`lltinge signal
`
`lrtutgc
`
`WCIISOT
`
`1ax::[dnp1w
`
`Sync
`level
`
`Blzmking
`levei
`
`Fi_i;m'c =1. Gcnerutinn nf the video output
`
`5-
`
`-"W113"? Snluliun for 1 Currecliun
`
`‘y
`he
`In
`iintngu data needs
`:n::||u_i1ue
`l'hu
`mr'|t-at-tl.
`tn m_mpcI1.~'utc fur the mmliiicariw Df
`Itlnniltir tubes L3]. This is u.~;u.;,;]y gmplcmclimd
`1I>i||!_t__' r.li<cr::1u components e.g.
`:1 Intlder-netwtark
`at
`climics,
`resistors;
`and
`reference voltages.
`Uni'airtuntili.'l}=.
`this is not suitable for
`integm-
`ticm.
`in this tie.-;i_:;n -y correction is zxchievcci by
`:1
`.~;imple sultnion which uses the nonlinear I
`-
`\/Us c|1:ir::ctcri.=:tic (if an M05 PET. as sltcixisiiii
`
`0.2
`
`0.4
`
`0.0 M It
`
`Figure 6.
`
`C_‘::.m1n1;1 s.nri'L'<:li:i11 cur\'L'5
`
`6. Simple Sulutinn fur '11-sl
`
`Special uimitlcruiimt Ims been _L1E\-’I.‘ll in mtikt‘ _|l
`])(J.‘i!~'li‘JlC tu <.'.u1‘1‘y tllll digital
`\\';I|L'r
`test w|iiL'|I I34
`as curnpletc as pn.~:~;ih|c_
`'l'he airialugtic parts am‘
`also tested by nmt.;ing them prmiut-c digital mil-
`Pllts. so uvtnitliiti-’ it
`ret]1IiI‘ument for full
`illliIlil-
`Euc
`test. The il.'!il
`il'1Cltl(it.Ԥ
`l1it—line
`ft"-‘-5“ mid
`word-line tests. Only in
`lJ.7HC'i> incrciltic in clltp
`area was rct]uirt.‘iI
`tn implement
`the on L'll|[3
`
`16
`
`

`
`l‘I£lr(i\\’2tI’[: ttccessary for this form of testing (Fig-
`ure 2). The ll1(il\’iL'l|.t1ll photo pixeis may he
`tested it‘ a .~:ui‘ficicnt|y long vector set
`is a|Iow-
`tli)iC.
`
`"the chip can also scltlgcnerztte a checkerboard
`pattern which may be displayed on :1 monitor
`screen. or capturctzl by a frame grabber. This
`pattern can be used not only to find defective
`pixels, but aiso to check analogue performance
`parameters. such as read out speed and unifor-
`tttity.
`
`7. Elitninalittg Noise
`
`Complete guard rings are put around all analo-
`gue parts to minimize interference from the digi-
`tal parts. Routing is arranged with priority to
`analogue output and analogue power supplies.
`Analogue power supplies and digital supplies are
`sepimtlctl. and supplies to different analogue
`parts :Irt.: Llivitlcd where necessary.
`
`fixed pattern noise:
`‘there are two sources of
`tltresltulti variation in the MOS pixel access
`transistors causing specklcs,
`and‘
`tTtlS[¥lElICi'tt:S
`between the column sense amptificrs causing
`vertical stripes. The solution to the pixel thres-
`l'l()lt.i variation is to reduce the pixel reset voltage
`helow (Vdtt-Vt)
`so that
`the reset voltage is
`insensitive to the variation of the threshold Vt.
`
`Column fixed pattern noise arises mostly from
`trffsct
`tuisrriatcltes in the column sense amplif-
`iers. We have successfully eliminated this prob-
`lem hy autornatically compensating each amplif-
`ier to give zero offset during each line synchron-
`ization interval.
`
`3. Clmracte'rir.ati_on
`
`test measurement set-up was used to
`An optical
`characterize the camera. The following table
`summarize the measured results of the perfor-
`mance characterization expcrirnents. The param-
`eters of typical
`tnonoeltromc CCD cameras am
`also given for cotuparison.
`
`operating voltage
`for catnera
`
`power dissipation
`for chi .
`
`power dissipation
`for camera
`
`ex OSU. 1'6 l'Eil'l ‘EC
`
`satttration level
`
`antiblooming fact_or
`dark current‘
`
`sum
`
`52:18
`
`. * as fraction of Si-li'l.1t":iIi{‘.|l‘t at room temperature.
`20msec integration time
`
`9. Conclusions
`
`We have developed several design tccltniqucs to
`achieve a
`single chip camera.
`it1 ut1rrto4.|i't'iet|
`CMOS
`teclmology.
`wltieh
`trtatc-lies
`the
`pctlormattcc of CCD cameras. The ticsigit has
`proven that three technical barriers wltich most
`greatly influence new product development:
`cost,
`power consumption and size.
`are
`ail
`dramatically reduced over
`today's
`soiicl-state
`camera tecltttoiogies.
`
`ID. Ackttowledgetnenls
`
`received from the
`We acknowledge support
`Science
`and Engineering Research Councii
`(Grant GRIP 36538 IEDZ/H1159).
`
`11. References
`
`cl". al., "ASIC Vision", Proc.
`[1] D. Rcnshaw.
`IEEE
`C1i.“tI()m
`integrated
`Circuits
`Conference, 1990, pp 3038-3041.
`
`ct.
`
`"ASIC image
`al..
`['2] D. Rcrisltaw.
`International
`IEEE.
`Sensors“,
`Proc.
`Symposium on Circa-its and Systems. 1990.
`pp7.3.t-’i.3.el.
`
`and Video
`'l'elevisio11
`Eugene 'l"rLtndlc,
`Engineers Pocket Book. Heinctrtattn, 1987.
`
`17