United States Patent [19]
`United States Patent [191
`Uesugi et al.
`U esugi et al.
`
`lllllllllllll|||llllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`111111111111111111111111111111111111111111111111111111111111111111111111111
`USOO5459683A
`US005459683A
`5,459,683
`5,459,683
`[11] Patent Number:
`Patent Number:
`[11]
`Oct. 17, 1995
`[45] Date of Patent:
`Oct. 17, 1995
`[45] Date of Patent:
`
`[54] APPARATUS FOR CALCULATING THE
`[54] APPARATUS FOR CALCULATING THE
`SQUARE ROOT OF THE SUM OF TWO
`SQUARE ROOT OF THE SUM OF TWO
`SQUARES
`SQUARES
`
`,bth
`75 Inet :MitsrU ';K 'h'H
`[75]
`Inventors: Mitsuru Uesugi; Kouichi Honma, both
`[
`1
`v n ors of Ygirhm?zuipanomc l onma 0
`of Yokohama, Japan
`’
`[73] Assignee: Matsushita Electric Industrial Co.,
`[73] Assignee: Matsushita Electric Industrial Co.,
`Ltd., Osaka, Japan
`Ltd., Osaka, Japan
`
`[21] Appl. No.: 277,826
`[21] Appl. No.: 277,826
`
`[22] Filed:
`Jul. 20, 1994
`Jul‘ 20’ 1994
`[22] Filed:
`[30]
`Foreign Application Priority Data
`Foreign Application Priority Data
`[30]
`
`[JP]
`[JP]
`
`Japan .................................... 5-191099
`Japan .................................. .. 5-191099
`
`[56]
`[56]
`
`Aug. 2, 1993
`Aug. 2, 1993
`Int. CI.6
`[51]
`........................................................ G06F 7/38
`[51] Int. Cl.6 ...................................................... .. G06F 7/38
`[52] U.S. CI ............................................................... 364nS2
`[52] U-S- (31-
`364/752
`[58] Field of Search ............................................... 3641752
`[58] Field of Search ............................................. .. 364/752
`_
`References Cited
`References Cited
`m E
`U.S. PATENT DOCUMENTS
`U'S' PATENT DOC
`NTS
`3,829,671
`3,829,671
`8/1974 Gathright et al. .................... .. 364/752
`811974 Gathright et al ....................... 3641752
`811974 Sather ..................................... 3641752
`3,829,672
`3,829,672
`8/1974 Sather ........... ..
`364/752
`3,858,036
`1211974 Lunsford ................................. 3641752
`1;;
`lgin?foig -
`311985 Slabinski ................................. 3641752
`4,503,549
`4,553,260 11/1985 Belt et a1‘
`364/752
`4,553,260
`11/1985 Belt et al ................................ 3641752
`4 599 701 7,1986 v ..
`711986 Vojir et al ............................... 3641752
`4,599,701
`4,694,417
`9/1987 Camwen
`364/752
`911987 Cantwell ................................. 3641752
`4,694,417
`4,736,334 4/1988 Mehrgardt ......... ..
`364/752
`4,736,334
`4/1988 Mebrgardt ............................... 3641752
`4,747,067
`5/193g jagodnik, Jr et a1
`364/752
`4,747,067
`5/1988 Jagodnik, Jr. et al. ................. 3641752
`5,159,567 10/1992 Gobert .................................. .. 364/757
`5,159,567
`10/1992 Gobert .................................... 3641757
`
`,
`
`,
`
`a 1ns
`
`,
`
`,
`
`ojir et al. ..
`
`364/752
`
`0437876 7/1991 European Pat. Off. .
`0437876
`711991 European Pat. Off ..
`2146200
`411985 United Kingdom.
`2146200 4/1985 United Kingdom .
`
`OTHER PUBLICATIONS
`OTHER PUBLICATIONS
`
`_
`Electronics Letters, vol. 10, No. 13, 27 Jun. 1974, Engage
`Electronics Letters, vol. 10, No. 13, 27 Jun. 1974, Engage
`GB, pp. 255-256, Braun et al. 'Digital hardware for approxi(cid:173)
`GB, pp. 255-256, Braun et al. ‘Digital hardware for approxi
`mating to the amplitude of quadrature pairs'.
`matmg to the amphtude of quadrature Pans’
`Electronics, vol. 56, No. 17, 25 Aug. 1983, New York US,
`Electronics, vol. 56, No. 17,25 Aug. 1983, New York US,
`pp. 138-139, Ho et al. 'Comparator compares 2's comple(cid:173)
`pp. 138-139, H0 et al. ‘Comparator compares 2’s comple
`ment numbers'.
`111cm numbers’
`
`Primary Examiner—Tan V. Mai
`Primary Examiner-Tan V. Mai
`Attorney, Agent, or Firm-Lowe, Price, LeBlanc & Becker
`Attorney, Agent, or Flrm—-Lowe, Pnce, LeBlanc & Becker
`
`[57]
`[57]
`
`ABSTRACT
`ABSTRACT
`
`A ?rst digital Signal of a Serial form is processed into a
`A first digital signal of a serial form is processed into a
`second digital signal of a serial form. The second digital
`second digital signal of a serial form. The second digital
`signal represents an absolute value of a value represented by
`signal represents an absolute value of a value represented by
`the first digital signal. A third digital signal of a serial form
`the ?rst digital signal. A third digital signal of a serial form
`is processed into a fourth digital signal of a serial form. The
`is processed into a fourth digital signal of a serial form. The
`fourth digital signal represents an absolute value of a value
`fourth digital signal represents an absolute value of a value
`represented by the third digital signal. The values repre
`represented by the third digital signal. The values repre(cid:173)
`sented by the first and third digital signals are compared to
`sented by the ?rst and third digital signals are compared to
`generate a comparison-result digital signal representing a
`generate a comparison-result digital signal representing a
`result of the comparison. A calculation-result digital signal
`result of the comparison. A calculation-result digital signal
`of a serial form is generated in response to the second digital
`of a senal form is generated in response to the second digital
`signal, the fourth digital signal, and the comparison-result
`signal, the fourth digital signal, and the comparison-result
`digital signal. The calculation-result digital signal represents
`digital signal. The calculation-result digital slgnal represents
`a value which is approximate to a square root of a sum of a
`a value which is aPPmXimate 1° a square T°?t_°f aPUm of *1
`square of the value represented by the first digital signal and
`square of the value represented by the ?rst d1g1tal signal and
`a square of the value represented by the third digital signal.
`a square of the value represented by the third digital signal.
`
`'
`
`-
`
`-
`
`-
`
`-
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`FOREIGN PATENT DOCUMENTS
`FOREIGN PATENT DOCUMENTS
`
`0238300 9/1987 European Pat. Off. .
`0238300
`911987 European Pat. Off ..
`
`4 Claims, 9 Drawing Sheets
`4 Claims, 9 Drawing Sheets
`
`20
`,
`JV
`l
`/V
`1
`..
`Sa —><l>———*——+ ABSOLUTE
`ABSOLUTE
`Sa
`.....
`_ . COMPA
`VALUE
`..
`VALUE
`..
`Sb
`——> COMPA
`Sb ——#<
`
`——————-+
`
`.. ..
`
`I
`
`'
`
`I
`i
`
`fr21
`/V
`.. ABSOLUTE
`..
`..
`—--> ABSOLUTE —————-—>
`VALUE
`..
`..
`CALC
`CALC
`-~*——~*
`
`.~
`
`JV
`[,V
`
`.
`I
`
`So
`.. ..
`So
`MUL
`MUL ——<>-——>
`
`-1 .
`
`|
`I
`
`--~
`
`RTL345-1_1025-0001
`
`

`
`u.s. Patent
`US. Patent
`
`Oct. 17, 1995
`Oct. 17, 1995
`
`Sheet 1 of 9
`Sheet 1 of 9
`
`5,459,683
`5,459,683
`
`FIG. 1 PRIOR ART
`FIG. 7 PRIOR ART
`
`,-
`
`.
`
`N
`Sb
`N
`Sb
`’?| 7
`
`2
`W2
`N
`Sa
`_
`N
`Sa
`N-BIT
`HUL
`“Pa: ""59
`'
`W3
`3
`N-BIT
`N-BIT
`I : MUL
`HUL
`
`4
`,V
`M
`I,‘ _
`, "A35?
`"
`
`H+1
`"+1
`1’
`
`‘
`
`5
`N5
`So
`SQUARE
`?g‘é’T‘RE —<>-——>
`ROOT
`
`I
`
`-~
`
`FIG. 2 PRIOR ART
`FIG. 2 PRIOR ART
`
`-
`
`-
`
`-
`
`;v6
`
`",,)
`
`_
`
`_
`
`Sa N
`....
`~97“
`N-BIT ~ N-BIT
`Sb -N ""2? { "HEP
`HPX
`HUL
`Sb N
`l+
`
`/,
`,/
`
`I
`
`/.
`
`/
`
`-
`
`-
`
`}VB
`H-BIT H
`S
`H
`was '11
`~ LATCH ~ H+1
`So
`SQUARE
`H-BIT
`M "A39 / 3884‘RE 41H
`ROOT
`ADD
`H
`L..
`I
`I
`
`-
`
`9
`
`N
`
`j\l101
`
`I
`
`_
`
`+
`/
`
`/
`
`-
`
`/
`
`-
`
`0
`
`I
`
`RTL345-1_1025-0002
`
`

`
`u.s. Patent
`US. Patent
`
`Oct. 17, 1995
`Oct. 17, 1995
`
`Sheet 2 of 9
`Sheet 2 of 9
`
`5,459,683
`5,459,683
`
`FIG. 3
`FIG.‘ 3
`
`-.
`N-BIT
`N-BIT
`SUB
`4 SUB
`r+
`
`;13
`13
`~
`-
`
`I
`I
`
`W17
`Wu J [V14
`,,,,,11
`;v14
`/1)7
`Sa N N-BIT
`H+1
`N
`a ,2‘. 2:52am +1"
`"I
`N
`N-BIT ~ H-BIT
`/. ABSOLUTE ~
`..
`ADO
`HPX
`yr
`r
`VALUE
`...
`
`/
`
`{H ;v16
`;v12
`W12
`I
`—§/V15 mp1s
`...
`;v15
`Sb N N-BIT
`N
`N
`Sb
`N-BIT
`N
`N
`r
`u
`N-BIT
`--,4 N-BIT
`r. ABSOLUTE
`-—><5+> ABSOLUTE +—1>__’ "Q3? / "iBF
`HUL
`HPX
`r
`r
`VALUE
`...
`VALUE
`i
`t
`f
`I
`
`I
`
`I
`
`/
`
`-
`
`.
`
`.
`
`--
`
`I
`
`I
`
`So
`so
`
`..
`
`.
`.
`
`FIXED
`FIXED
`VALUE
`VALUE
`
`FIG. 4
`
`W20
`20
`,IV
`ABSOLUTE
`ABSOLUTE
`VALUE
`VALUE
`COHPA
`—> COMPA
`
`Sa
`Sa
`Sb
`Sb
`
`.
`
`I
`
`•
`
`JV' 21
`A, 21
`-. ABSOLUTE
`ABSOLUTE
`VALUE
`VALUE
`----+ CALC
`CALC
`
`I
`I
`
`W22
`;v
`
`•
`
`So
`So
`HUL ~
`MUL —-<>_-->
`
`...
`
`I
`'
`
`L _____ ~
`
`RTL345-1_1025-0003
`
`

`
`u.s. Patent
`US. Patent
`
`Oct. 17, 1995
`Oct. 17, 1995
`
`Sheet 3 of 9
`Sheet 3 of 9
`
`5,459,683
`5,459,683
`
`FIG. 5
`FIG. 5
`
`'
`
`‘
`
`'
`
`'
`
`r
`
`,
`
`1'
`
`JV23
`E24
`N23
`W 24
`88
`Sa
`—--—>O——-——-—¢——>
`EX-OR r--. LATCH
`Sb
`Sb
`EX-OR -—» LATCH
`———><>
`
`1>20
`
`$20
`I
`
`,
`
`Sc
`3°
`--.
`
`f---(
`
`I
`
`.
`
`-
`I
`
`,
`
`,
`
`'
`
`JV30
`
`;v31
`
`JV26
`"—“’ 1-BIT
`1-81T r--. HPX
`f---+ EX-OR
`ADD
`
`ADD —-+ MPX —-+ EX-OR T 1 27
`
`
`1 ! l> 27
`
`5
`
`LATCH
`LATCH
`
`,
`
`5 28
`28
`5
`
`25",
`1~BIT
`25“
`1-81T
`I ~ NOT J-. ADD
`NOT --+ ADD
`T ! [529
`
`I
`
`LATCH
`LATCH
`~------- - - - - - - - - - - - - - - --~
`
`I
`
`RTL345-1_1025-0004
`
`

`
`u.s. Patent
`US. Patent
`
`0a. 17, 1995
`Oct. 17, 1995
`
`Sheet 4 of 9
`Sheet 4 of 9
`
`5,459,683
`5,459,683
`
`FIG. 6
`FIG. 6
`
`/"" 21
`15 21A
`37A
`36A
`37A T‘
`36A
`N
`IV
`IV
`I Sd
`I
`, 1-BIT
`SHIFT
`Sd
`1-BIT
`SHIFT
`-
`~ ...
`..
`EX-OR
`-.
`ADD
`REGISTER 9 EH“
`ADD
`REGISTER
`t-
`t-
`15 35A
`"
`5 35A I
`LATCH
`LATCH
`
`-
`
`34A
`34A
`
`~
`
`-
`
`21A
`
`I
`I
`
`o
`
`38A
`38A
`"J
`
`~ LATCH
`LATCH
`
`I
`
`I
`
`I
`
`Sa
`_"‘
`
`~
`
`.
`
`I
`
`I
`
`~---
`/1/348
`34B
`SHIFT
`I
`SHIFT
`.. REGISTER
`REGISTER
`
`-
`-
`
`Sb
`Sb
`
`y
`
`...
`
`LATCH
`LATCH
`
`I
`
`I
`
`l> 218
`-
`'
`;v36B
`jV37B
`36B
`373
`IV
`Se
`. EX-OR
`1-BIT
`I
`1~BIT
`_
`~ ...
`...
`--.
`ADD
`EX OR _’ ADD —?’_—’
`5 358
`I
`35B
`
`-
`_
`
`5 8
`
`I
`
`38B
`388
`"7
`
`LATCH
`F LATCH
`
`0
`
`RTL345-1_1025-0005
`
`

`
`~
`=" Q()
`,.,.
`\C
`Ut
`-------~
`~
`,.,.
`Ut
`
`Sk
`
`r--'" LATCH r-LATCH -~ LATCH r-LATCH -.. LATCH -
`/V44
`/0156
`
`;v55
`
`",,54
`
`;\153
`
`jY52
`
`MPX
`
`Sj
`
`Si
`
`...
`Sh
`
`"'-LATCH -
`
`I--LATCH
`
`I--LATCH
`
`f--LATCH
`
`.. LATCH
`
`... LATCH
`
`... LATCH
`
`MPX
`
`r-~
`
`S9
`
`Jv51
`
`JV50
`
`j\l49
`
`-
`
`jV48
`
`~47
`
`jV46
`
`Jv45
`
`~ ;v43
`
`-
`
`-
`
`-
`
`FIG. 7
`
`,
`
`,
`
`,
`
`I
`
`5e
`
`Sd
`
`Sc
`
`...
`~
`~ = """'"
`
`\C
`
`s,
`CI:l =-a
`
`!.It
`
`I
`
`~
`\C
`I-"
`
`,.,......:1
`I-"
`
`f4.
`o
`
`So
`
`LATCH
`,
`1~71
`ADD
`1-BIT
`
`;V IV
`
`LATCH ?
`i 1 69
`ADD -
`
`I-BIT
`
`ft6~
`
`~
`
`f---4o
`
`LATCH
`i 16~
`ADD
`I-BIT
`
`fi65
`
`LATCH
`
`1 1 /!t63
`
`ADD
`l-BIT
`
`/\162
`
`-
`
`-
`
`-
`
`~
`~
`•
`00
`d •
`
`RTL345-1_1025-0006
`
`

`
`u.s. Patent
`US. Patent
`
`Oct. 17, 1995
`Oct. 17, 1995
`
`Sheet 6 of 9
`Sheet 6 of 9
`
`5,459,683
`5,459,683
`
`FIG. 8
`F/G. 8
`
`1
`0
`
`0
`0
`
`1
`1
`
`0
`1
`
`1
`1
`
`0
`
`0
`0
`
`0
`0
`
`I
`
`III
`
`0
`
`0
`
`0
`
`r ll roll
`
`
`
`Ill‘ lil
`
`SIGNAL Sa
`SIGNAL Sa
`SIGNAL Sb
`SIGNAL Sb
`
`EX-OR 23
`EX-OR 23
`
`LATCH 24
`LATCH 24
`
`ADDER 26
`ADDER 26
`
`LATCH 27
`LATCH 27
`
`0 0 0 1 1
`
`1
`
`1
`
`0
`
`ADDER 28
`ADDER 28
`
`LATCH 29
`LATCH 29
`
`1 1 1 1
`
`1
`
`0
`
`0
`
`0 0
`
`MUL TIPLEXER 30
`HULTIPLEXER 30
`
`EX-OR 31
`EX-OR 31
`
`~
`
`TIME
`
`FIG. 9
`FIG. 9
`SIGNAL
`SIGNAL
`SIGNAL
`Sa
`Sb
`Sb
`0;
`o~
`O~
`0
`O;
`S
`O~
`o~
`NEGATIVE
`NEGATIVE
`O S
`O~
`NEGATIVE
`NEGATIVE
`0;
`o~
`NEGATIVE
`NEGATIVE
`02
`O~
`NEGATIVE
`NEGATIVE
`0 S
`O~
`NEGATIVE NEGATIVE
`' NEGATIVE NEGATIVE
`NEGATIVE NEGATIVE
`NEGATIVE NEGATIVE
`
`RELATION BETWEEN MULTIPLEXER
`RELATION BETWEEN
`NULTIPLEXER
`OUTPUT
`Sa AND Sb
`Sa AND Sb
`OUTPUT
`0
`ISal~ISbl
`ISal<ISbl
`1
`0
`ISa/~/Sbl
`ISal<ISbl
`1
`ISal>ISbl
`1
`0
`/Sa/~ISbl
`ISa/>/Sb/
`1
`0
`/Sa/~/Sb/
`
`RTL345-1_1025-0007
`
`

`
`u.s. Patent
`
`Oct. 17, 1995
`
`Sheet 7 of 9
`
`5,459,683
`
`FIG. 10
`
`RELATION BETWEEN
`Sa AND Sb
`ISal~ISbl
`ISal<ISbl
`ISal~ISbl
`ISal<ISbl
`ISal>ISbl
`ISal~ISbl
`ISal>ISb/
`ISal~ISbl
`
`SIGNAL Sc
`0
`1
`0
`1
`0
`1
`0
`1
`
`SIGNAL
`Sb
`O~
`
`SIGNAL
`Sa
`O~
`
`O~
`
`O~
`
`O~
`NEGATIVE
`NEGATIVE
`O~
`
`O~
`NEGATIVE
`NEGATIVE
`O~
`NEGATIVE NEGATIVE
`NEGATIVE NEGATIVE
`
`.
`
`I
`
`.
`
`I
`
`I
`
`SIGNAL Sa
`
`FIG. 11
`.
`.
`
`I
`
`I
`
`,
`I
`
`SHIFT REGISTER ~--H---!l-+'---"!I-~~---!,.-...o...,..-1-i--+----i--!--~-
`34A
`
`I
`I
`I
`
`I
`I
`I
`
`I
`I
`I
`
`LATCH 35A
`
`EX-OR 36A
`
`LATCH 37A
`
`SIGNAL Sd
`
`I
`I
`
`-
`
`1
`
`-
`
`I
`I
`I
`
`:0
`0:
`
`!O
`
`..
`
`TIME
`
`RTL345-1_1025-0008
`
`

`
`u.s. Patent
`US. Patent
`
`Oct. 17, 1995
`Oct. 17, 1995
`
`Sheet 8 of 9
`Sheet 8 of 9
`
`5,459,683
`5,459,683
`
`FIG. 12
`FIG. 72
`
`SIGNAL Sc
`
`1
`
`SIGNAL Sd
`
`1 0 1 0 0
`
`SIGNAL Se
`
`0 1 1 1 0
`
`MULTIPLEXER 43
`MULTIPLEXER 43
`
`MULTIPLEXER 44?; 15 0
`MULTIPLEXER 44
`
`SIGNAL Sg
`
`SIGNAL Sh
`
`SIGNAL Si
`
`SIGNAL Sj
`
`SIGNAL Sk
`
`0
`
`1| 0
`0
`
`1. 1| 0
`
`0
`
`0
`
`0
`
`0
`
`o 0 0 0
`
`0 1| 1
`
`0
`
`ADDER 62
`ADDER 62
`
`0
`
`ADDER 65
`ADOER 65
`
`ADDER 68
`ADDER 68
`
`'0
`
`0
`
`ADDER 70
`ADDER 70
`
`0
`
`III
`
`0
`
`o O 0 4|
`
`1: ..|| ||: |.... 5... 531:7: |..|
`
`
`
`1 0 0
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`TIME
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`
`RTL345-1_1025-0009
`
`

`
`u.s. Patent
`US. Patent
`
`Oct. 17, 1995
`Oct. 17, 1995
`
`Sheet 9 of 9
`Sheet 9 0f 9
`
`5,459,683
`5,459,683
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`RTL345-1_1025-0010
`
`

`
`5,459,683
`5,459,683
`
`1
`1
`APPARATUS FOR CALCULATING THE
`APPARATUS FOR CALCULATING THE
`SQUARE ROOT OF THE SUM OF TWO
`SQUARE mm or THE SUM OF Two
`SQUARES
`SQUARES
`
`BACKGROUND OF THE INVENTION
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`1. Field of the Invention
`This invention relates to an apparatus for calculating the
`This invention relates to an apparatus for calculating the
`square root of the sum of the square of the value represented
`square root of the sum ofthe square of the value represented
`by a ?rst digital signal and the square of the value repre
`by a first digital signal and the square of the value repre(cid:173)
`sented by a second digital signal.
`sented by a second digital signal.
`2. Description of the Prior Art
`2. Description of the Prior Art
`In digital signal processing, some calculations are
`In digital signal processing, some calculations are
`intended to derive the square root So of the sum of the square
`intended to derive the square root So of the sum of the square
`of a ?rst value represented by a ?rst digital signal and the
`of a first value represented by a first digital signal and the
`square of a second value represented by a second digital
`square of a second value represented by a second digital
`signal. Speci?cally, the square root So is expressed as S0:
`signal. Specifically, the square root So is expressed as So=
`= A2+B2 where "A" denotes the value represented by the 20
`: A2+B2 where “A” denotes the value represented by the
`?rst digital signal and “B” denotes the value represented by
`first digital signal and "B" denotes the value represented by
`the second digital signal.
`the second digital signal.
`As will be described later, prior-art apparatuses for such
`As will be described later, prior-art apparatuses for such
`calculations tend to be complicated in structure.
`calculations tend to be complicated in structure.
`
`15
`
`SUMMARY OF THE INVENTION
`SUMMARY OF THE INVENTION
`
`2
`2
`l-bit adder for adding an output signal from the Exclusive
`I-bit adder for adding an output signal from the Exclusive(cid:173)
`OR circuit and an output signal from the second latch, and
`OR circuit and an output signal from the second latch, and
`generating the fourth digital signal; wherein the second latch
`generating the fourth digital signal; wherein the second latch
`is operative for latching a carry signal generated by the
`is operative for latching a carry signal generated by the
`5 adder.
`adder.
`It is preferable that the third means comprises a first
`It is preferable that the third means comprises a ?rst
`Exclusive-OR circuit for executing Exclusive-OR operation
`Exclusive-OR circuit for executing Exclusive-OR operation
`between the ?rst digital signal and the third digital signal; a
`between the first digital signal and the third digital signal; a
`first latch for latching an output signal from the first Exclu-
`?rst latch for latching an output signal from the ?rst Exclu
`10
`10 sive-OR circuit; an inverter for inverting the third digital
`sive-OR circuit; an inverter for inverting the third digital
`signal; a ?rst l-bit adder for adding the ?rst digital signal
`signal; a first I-bit adder for adding the first digital signal
`and the second digital signal; a second latch for latching a
`and the second digital signal; a second latch for latching a
`carry signal generated by the ?rst adder; a second l-bit adder
`carry signal generated by the first adder; a second I-bit adder
`for adding the ?rst digital signal an output signal from the
`for adding the first digital signal an output signal from the
`inverter; a third latch for latching a carry signal generated by
`inverter; a third latch for latching a carry signal generated by
`the second adder; a multiplexer for selecting one of an
`the second adder; a multiplexer for selecting one of an
`output signal from the ?rst adder and an output signal from
`output signal from the first adder and an output signal from
`the second adder in response to an output signal from the
`the second adder in response to an output signal from the
`first latch; and a second Exclusive-OR circuit for executing
`?rst latch; and a second Exclusive-OR circuit for executing
`Exclusive-OR operation between the ?rst digital signal and
`Exclusive-OR operation between the first digital signal and
`an output signal from the multiplexer, and for generating the
`an output signal from the mUltiplexer, and for generating the
`comparison-result signal in response to the ?rst digital signal
`comparison-result signal in response to the first digital signal
`and the output signal from the multiplexer.
`and the output signal from the multiplexer.
`It is preferable that the fourth means comprises a first
`It is preferable that the fourth means comprises a ?rst
`25
`multiplexer for selecting one of the second digital signal and
`25 multiplexer for selecting one of the second digital signal and
`the fourth digital signal in response to the comparison-result
`the fourth digital signal in response to the comparison-result
`signal; a second multiplexer for selecting one of the second
`signal; a second multiplexer for selecting one of the second
`digital signal and the fourth digital signal in response to the
`digital signal and the fourth digital signal in response to the
`comparison-result signal; a ?rst series combination of ?ip
`comparison-result signal; a first series combination of fiip-
`30
`?ops successively storing an output signal from the ?rst
`30 flops successively storing an output signal from the first
`multiplexer; a second series combination of flip-flops suc(cid:173)
`multiplexer; a second series combination of ?ip-?ops suc
`cessively storing an output signal from the second multi
`cessively storing an output signal from the second multi(cid:173)
`plexer; a first I-bit adder for adding am output signal from
`plexer; a ?rst l-bit adder for adding am output signal from
`the ?rst combination of the ?ip-?ops and the output signal
`the first combination of the flip-flops and the output signal
`from the second multiplexer; a first latch for latching a carry
`from the second multiplexer; a ?rst latch for latching a carry
`signal generated by the first adder; a second I-bit adder for
`signal generated by the ?rst adder; a second l-bit adder for
`adding output signals from given ?ip-?ops in the second
`adding output signals from given flip-flops in the second
`combination; a second latch for latching a carry signal
`combination; a second latch for latching a carry signal
`generated by the second adder; a third I-bit adder for adding
`generated by the second adder; a third l-bit adder for adding
`40 an output signal from the second combination of the fiip-
`an output signal from the second combination of the flip
`flops and an output signal from the second adder; a third
`?ops and an output signal from the second adder; a third
`latch for latching a carry signal generated by the third adder;
`latch for latching a carry signal generated by the third adder;
`a fourth I-bit adder for adding an output signal from the first
`a fourth l-bit adder for adding an output signal from the ?rst
`adder and an output signal from the third adder; and a fourth
`adder and an output signal from the third adder; and a fourth
`latch for latching a carry signal generated by the fourth
`latch for latching a carry signal generated by the fourth
`adder.
`adder.
`
`35
`35
`
`45
`45
`
`It is an object of this invention to provide an improved
`It is an object of this invention to provide an improved
`calculation apparatus.
`calculation apparatus.
`This invention provides a calculation apparatus compris
`This invention provides a calculation apparatus compris(cid:173)
`ing ?rst means for processing a ?rst digital signal of a serial
`ing first means for processing a first digital signal of a serial
`form into a second digital signal of a serial form, the second
`form into a second digital signal of a serial form, the second
`digital signal representing an absolute value of a value
`digital signal representing an absolute value of a value
`represented by the ?rst digital signal; second means for
`represented by the first digital signal; second means for
`processing a third digital signal of a serial form into a fourth
`processing a third digital signal of a serial form into a fourth
`digital signal of a serial form, the fourth digital signal
`digital signal of a serial form, the fourth digital signal
`representing an absolute value of a value represented by the
`representing an absolute value of a value represented by the
`third digital signal; third means for comparing the values
`third digital signal; third means for comparing the values
`represented by the ?rst and third digital signals, and gener
`represented by the first and third digital signals, and gener(cid:173)
`ating a comparison-result digital signal representing a result
`ating a comparison-result digital signal representing a result
`of said comparing; and fourth means for generating a
`of said comparing; and fourth means for generating a
`calculation-result digital signal of a serial form in response
`calculation-result digital signal of a serial form in response
`to the second digital signal, the fourth digital signal, and the
`to the second digital signal, the fourth digital signal, and the
`comparison-result digital signal, the calculation-result digi
`comparison-result digital signal, the calculation-result digi(cid:173)
`tal signal representing a value which is approximate to a
`tal signal representing a value which is approximate to a
`square root of a sum of a square of the value represented by
`square root of a sum of a square of the value represented by
`the ?rst digital signal and a square of the value represented
`the first digital signal and a square of the value represented
`by the third digital signal.
`by the third digital signal.
`It is preferable that the first means comprises a shift
`It is preferable that the ?rst means comprises a shift
`register for temporarily storing the ?rst digital signal; a ?rst
`register for temporarily storing the first digital signal; a first 50
`50
`latch for latching an MSB of the ?rst digital signal; an
`latch for latching an MSB of the first digital signal; an
`Exclusive-OR circuit for executing Exclusive-OR operation
`Exclusive-OR circuit for executing Exclusive-OR operation
`between an output signal from the shift register and an
`between an output signal from the shift register and an
`output signal from the ?rst latch; a second latch for latching
`output signal from the first latch; a second latch for latching
`the MSB of the ?rst digital signal as an initial value; and a
`the MSB of the first digital signal as an initial value; and a 55
`55
`l-bit adder for adding an output signal from the Exclusive
`I-bit adder for adding an output signal from the Exclusive(cid:173)
`OR circuit and an output signal from the second latch, and
`OR circuit and an output signal from the second latch, and
`generating the second digital signal; wherein the second
`generating the second digital signal; wherein the second
`latch is operative for latching a carry signal generated by the
`latch is operative for latching a carry signal generated by the
`adder.
`adder.
`It is preferable that the second means comprises a shift
`It is preferable that the second means comprises a shift
`register for temporarily storing the third digital signal; a ?rst
`register for temporarily storing the third digital signal; a first
`latch for latching an MSB of the third digital signal; an
`latch for latching an MSB of the third digital signal; an
`Exclusive-OR circuit for executing Exclusive-OR operation
`Exclusive-OR circuit for executing Exclusive-OR operation
`between an output signal from the shift register and an 65
`between an output signal from the shift register and an
`65
`output signal from the ?rst latch; a second latch for latching
`output signal from the first latch; a second latch for latching
`the MSB of the third digital signal as an initial value; and a
`the MSB of the third digital signal as an initial value; and a
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a first prior-art calculation
`FIG. 1 is a block diagram of a ?rst prior-art calculation
`apparatus.
`apparatus.
`FIG. 2 is a block diagram of a second prior-art calculation
`FIG. 2 is a block diagram of a second prior-art calculation
`apparatus.
`apparatus.
`FIG. 3 is a block diagram of an approximate calculation
`FIG. 3 is a block diagram of an approximate calculation
`apparatus.
`apparatus.
`FIG. 4 is a block diagram of a calculation apparatus
`FIG. 4 is a block diagram of a calculation apparatus
`according to a first embodiment of this invention.
`according to a ?rst embodiment of this invention.
`FIG. 5 is a block diagram of an absolute-value comparator
`FIG. 5 is a block diagram of an absolute-value comparator
`in FIG. 4.
`in FIG. 4.
`FIG. 6 is a block diagram of an absolute-value calculator
`FIG. 6 is a block diagram of an absolute-value calculator
`in FIG. 4.
`in FIG. 4.
`FIG. 7 is a block diagram of a multiplier in FIG. 4.
`FIG. 7 is a block diagram of a multiplier in FIG. 4.
`FIG. 8 is a time-domain diagram of various signals in the
`FIG. 8 is a time-domain diagram of various signals in the
`absolute-value comparator of FIG. 5.
`absolute-value comparator of FIG. 5.
`FIG. 9 is a diagram of the relation among the values
`FIG. 9 is a diagram of the relation among the values
`
`60
`
`RTL345-1_1025-0011
`
`

`
`5,459,683
`5,459,683
`
`3
`3
`represented by input digital signals Sa and Sb, and the logic
`represented by input digital signals Sa and Sb, and the logic
`state of the output signal from a multiplexer 30 in the
`state of the output signal from a multiplexer 30 in the
`absolute-value comparator of FIG. 5.
`absolute-value comparator of FIG. 5.
`FIG. 10 is a diagram of the relation among the values
`FIG. 10 is a diagram of the relation among the values
`represented by the input digital signals Sa and Sb, and the
`represented by the input digital signals Sa and Sb, and the 5
`logic state of the output signal Sc from an Exclusive-OR
`logic state of the output signal Sc from an Exclusive-OR
`circuit 31 in the absolute-value comparator of FIG. 5.
`circuit 31 in the absolute-value comparator of FIG. 5.
`FIG. 11 is a time-domain diagram of various signals in the
`FIG. 11 is a time-domain diagram of various signals in the
`absolute-value calculator of FIG. 6.
`absolute-value calculator of FIG. 6.
`FIG. 12 is a time-domain diagram of various signals in the
`FIG. 12 is a time-domain diagram of various signals in the
`multiplier of FIG. 7.
`multiplier of FIG. 7.
`FIG. 13 is a block diagram of a calculation apparatus
`FIG. 13 is a block diagram of a calculation apparatus
`according to a second embodiment of this invention.
`according to a second embodiment of this invention.
`
`DESCRIPTION OF THE PREFERRED
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`EMBODIMENTS
`
`4
`4
`square "Sb2
`square “8b” of the value represented by the digital signal Sb
`" of the value represented by the digital signal Sb
`and outputs an M-bit digital signal indicating the calculated
`and outputs an M-bit digital signal indicating the calculated
`square "Sb2
`". In this case, the adder 9 receives the output
`square “Sb2”. In this case, the adder 9 receives the output
`signal from the multiplier 7 which represents the calculated
`signal from the multiplier 7 which represents the calculated
`square "Sb2
`". At the same time, the adder 9 receives the
`square “Sb2”. At the same time, the adder 9 receives the
`output signal from the latch 8 which represents the calcu(cid:173)
`output signal from the latch 8 which represents the calcu
`lated square "Sa2
`lated square “Sa2”.
`".
`The adder 9 calculates the sum "Sa2+Sb2
`" of the values
`The adder 9 calculates the sum “Sa2+Sb2” of the values
`"Sa2 " and "Sb2
`" represented by the output signals from the
`“8a” and “8b” represented by the output signals from the
`10 multiplier 7 and the latch 8. The adder 9 outputs an (M+l)(cid:173)
`multiplier 7 and the latch 8. The adder 9 outputs an (M+l)
`10
`bit digital signal indicating the calculated sum "Sa2+Sb2
`bit digital signal indicating the calculated sum “Sa2+Sb2”.
`".
`The square root calculator 10 receives the output signal
`The square root calculator 10 receives the output signal
`the square root
`from ~dder 9, and calculates
`from the adder 9, and calculates the square root
`"= Sa2+Sb2
`" of the value "Sa2+Sb2
`“= Sa2+Sb2” of the value “Sa2+Sb2” represented by the
`" represented by the
`15 output signal from the adder 9. The square root calculator 10
`output signal from the adder 9. The square root calculator 10
`outputs a digital signal So indicating the calculated square
`outputs a digital signal So indicating the calculated square
`root “= Sa2+Sb2”.
`FIG. 3 shows an approximate calculation apparatus which
`FIG. 3 shows an approximate calculation apparatus which
`is not prior art against this invention. As shown in FIG. 3, the
`is not prior art against this invention. As shown in FIG. 3, the
`approximate calculation apparatus includes N-bit absolute
`approximate calculation apparatus includes N-bit absolute(cid:173)
`value calculators 11 and 12, an N-bit subtracter 13, N-bit
`value calculators 11 and 12, an N-bit subtracter 13, N-bit
`multiplexers 14 and 15, an N-bit multiplier 16, and an M-bit
`multiplexers 14 and 15, an N-bit multiplier 16, and an M-bit
`adder 17, where "N" and "M" denote given natural numbers
`adder 17, where “N” and “M” denote given natural numbers
`respectively.
`25 respectively.
`25
`The approximate calculation apparatus of FIG. 3 is
`The approximate calculation apparatus of FIG. 3 is
`designed to operate on input N-bit digital signals Sa and Sb
`designed to operate on input N-bit digital signals Sa and Sb
`of a parallel form which represent an in-phase component
`of a parallel form which represent an in-phase component
`and a quadrature component of a constant-envelope analog
`and a quadrature component of a constant-envelope analog
`signal respectively. In this case, the square root of the sum
`signal respectively. In this case, the square root of the sum
`of the square of the value “A” represented by the digital
`of the square of the value "A" represented by the digital
`signal Sa and the square of the value “B” represented by the
`signal Sa and the square ofthe value "B" represented by the
`digital signal Sb is approximately given by the following
`digital signal Sb is approximately given by the following
`equation.
`equation.
`
`20
`20
`
`Prior-art calculation apparatuses will now be described
`Prior-art calculation apparatuses will now be described
`for a better understanding of this invention.
`for a better understanding of this invention.
`FIG. 1 shows a ?rst prior-art calculation apparatus. As
`FIG. 1 shows a first prior-art calculation apparatus. As
`shown in FIG. 1, the ?rst prior-art calculation apparatus
`shown in FIG. 1, the first prior-art calculation apparatus
`includes N~bit multipliers 2 and 3, an M-bit adder 4, and a
`includes N-bit multipliers 2 and 3, an M-bit adder 4, and a
`square root calculator 5, where “N” and “M” denote given
`square root calculator 5, where "N" and "M" denote given
`natural numbers respectively.
`natural numbers respectively.
`An input N-bit digital signal Sa having a parallel form is
`An input N-bit digital signal Sa having a parallel form is