ASML’s customer magazine | 2014
`
`A faster route
`to better overlay
`
`Product lifecycle management:
`added-value across the industry
`
`Focus on a new star
`
`Energetiq Ex. 2005, page 1 - IPR2015-01362
`
`

`
`6
`
`10
`
`16
`
`4 A faster route to better overlay
`
`images | Colofon
`
`6
`
`EUV shows consistent performance
`in the field
`
`Editorial Board
`
`© 2014, ASML Holding BV
`
`ASML, ASM Lithography, TWINSCAN, PAS 5500,
`
`PAS 5000, SA 5200, ATHENA, QUASAR, IRIS, ILIAS,
`
`Lucas van Grinsven, Peter Jenkins
`
`FOCAL, Micralign, Micrascan, 3DAlign, 2DStitching,
`
`10 Product lifecycle management:
`added-value across the industry
`
`Managing Editor
`
`Michael Pullen
`
`12 New nodes with your installed
`TWINSCAN NXTs
`
`Contributing Editor
`
`Saskia Boeije
`
`16 Focus on a new star
`
`Contributing Writers
`
`3DMetrology, Brion Technologies, LithoServer,
`
`LithoGuide, Scattering Bars, LithoCruiser, Tachyon
`
`2.0, Tachyon RDI, Tachyon LMC, Tachyon OPC+,
`
`LithoCool, AGILE, ImageTuner, EFESE, Feature Scan,
`
`T-ReCS and the ASML logo are trademarks of ASML
`
`Holding N.V. or of affiliate companies. The trademarks
`
`may be used either alone or in combination with
`
`a further product designation. Starlith, AERIAL,
`
`Paul Tuffy, Jan-Willem van der Horst,
`
`and AERIAL II are trademarks of Carl Zeiss. TEL is
`
`Thomas van Wezel, Jules Tops,
`
`a trademark of Tokyo Electron Limited. Sun, Sun
`
`Janneke van Heteren, Remi Pieternella,
`
`Microsystems, the Sun Logo, iForce, Solaris, and the
`
`Stuart Young
`
`Circulation
`
`Java logo are trademarks or registered trademarks of
`
`Sun Microsystems, Inc. in the United States and other
`
`countries. Bayon is a trademark of Kureha Chemical
`
`Karen Lo, Michael Pullen, Saskia Boeije
`
`Industry Co. Ltd. Nothing in this publication is intended
`
`For more information, please see:
`
`trademark is registered or to suggest that any sign
`
`www.asml.com/images
`
`other than those mentioned should not be considered
`
`to make representations with regard to whether any
`
`to be a trademark of ASML or of any third party.
`
`ASML lithography systems are Class 1 laser products.
`
`2
`
`Energetiq Ex. 2005, page 2 - IPR2015-01362
`
`

`
`Editor’s note
`
`30 years down,
`30 plus to go
`
`By Michael Pullen, Senior Communications Specialist
`
`Last, but not least, you will read about
`the latest YieldStar system, the 250D.
`It is the first metrology system capable
`of measuring overlay, focus and CD
`in a production environment, helping
`customers maximize their yields of good
`wafers-per-day.
`
`I hope you find this issue informative
`and of value. Please feel free to
`provide direct feedback to me at
`michael.pullen@asml.com so that we
`can continue to improve the magazine
`and your experience.
`
`Happy reading!
`Mike
`
`As 2014 comes to a close and we look
`back on our 30 year history of providing
`lithography solutions for the ever growing
`and changing semiconductor industry,
`it is amazing to see the challenges
`that we have overcome, and the
`accomplishments that we have made,
`together as an industry. As we look to
`coming years, there are obvious hurdles
`and roadblocks that we must overcome
`to continue down the path set forth by
`Moore’s Law.
`
`In this issue of Images Magazine,
`we will take a look at how we, at ASML,
`are preparing to clear those hurdles and
`continue down the path for another
`30 plus years.
`
`Going back nearly to our start in 1984,
`the PAS 2500/5000 is still in use today
`at several customers. While its End
`of Service is approaching, the Mature
`Products Service team is redefining
`the life cycle of all ASML products and
`mapping out four major lifecycle stages
`that will increase transparency with
`customers and help them improve their
`own business planning in the future.
`
`You will hear how ASML’s new Design
`for Control (D4C) Overlay software
`is tackling the current industry
`requirements for overlay, focus control
`and critical dimension uniformity (CDU)
`and will meet the future demands by
`allowing customers to design and
`optimize metrology targets that can be
`used to deliver significant improvements
`to overlay performance.
`
`Another hurdle you will read about is
`the cost ineffectiveness of transitioning
`from node to node and how ASML’s
`System Node Extension Packages
`(SNEPs) are breaking through this by
`converting any TWINSCAN NXT system
`to a newer model in the field, effectively
`extending its capabilities another one or
`two production nodes.
`
`As you may have read recently, our EUV
`tools are meeting and exceeding the 500
`wafer per day barrier, with one machine
`at IBM exposing 637 EUV wafers in a
`single day! Additional advancements
`and improvements are being made to
`source power, availability and particle
`contamination.
`
`3
`
`ASML Images, 2014
`
`Energetiq Ex. 2005, page 3 - IPR2015-01362
`
`

`
`A faster route
`to better overlay
`
`By Paul Tuffy, Product Manager BRION Wafer Fab Applications
`
`Abstract | ASML’s new Design for Control
`Overlay software identifies the best
`metrology target design for any given layer
`combination and process in the shortest
`time. It allows customers to design and
`optimize metrology targets that deliver
`the ideal balance of printability, detectability,
`accuracy and device matching. These targets
`can be used in an automated feedback
`loop to deliver significant improvements to
`on-product overlay performance.
`
`4
`
`Fast, precise and accurate, ASML’s
`YieldStar diffraction-based metrology tool
`has made it possible to continually monitor
`on-product overlay performance and
`provide faster feedback to the scanner.
`This is done through a feedback loop
`where overlay data from an in-track
`YieldStar module is converted into
`smart exposure corrections by system
`enhancement packages like Litho Insight.
`These corrections are fed back to the
`scanner for subsequent wafers, resulting in
`improved on-product overlay performance.
`
`These overlay measurements are based
`on grating targets included in the reticle
`designs for the many overlay-sensitive
`layer combinations in a product. The design
`of these targets needs to fulfill certain
`performance requirements. It must print
`well across the process window, and
`deliver an easily detectable diffraction
`signal to ensure precision and short
`measurement times. It also needs to
`help ensure the measurements are
`accurate and not affected by variability
`in processing steps such as etching and
`chemical mechanical planarization (CMP).
`
`As design features shrink, more and more
`overlay targets are needed to capture
`the overlay fingerprint at the required
`level of detail. At the same time, placing
`targets within the actual device becomes
`advantageous as it allows more accurate
`and higher-order corrections. This in-die
`placement is only feasible with very small
`targets, making it important to optimize
`
`the target design for a strong diffraction
`signal. Moreover, the increased use of
`opaque materials in the latest technology
`process stacks – such as the sacrificial
`layers used in spacer processes – make
`target optimization for signal strength
`doubly important.
`
`Identify the best
`
`target designs in the
`
`shortest time
`
`Design for Control
`ASML’s new Design for Control Overlay
`(D4C Overlay) software package helps
`semiconductor manufacturers identify
`the best metrology target designs in the
`shortest time. It does this by simulating
`the lithography process and resulting
`YieldStar measurements of candidate
`targets including the full layer stack,
`allowing the design parameters of the
`target for a given layer to be optimized.
`
`D4C Overlay transforms target
`optimization from a lengthy trial-and-
`error process to a quick and reliable
`computational one. It avoids the need
`to carry out repeated wafer experiments
`on different test designs – significantly
`speeding up process development.
`And it allows users to try out thousands
`more targets and fully explore the design
`space – enabling the development of
`
`Energetiq Ex. 2005, page 4 - IPR2015-01362
`
`

`
`the final target design in a single reticle
`tape out cycle.
`
`By identifying targets that balance
`precision and accuracy, D4C Overlay
`helps deliver significantly better on-
`product overlay performance. What’s
`more, it can match the aberration
`sensitivity of the target to that of the
`critical device features being printed in
`the specified layer, enabling further
`overlay gains. (See Fig. 1)
`
`Tailor-made targets
`Design for Control Overlay is a complete
`target optimization software package.
`Its easy-to-use graphical user interface
`guides the user through the target design
`process step by step. This includes a
`flexible interface for defining the process
`stack in the same way as it is built in the
`fab: adding etch, deposition, CMP and
`patterning steps to build each layer.
`This approach allows almost any stack
`design to be simulated. (See Fig. 2)
`
`Once the user has specified the process
`design rules and constraints, the software
`runs an initial simulation to identify target
`candidates that meet the printability
`and detectability specifications.
`The detectability, overlay accuracy
`and lens aberration performance of
`these candidates are then tested in a
`further round of simulations.
`
`An extensive set of built-in analysis features
`including 2D heat maps and 3D amplitudes
`simplifies the selection of optimal targets.
`Once the user has chosen a number of best
`candidates for experimental validation,
`the D4C Overlay software outputs the
`complete reticle pattern for that layer in
`the GDS format. (See Fig. 3)
`
`In-house design and optimization
`D4C Overlay runs on any fab server
`cluster using the Tachyon Flex platform.
`We offer extensive training and detailed
`user manuals on how to get the best
`from the package. This allows companies
`to keep target design and optimization
`completely in house.
`
`D4C Overlay was initially released in
`late 2013 in a version that focused on
`
`Design for Control Overlay optimizes YieldStar overlay
`targets for best on-product overlay performance
`
`Printability
`• Mask optimization
`• Litho process window
`• Design rule compatibility
`
`Detectability
`• Target selection to meet TMU/
` MAM requirements
`• Including process variations
` for detectability robustness
`
`D4C
`
`Accuracy: Device matching
`device
`target
`• Improved overlay due
` to improved aberration
` sensitivity matching
` (target to device)
`
`Accuracy: Process robustness
`• Target selection for
` robust and accurate
` overlay with lowest
` sensitivity to process
` induced asymmetry
`
`∆SWA
`
`D4C Overlay Target Design Flow
`
`Input
`
`YieldStar detectability
`
`Detectability robustness
`
`Design
`input
`(process flow)
`
`Simulate
`detectability KPIs
`@ nominal
`
`Simulate detectability
`robustness KPIs
`
`Simultation
`settings
`(YS & target
`patterns)
`
`Litho
`
`model
`(Tachyon
`FEM+)
`
`Filter out targets
`with poor detectability
`and printability
`
`Optional
`
`Litho Printability
`
`Simulate
`printability KPIs
`
`Overlay robustness
`
`Target selection
`
`Simulate overlay
`robustness KPIs
`
`Select targets based
`on weighed KPIs
`
`Aberration matching
`
`Simulate aberration
`sensitivity KPIs
`
`Fig. 1
`
`Fig. 2
`
`Fig. 3
`
`target printability and detectability.
`The full version including overlay
`accuracy was launched in Q3 2014.
`It is designed for use with ASML’s
`TWINSCAN NXT immersion ArF and
`NXE extreme ultraviolet scanners in
`conjunction with YieldStar YS 200C or
`YS 250D metrology tools and Litho Insight
`overlay optimization software.
`
`Together these systems deliver a
`holistic solution to the current industry
`requirements for 5 nm overlay,
`60 nm focus control and 1.6 nm CDU
`(after etch). Planned enhancements to
`all these products will support roadmaps
`towards 2017 that demand 2.5 nm overlay,
`50 nm focus control and 1.1 nm CDU
`(after etch).
`
`5
`
`ASML Images, 2014
`
`Energetiq Ex. 2005, page 5 - IPR2015-01362
`
`

`
`EUV shows consistent
`performance in the field
`
`By Jan-Willem van der Horst, Product Manager EUV
`
`Abstract | ASML has qualified and shipped
`six TWINSCAN NXE:3300B extreme
`ultraviolet (EUV) lithography scanners.
`With multiple systems exposing wafers
`at customer sites, the NXE:3300B
`is demonstrating consistently good
`performance. Meanwhile, enhancements
`to source power and availability are driving
`productivity gains. In addition, a joint
`research program with customers and
`materials suppliers is exploring a pellicle
`concept to protect EUV masks from
`particle contamination, and hence reduce
`printed defect levels.
`
`EUV lithography is making continued
`progress towards maturity and production
`insertion. Systems at customer sites are
`delivering consistent performance fit for
`development of 10 nm logic and sub-20 nm
`DRAM products. Productivity levels are
`up – leading to a record number of EUV
`wafer exposures in a day.
`
`The TWINSCAN NXE:3300B is our
`third-generation EUV lithography system,
`with a resolution specification of 22 nm.
`Six of these systems have been qualified at
`our facility in Veldhoven, the Netherlands
`and shipped to customer sites. A further
`five are currently going through the
`qualification process.
`
`Excellence as standard
`These installed systems demonstrate
`that the NXE:3300B’s excellent imaging
`performance is repeated across multiple
`systems. In fact, the systems in the field
`often achieve performance levels in excess
`of specifications – for example printing
`16 nm dense lines with large process
`windows. Full wafer focus uniformity
`better than 12 nm is common, as is critical
`dimension uniformity (CDU) below 1.5 nm.
`
`Excellent imaging
`
`performance is repeated
`
`across multiple systems
`
`6
`
`Energetiq Ex. 2005, page 6 - IPR2015-01362
`
`

`
`ASML Images, 2014
`
`X - axis
`Y - axis
`
`Systems feature the
`
`new MOPA-PP source
`
`confi guration running
`
`at 40 W
`
`Overlay performance too is consistently
`excellent. The six installed systems exhibit
`matched machine overlay (MMO) with
`our immersion scanners of around 5 nm
`or better. And full-wafer dedicated chuck
`overlay (DCO) below 1.4 nm has been
`achieved. (See Fig. 1)
`
`Customers had already shown that the
`NXE:3300B is capable of printing real
`devices structures for the 10-nm logic
`node with an extended depth of focus
`(DoF). Now by combining the scanner’s
`off-axis illumination (OAI) capabilities
`with ASML-Brion’s advanced optical
`proximity correction (OPC), they have
`reproduced those results at much lower
`doses. For example, customers have
`printed 10-nm logic metal 1 layers with a
`120 nm DoF at a dose of around 20 mJ/cm2
`– both fi gures are within requirements for
`high-volume production. (See Fig. 2)
`
`Pushing up productivity
`The six installed NXE:3300B systems
`feature the new master oscillator
`power amplifi er pre-pulse (MOPA-PP)
`
`7
`
`Lot (3.2,3.0)
`
`
`
`1
`
`2
`
`3
`4
`5
`6
`Wafer – after std modelling
`corrected using standard scanner model
`
`7
`
`8
`
`6
`
`4.5
`
`3
`
`1.5
`
`0
`
`Matched machine overlay [nm]
`
`Fig. 1: MMO performance for various machines
`
`Logic 10nm Metal 1 layer: Wide Depth of Focus at 20 mJ/cm2
`
`Quasar illumination¬
`Dose ~20 mJ/cm2¬NXE OPC+
`
`-80nm
`-60nm
`-40nm
`-20nm
`0nm
`20nm
`40nm
`60nm
`80nm
`
`FOCUS: DoF 120nm
`FOCUS: DoF 120nm
`
`NXE:3300B, 10 nm logic
`Metal 1 layer, 45 nm pitch.
`
`Clips courtesy of STMicroelectronics
`
`Fig. 2: 10-nm logic metal 1 layer
`
`Energetiq Ex. 2005, page 7 - IPR2015-01362
`
`

`
`Field collector cleaned
`in NXE:3300 source
`vessel test rig
`
`In-situ collector cleaning¬
`Effectiveness of product configuration confirmed
`
`Start
`
`End
`
`Reflectivity Al-05 (unpolarized)
`
`After cleaning
`Brand new
`
`
`
`55
`50
`45
`40
`35
`30
`25
`20
`15
`10
`
`05
`
`Reflectivity,%
`
`50
`
`100
`
`150
`200
`250
`Substrate radius, mm
`
`300 350
`
`Start
`
`End
`
`Reflectivity restored within 0.8% of original Cleaning
`in off-line MOPA Prepulse development vessel
`
`Off-line cleaning using NXE:3300B source vessel
`with product configuration hardware
`
`Full-size EUV pellicle prototype manufactured
`
`Pellicle
`
`Absorber pattern
`
`Mask
`
`Pellicle transmission
`requirement: 90%
`Current status: ~86%
`
`µm-size particles
`do not aff ect imaging
`
`Fig. 3
`
`Fig. 4
`
`8
`
`Energetiq Ex. 2005, page 8 - IPR2015-01362
`
`

`
`source confi guration running at 40 W.
`Complementing this increased source
`power, we have developed a number of
`features to improve source availability.
`
`Among these is a system for cleaning the
`collector mirror in-situ. The system can
`restore the collector’s refl ectivity to almost
`brand new, eliminating the need to take
`the system off line to replace the collector.
`We’ve also shown that the source can be
`run in a fully automated mode with good
`dose control. This increases availability
`while maintaining a 99.9% die yield.
`(See Fig. 3)
`
`As a result, productivity from our
`EUV scanners has been steadily rising –
`resulting in the recent announcement by
`IBM of a new 1-day EUV wafer exposure
`world record. In a test of the source,
`they exposed 637 EUV wafers in a single
`day. This test to verify the source’s power
`output and reliability was carried out with
`the scanner linked to a track, and using
`an exposure dose of 20 mJ/cm2 and
`conventional illumination.
`
`“The test was designed to check if the
`newly installed source was working
`correctly. Exposing so many wafers was
`an unexpected bonus – due to the source
`operating so well,” Dan Corliss, IBM’s EUV
`development program manager.
`
`In the meantime, several customers have
`cleared the 500 wafers per day barrier.
`These achievements show we are on track
`to meet our previously stated end-of-year
`goal of 500 wafers per day as an average
`and our 2016 goal of 1500 wafers per day
`to support volume production.
`
`Addressing the mask defect challenge
`With EUV lithography scanners becoming
`more mature, ASML is also active in
`addressing ancillary issues related to
`EUV lithography wafer fabrication.
`One example is mask front-side
`defectivity. In parallel to improving the
`system’s overall cleanliness, we are
`
`working with customers and materials
`suppliers in an ongoing joint research
`program to explore pellicles for protecting
`EUV masks from particle contamination.
`Together these efforts aim to improve
`printed defect levels. (See Fig. 4)
`
`EUV lithography requires refl ective rather
`than transmission masks. Hence pellicle
`materials for EUV have higher single-pass
`transmission requirements than for DUV
`lithography, as the EUV light must pass
`through the pellicle twice. The year-long
`research collaboration has developed a
`new higher-transmission pellicle. Tests on
`half-size pellicles mounted on the reticle
`have shown the new pellicle concept
`has little or no impact on CD or line
`roughness. The pellicles have also shown
`good robustness, surviving multiple
`exposures and extensive mechanical
`testing – including unusually rough
`handling – intact.
`
`First full-size, free-standing
`
`pellicle prototype for EUV
`
`masks
`
`The fi rst full-size, free-standing pellicle
`prototypes for EUV masks have been
`manufactured. Exposure tests using these
`prototypes are planned for later this year.
`
`Enabling future shrink
`Single-exposure EUV lithography enables
`aggressive feature shrink to drive the
`semiconductor industry forward over the
`coming years. The imaging performance
`reported from our NXE:3300B systems
`already exceeds requirements for the
`10-nm 2D logic node. And ASML’s
`technology roadmap extends the NXE
`platform to beyond the 7 nm node. As the
`next step on that roadmap, integration
`and qualifi cation of our fourth-generation
`system – the TWINSCAN NXE:3350B –
`has already begun.
`
`ASML Images, 2014
`
`“ Thank you for
`participating in our
`reader survey. We
`appreciate your
`input as it helps
`us improve the
`magazine.
`The Bose® SoundLink
`Mini Speaker is won
`by Sang Nyung Yoon
`of DuPont
`Electronics”
`
`www.asml.com/ImagesSurvey
`
`9
`
`Energetiq Ex. 2005, page 9 - IPR2015-01362
`
`

`
`Product lifecycle
`management:
`added-value across
`the industry
`
`By Thomas van Wezel, MPS Product Manager Product Life Cycle
`
`Abstract | ASML is introducing a more
`formalized approach to product lifestyle
`management. This involves mapping our
`systems to four major lifecycle stages
`defined by the level of support ASML offers.
`Timelines for when each system type
`transitions between stages are defined well
`in advance, and reviewed annually based on
`market demands and customer feedback.
`By communicating this information in a
`timely fashion, we will increase transparency
`for customers and suppliers – helping them
`improve their own business planning.
`
`ASML is 30 years old this year.
`In celebrating this anniversary, it is
`remarkable to note that one of the very
`first machine types we developed is still
`in service today. Almost 30 years old
`itself, the PAS 2500/5000 is still being
`used in production at several customers.
`Of course its role has changed: from the
`cutting edge of semiconductor production
`to More-than-Moore applications.
`
`However, all good things come to an end.
`And the PAS 2500/5000 will soon become
`the first ASML scanner to officially come
`to its End of Service (EoS), with ASML
`no longer providing support. With this
`milestone approaching, ASML is also
`launching a more formalized approach
`to product lifecycle management.
`
`This involves clearly defining the various
`stages of a product’s lifestyle and how
`ASML supports machines in each of
`these stages. Then by communicating
`this information along with the relevant
`timelines, including target dates for stage
`transitions, we hope to create greater
`transparency for both our customers and
`our suppliers on exactly what they can
`expect from ASML. This will in turn help
`simplify business planning.
`
`Defining the lifecycle
`To start this process, we have divided
`the product lifecycle into four stages
`based on the level of service we offer.
`We call these stages Regular Service,
`Extended Service, Limited Service and
`End of Service.
`
`10
`
`Energetiq Ex. 2005, page 10 - IPR2015-01362
`
`

`
`New
`
`Refurbishment
`
`Regular Service
`
`Extended Service
`
`Limited
`Service
`
`End of
`Service
`
`7 years
`
`Economic lifetime
`extension for ASML
`and customer
`
`Controlled
`Exit (typically
`3 years)
`
`Possible
`Transfer to
`3rd party
`
`time
`
`Fig. 1: Product lifestyle stages
`
`Easier for customers and suppliers to plan their business
`
`In the Regular Service stage we provide
`our highest level of support for new
`and recently refurbished machines to
`maximize system availability and enhance
`performance. We offer full availability
`of parts and a range of service level
`options to suit different semiconductor
`manufacturers’ needs.
`
`Around seven years after we finish
`manufacturing a machine type, it will
`transition to the Extended Service stage.
`Here again, we offer full parts availability
`and a range of service level options.
`But now the focus is more on extending
`the economic lifetime of systems.
`
`At some point after that, the system type
`moves into the Limited Service stage
`where we start to ramp down the support
`we offer. Spare part availability isn’t
`guaranteed and service is supplied on
`a best effort basis.
`
`Finally, the system type moves to End
`of Service, where ASML stops providing
`support altogether. However, systems
`may continue to provide an economically
`viable production facility – typically in
`niche applications – and we will endeavor
`to help customers find alternative service
`solutions where possible. (See Fig. 1)
`
`Communicating timelines
`The timeline for when a system type
`moves from stage to stage is not the same
`
`for all types. Although the transition to
`Extended Service is always seven years
`after manufacturing stops, some system
`types may be manufactured for longer
`than others. This could depend on the
`system’s popularity and intended role.
`For example, a pre-production system like
`the TWINSCAN NXE:3100 would come out
`of manufacturing earlier than a production
`workhorse like the TWINSCAN XT:1900i.
`Similarly, customer demand for and usage
`of refurbished systems plays a role in
`deciding when a system type transitions
`to Limited Service or EoS.
`
`Hence, a key part of our product lifecycle
`approach is deciding well in advance when
`each system type will transition between
`stages and communicating that in a timely
`fashion to both customers and suppliers.
`
`Extend the productive life
`
`of new systems
`
`Of course, these timelines aren’t
`something that we dictate and set in
`stone. Transition dates are reviewed
`based on feedback from customers and
`suppliers. For example, we have already
`decided to prolong the PAS 5500’s
`Extended Service period by four years
`to 2022. We will continue to review and
`update our product lifecycle timelines
`
`based on business potential and customer
`feedback on a yearly basis.
`
`Benefits throughout the chain
`Product lifecycle management is
`something we have always done within
`ASML. But by formalizing it in this way,
`we believe we can bring benefits for
`everyone. For example, by considering
`the lifecycle stages and end of life issues
`more rigorously in our design process,
`we can help extend the productive life
`of new systems.
`
`Meanwhile, by communicating the
`transitions between lifecycle stages,
`we make it easier for customers and
`suppliers to plan their business and
`investment in equipment. Our aim is to
`share these timelines as early as possible
`– particularly for the transition from
`Extended to Limited service and from
`Limited service to End of Service – and
`at least one year ahead of the transition.
`This will give everyone time to factor the
`information into their business decisions.
`
`Hence customers will be aware just how
`long ASML will be supporting the systems
`installed at their facility, and can decide
`the best time to migrate to new tools
`based on the service available, resale
`potential, etc. If they are considering
`buying a remarketed ASML system,
`they will be able to confirm how long the
`system will be supported before they
`finalize the deal.
`
`Suppliers will be better able to predict
`the demand for their products as they
`will know ahead of time when we will
`be manufacturing, refurbishing
`and supplying spare parts for each
`system type. This allows them to plan
`capacity, staffing levels and equipment
`requirements with more confidence.
`
`Given the long lifetimes of our systems,
`this long-term planning of the entire
`lifecycle will bring value for all parties
`involved in the semiconductor industry
`and associated businesses.
`
`Details of product lifecycle stages and
`transition timelines are available via
`ASML’s Account Managers.
`
`11
`
`ASML Images, 2014
`
`Energetiq Ex. 2005, page 11 - IPR2015-01362
`
`

`
`New nodes with your installed
`TWINSCAN NXTs
`
`By Jules Tops, SNEP Project Cluster Manager DUV, and Janneke van Heteren, SNEP Product Marketing Manager
`
`Abstract | ASML’s System Node Extension
`Packages (SNEPs) allow any TWINSCAN
`NXT system to be converted into a newer
`model in the fi eld. For example, the
`SNEP:A2C and SNEP:B2C respectively
`transform NXT:1950i and NXT:1960Bi
`systems into an NXT:1970Ci. SNEPs allow
`semiconductor manufacturers to extend
`their installed NXT systems for volume
`production at new nodes. This helps them
`transition from node to node in a cost
`effective manner, always having the latest
`lithography system while managing their
`capital expenditure.
`
`12
`
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`
`

`
`New nodes with your installed
`
`ASML Images, 2014
`
`Everyone likes getting value for their
`money. And at ASML, we want to make
`sure we deliver the maximum value for
`our customers. That’s why our TWINSCAN
`scanners have always been built using
`a highly modular architecture that allows
`systems to be upgraded in the fi eld with
`new options to improve productivity and
`performance. This allows semiconductor
`manufacturers to buy new systems
`in confi gurations tailored to their needs
`at that time, safe in the knowledge
`that the tool can be adapted as their
`needs change.
`
`its capabilities by one or two production
`nodes. The transformed system meets the
`full ATP specifi cation for the new model,
`and comes complete with a standard
`ASML warranty running from the date
`of the upgrade. In effect, manufacturers
`gain all the benefi ts of buying a brand
`new system, without the hassle of
`de-commissioning an installed tool.
`
`Our SNEP strategy gives semiconductor
`manufacturers the maximum fl exibility in
`planning their investment in lithography
`equipment. You can buy an NXT system
`
`Any installed NXT system can be converted to a
`newer model in the fi eld
`
`Now with the TWINSCAN NXT platform,
`we are taking that approach a step
`further. Through System Node Extension
`Packages (SNEPs), any installed NXT
`system can effectively be converted to
`a newer model in the fi eld – extending
`
`for high-volume manufacturing at one
`node and then upgrade it when you are
`ready to transition to the next node.
`This avoids the need to invest in brand
`new systems each time you move to a
`new production node.
`
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`
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`
`

`
`A completely new system
`Two SNEPs are available: the SNEP:A2C
`and SNEP:B2C. These transform
`NXT:1950i and NXT:1960Bi systems
`respectively into our latest scanner,
`the NXT:1970Ci. This represents a
`one-node extension for the NXT:1960Bi and
`a two-node extension for the NXT:1950i.
`(See Fig. 1)
`
`Extending its
`
`capabilities by one or two
`
`production nodes
`
`Upgrades are carried out by a dedicated
`SNEP team, in cooperation with our
`local customer support personnel.
`Each upgrade is tailored to a specific
`tool via the tool number. The exact
`sub-systems to be upgraded are
`determined based on the system’s
`current configuration. But typically the
`upgrade includes replacing the wafer
`handler, stage and table, and installing
`the new ultra-violet level sensor (UV-LS),
`parallel ILIAS (PARIS) sensor and CO2
`
`immersion hood. Where necessary,
`the projection lens may also be replaced
`with a newer model.
`
`Once all the necessary hardware and
`software is upgraded, the team qualifies
`all the modules and then the system
`as whole before carrying out the ATP
`specification. The final system has all
`the features and performance of a
`straight-from-the-factory NXT:1970Ci
`(see box), backed up by our standard
`12-month new system warranty.
`
`A flexible process
`Our dedicated SNEP team has already
`carried out a number of system upgrades
`at ASML facilities around the world.
`This has allowed us to optimize the
`upgrade procedure to maximize flexibility
`and minimize downtime. For example,
`by performing jobs in parallel wherever
`possible, we reduce the time taken for
`the upgrade. This also affords us some
`freedom in the order in which tasks are
`carried out to reduce the impact of any
`unexpected delays. Moreover, the team
`is able to adjust the upgrade process
`according to the space available around the
`system, reducing risk.
`
`Following this learning period, the first SNEP
`upgrade projects at customer sites were
`carried out earlier this year. These systems
`are now operating in production and in spec,
`allowing the customers to move into volume
`production at a new node.
`
`An ongoing roadmap for value
`The SNEP:A2C and SNEP:B2C are just
`the first steps in our roadmap for node
`extension. As each new TWINSCAN NXT
`system is released, we will also be making
`available packages for transforming installed
`NXT systems into the very latest model.
`In this way, we aim to give semiconductor
`manufacturers the ability to transition from
`node to node in the most cost-effective way
`possible – ensuring they always have the
`capabilities needed for profitable volume
`manufacturing of advanced products as
`well as the freedom to control their capital
`expenditure and investment in new equipment.
`
`Transform NXT:1950i and
`
`NXT:1960Bi systems into
`
`an NXT:1970Ci
`
`TWINSCAN NXT:1970Ci
`specifications
`
`Full-wafer dedicated
`chuck overlay
`
`Full-wafer matched
`machine overlay
`
`Full-wafer focus
`uniformity
`
`2.0 nm
`
`3.5 nm
`
`20 nm
`
`Full-wafer CDU (isolated
`features)
`
`1.3 nm
`
`Full-field throughput (96
`shots)
`
`250 wph
`
`NXT configurations in the field and transformation paths
`
`B2C path
`A2C path
`
`SNEP:B2C
`(+1 node)
`
`NXT:1970Ci
`
`NXT:1960Bi
`1951 lens
`
`NXT:1960Bi
`1952 lens
`
`Snep = System Node
`Extension Package
`
`
` Performance
`
`NXT:1950i
`1950/1951 lens
`
`NXT:1950i + PEP
`1950/1951 lens
`
`SNEP: A2C
`(+ 2 nodes)
`
`Node N
`
`Node N+1
`
`Node N+2
`
`Defects
`
`< 7 per wafer
`
`Fig. 1: SNEP is a System Node Extension Package: New hardware and software installed during a field
`
`transformation will bring the NXT:1950i or NXT:1960Bi to the newest node. (NXT:1970Ci specs)
`
`14
`
`Energetiq Ex. 2005, page 14 - IPR2015-01362
`
`

`
`The TWINSCAN NXT:1970Ci
`
`By Rem