United States Patent [191
`Lee et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,952,524
`Aug. 28, 1990
`
`[54] SEMICONDUCTOR DEVICE
`MANUFACTURE INCLUDING TRENCH
`FORMATION
`
`[75] Inventors: Kuo-Hua Lee; Chili-Yuan Lu, both of
`Lehlgh county’ Pa‘
`[73] Assignee: AT&T Bell Laboratories, Murray
`H111’ NJ‘
`[21] Appl' No‘: 347’975
`[22] Filed:
`May 5, 1989
`
`5
`
`""""""""""""""""""""
`. .................................... ..
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`
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`
`,
`437/982
`
`[58] Field of Search ....................... .. 437/67, 240, 982
`His/DIG 132;
`'
`
`[56]
`
`References Cited
`
`
`
`1
`U‘S. 4 506 435 3/1985 Pr k_
`i
`i
`15 "1 et a‘ --------------------- ~~
`4,543,706 10/1985 Bencuya et al.
`..
`4,571,819 2/1986 Rogers et a1. ..................... .. 156/653
`FOREIGN PATENT DOCUMENTS
`
`437/67
`
`"""""
`437/67
`57-12533 l/l982 Japan ................... ..
`437/67
`58-143548 3/1983 Japan .... ..
`59-63739 4/1984 Japan ................................... .. 437/67
`
`59-106133 6/1984
`60-43343 3/ 1935
`61-8944 l/l986
`61-90442 5/1986
`62-216261 9/1987
`Primary Examiner-Olik Chaudhuri
`Attorney, Agent, or Firm-John T. Rehberg
`[57]
`ABSTRACT
`A trench which provides electrical isolation between
`transistors on an integrated circuit substrate is de
`scribed. The trench is lined with a diffusion barrier,
`typically a thermal oxide followed by a thermal ‘stress
`relieflayer’ typically formed from TEOS Then a ?ner
`.
`.
`.
`.
`
`mammal’ typlcany BPTEOS’ ‘5 dammed t° ?n ‘he
`trench and cover the upper surface of the wafer. The
`?ller material is heated to make it ?ow. Next the outer
`surface of the flowed ?ller material is next subjected to
`
`an etch-back trench protrude slightly above the upper surface of the makes the tOp Surface of the
`
`
`substrate. The resulting trench contains the diffusion
`barrier 1a
`-
`yer, the thermal stress rellef layer, and the
`?ner material’ The ?ner material and the thermal Stress
`relief layer will soften during subsequent heat treat
`ments of the wafer, thus relieving thermal stresses, and
`preventing the occurrence of defects and dislocations
`wlthm the Wafer
`
`13 Claims, 3 Drawing Sheets
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`NVIDIA Corp.
`Exhibit 1111
`Page 001
`
`

`

`US. Patent Aug. 28, 1990
`
`Sheet 1 of3
`
`4,952,524
`
`NVIDIA Corp.
`Exhibit 1111
`Page 002
`
`

`

`U.S. Patent
`
`Aug. 28, 1990
`
`Sheet 2 of3
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`4,952,524
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`NVIDIA
`Exhibit
`Page 003
`
`NVIDIA Corp.
`Exhibit 1111
`Page 003
`
`

`

`U.S. Patént Aug. 28, 1990
`
`Sheet 3 of3
`
`‘4,952,524
`
`F1617 r
`
`NVIDIA Corp.
`Exhibit 1111
`Page 004
`
`

`

`1
`
`4,952,524
`
`SEMICONDUCTOR DEVICE MANUFACTURE
`INCLUDING TRENCH FORMATION
`
`10
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to semiconductor integrated
`circuits and more particularly to integrated circuits
`with trenches for inter-device isolation.
`2. Description of the Prior Art
`As integrated circuits become smaller, the need for
`effective isolation between individual devices becomes
`more critical. Structures used for inter-device isolation
`should desirably provide effective electrical isolation
`while occupying little space and allowing good surface
`planarity.
`One method of inter-device isolation is the use of a
`?eld oxide between devices. Field oxides provide ac
`ceptable isolation between devices with shallow active
`regions. However, ?eld oxides grown by conventional
`processes often exhibit birds beaks and other formations
`which not only cause undesirable encroachments into
`device areas but also adversely affect surface planarity.
`Trench isolation is another way of providing inter
`device isolation. Trench isolation is applicable to both
`bipolar and ?eld effect transistor technologies.
`Trenches generally consume less space than ?eld ox
`ides. Traditionally, trench isolation involves etching a
`narrow, deep trench or groove in a silicon substrate and
`then ?lling the trench with a ?ller material such as a
`silicon oxide or polysilicon. Trenches are also often
`used in memory design to provide information storage
`capacity which requires good electrical connection to
`selected transistors. However, isolation trenches de
`scribed here are designed to have minimal charge stor
`age and no electrical connection to any transistor.
`As already mentioned, trenches are often ?lled with
`“hard” materials such as silicon oxide or polysilicon.
`However, existing techniques do not permit wide varia
`tions in the dimensions of the trench. For example, if a
`wafer contains both large and small trenches and
`polysilicon is deposited so that it ?lls the small trenches,
`the large trenches will not be completely ?lled. Fur
`thermore, since polysilicon deposition is not always
`completely conformal, voids, or at least seams, may
`45
`form in the polysilicon, especially in narrow trenches.
`The voids may trap various impurities which may later
`cause reliability problems.
`.
`Another problem with the use of “hard” materials is
`that they may cause dislocations and other defects in the
`silicon substrate during subsequent high temperature
`processing of the wafer due to the differences in rates of
`thermal expansion between the “hard” ?ller material
`and the silicon substrate. Furthermore, trenches formed
`by traditional techniques have upper surface which are
`dif?cult to planarize. Consequently, most designers
`who employ trenches use them in narrow inter-device
`regions and use conventional thermally grown ?eld
`oxides in wider inter-device regions.
`Those concerned with the development of advanced
`semiconductor integrated circuit technology have en
`gaged in a continuous search for improved methods of
`inter-device isolation and particularly for improved
`methods of inter-device trench formation of various
`sizes.
`One approach to trench construction is illustrated in
`Becker et al., “Low Pressure Deposition of Doped
`SiO2 by Pyrolysis of Tetraethylorthosilicate (TEOS)”,
`
`60
`
`65
`
`2
`J. Electrochem. Soc., Vol. 134, No. 11, pp. 2923-2931
`(1987). The publication discusses trenches ,which con
`tain silicon dioxide spacers and a silicon dioxide block in
`the center of the trench. The silicon dioxide block effec
`tively reduces the size of the trench cavity; thus making
`a wide trench into two or more narrow trenches which
`may, of course, be more easily ?lled.
`
`SUMMARY OF THE INVENTION
`Applicants have invented a method for fabricating
`trenches in a wide range of sizes that avoids a variety of
`problems associated with prior art techniques, such as
`thermally generated stresses in the substrate and voids
`in the trench ?ller material. In a typical embodiment of
`this invention, a trench is etched into a substrate, typi
`cally silicon, around the device area which is to be
`isolated. The interior of the trench is then covered with
`a primary diffusion barrier; for example, a thermally
`grown oxide. The primary diffusion barrier serves to
`prevent diffusion of dopants contained in materials
`which may subsequently be used to ?ll the trench. Next,
`a thermal stress-relief layer (i.e., one that absorbs
`stresses due to heating efforts), for example, a confor
`mal dielectric, is deposited in the trench over the pri
`mary diffusion barrier. The thermal stress-relief layer
`also serves as a secondary diffusion barrier. Next a third
`layer of ?ller material, such as a flowable dielectric is
`deposited within the trench on top of the thermal stress
`relief layer. The ?ller material has a flow temperature
`which is lower than the ?ow temperature of the stress
`relief layer. The ?ller material is deposited with suf?
`cient thickness to completely ?ll the remainder of the
`trench and cover the upper surface of the silicon wafer.
`Then the ?ller material is flowed by heating it to its
`flow temperature. During the heating process, the
`stress-relief layer softens without ?owing. The rela
`tively soft stress-relief layer absorbs the stresses gener
`ated during the heating process and prevents cracking
`or dislocations in the diffusion barrier or silicon sub—
`strate. Meanwhile, the resulting surface topography of
`the ?ller material becomes comparatively flat after
`?ow. Finally, an etch-back planarization step is used to
`etch the ?owed ?ller material back to the surface of the
`substrate. After the trench is ?lled, device processing
`steps may be started.
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`FIGS. 1-8 are cross sectional views of structures of
`one illustrative embodiment formed by an exemplary
`sequence of processing steps; and
`FIG. 9 is a cross sectional view of an additional illus
`trative embodiment of the present invention.
`
`DETAILED DESCRIPTION
`FIGS. 1-9 have not been drawn to scale so that they
`may be more clearly understood. Furthermore, the
`details of individual transistor structures have been
`eliminated to make the ?gures clearer. Only cross-sec
`tions of trenches are shown. The ?gures schematically
`show both a narrow trench and a wide trench. Alterna
`tively, the pair of illustrated structures may be consid
`ered cross-sectional views of different points through
`the same trench.
`In FIG. 1, reference numeral 11 denotes a substrate,
`which may be typically silicon. Substrate 11 may in
`clude an upper epitaxial layer, if desired. Reference
`numeral 13 denotes a grown or deposited dielectric pad
`
`NVIDIA Corp.
`Exhibit 1111
`Page 005
`
`

`

`25
`
`4,952,524
`3
`which may be typically silicon dioxide. Reference nu
`meral 15 denotes a masking layer which may be typi
`cally silicon nitride. Reference numeral 17 refers to a
`patterned material such as a photoresist. Those skilled
`in the art will realize that pad 13 and masking layer 15
`may be formed by conventional techniques during typi
`cal initial stages of semiconductor processing. Repre
`sentative thicknesses for layers 15 and 13 are 1000-3000
`A and 100-400 A, respectively.
`Alternatively, if desired, masking layer 15 may be
`polysilicon with a thickness of 10004000 A. Polysilicon
`may be desired as the masking layer instead of silicon
`nitride because an etchback planarization step (to be
`described later) typically has greater selectivity for
`polysilicon than silicon nitride. Other materials may
`also be used.
`Photoresist 17 may be patterned by conventional
`techniques. Then, the entire structure is etched by tech
`niques well-known to those skilled in the art to “dig”
`trenches 51 and 53 (illustrated in FIG. 2). (If cover layer
`15 is a nitride layer, photoresist 17 may be stripped if
`desired, before trenches 51 and 53 are created. Nitride
`layer 15 can then serve as an etch mask. However, if
`cover layer 15 is polysilicon, photoresist 17 typically
`remains in place during creation of trenches 51 and 53
`because polysilicon does not serve as an effective mask
`for the common etchants used in etching the underlying
`silicon substrate.)
`One recipe for “digging” a suitable trench is a two
`step reactive ion etching process practiced by those
`skilled in the art. The ?rst step utilizes 150 sccm 0;,
`together with 15 sccm SF 6 at 500 Watts power and 400
`milliTorr for 1-7 minutes. The second step utilizes 2.5
`sccm Freon-13Bl at 500 Watts and 600 milliTorr until a
`satisfactory trench depth and pro?le is achieved. Typi
`cal trench depths are l~5 um. Numerous other etching
`recipes will occur to those skilled in the art.
`Trench 51 has been illustrated in FIG. 2 as being
`narrower than trench 53. The invention described
`herein is applicable to trenches with a wide variety of
`widths. Trenches as narrow as 0.6 um and as wide as 30
`pm have been created with the present technique.
`After trenches 51 and 53 have been created, as illus
`trated in FIG. 2, photoresist 17 is stripped if it has re
`mained in place (e.g., if masking layer 15 is polysilicon).
`Next, a primary diffusion barrier layer 21 is formed on
`the sidewalls and bottom of trenches 51 and 53. The
`diffusion barrier 21 should be a material which exhibits
`relatively few interface charge traps with substrate 11.
`Interface charge traps are undesirable because trapped
`charges attract opposing charges in the substrate, thus
`creating a channel on the trench wall which, in combi
`nation with adjacent source/drain regions, will com
`prise a parasitic transistor.
`An exemplary candidate for layer 21 is a thin, high
`quality undoped silicon dioxide layer. FIG. 3 illustrates
`oxide layer 21. A steam-grown thermal oxide formed at
`approximately 850° C. is a good candidate for oxide
`layer 21 because of its low stress and low silicon-inter
`face trap density. A representative thickness for layer
`21 is 100400 A. A uniform thickness for layer 21 is
`desirable and achievable by the above process.
`Next, as illustrated in FIG. 4, a thermal stress-relief
`layer 23 is formed upon diffusion barrier layer 21. As
`can be seen from FIG. 4, stress-relief layer 23 com
`pletely covers oxide layer 21 on the bottom and side
`walls of trenches 51 and 53. A comparatively uniform
`
`4
`thickness for layer 23 is desirablea A representative
`thickness for layer 23 is 1000-3000 A.
`Stress relief layer 23 may be, for example, borophos
`phosilicate glass (BPSG) or an oxide layer deposited by
`the pyrolysis and decomposition of tetraethoxysilane
`[(Si(OC2H5)4], abbreviated TEOS. Methods for depos
`iting BPSG or pyrolyzing TEOS are well-known to
`those skilled in the art. Consequently, the expression
`“depositing a layer of TEOS” is generally understood
`by those skilled in the art to mean the deposition of a
`dielectric layer by decomposition and pyrolysis of
`TEOS in a reactor. The resulting oxide of silicon exhib
`its excellent step coverage. Other oxide precursor gases,
`for example, silane, may be employed, if desired. How
`ever, TEOS is comparatively safer to handle than, for
`example, silane.
`Other materials may also be used for layer 23. What
`ever material is utilized for layer 23, it should have a
`low charge trap density and a comparatively high flow
`temperature. The signi?cance of the comparatively
`high flow temperature layer 23 will be subsequently
`explained.
`After layer 23 is deposited, a ?ller layer 25, illustrated
`in FIG. 5, is deposited. The ?ller layer 25 is a material
`which flows at a lower temperature than stress-relief 23.
`Furthermore, ?ller layer 25 is deposited in suf?cient
`quantity to fill the trench.
`An exemplary candidate for ?ller layer 25 is an oxide
`formed by the pyrolysis and decomposition of TEOS
`with approximately 3 percent boron and 3 percent phos
`phorous by weight added. The resulting dielectric ma
`terial is often assigned the acronym, BPTEOS, associ
`ated with' the chemical precursors used in its deposition.
`Thus, the expression “depositing a layer of BTPEOS” is
`generally understood by those skilled in the art to mean
`the deposition of a dielectric layer by decomposition of
`TEOS in the presence of phosphorous and boron dop
`ants in a reactor. The phosphorous and boron dopants
`may be obtained, for example, from trimethylphosphite,
`phospine, trimethylborate, trimethylphosphate, trieth
`ylphosphite, or triethylphosphate.
`A variety of other materials may be selected to pro
`duce layers 23 and 25. For layer 23, the chemical pre
`cursors, diacetoxytditertiarybutoxysilane (C10H26O4Si),
`known by the acronym “DADBS”, or tetramethylcy
`clotetrasiloxane (C4H16Si4O4), known by the acronym
`“TMCTS”, sold by J. C. Schumacher, a unit of Air
`Products and Chemicals Inc. under the trademark
`“TOMCATS”, may be used. Deposition techniques for
`these materials are known to those skilled in the art.
`For layer 25, any of the above chemical precursors
`may be combined with dopants to provide a suitable
`flowable ?ller material. Furthermore, layer 23 may be
`also formed from any of the above precursors, together
`with dopants, provided the doping level in layer 23 is
`lower than in layer 25 so tht layer 25 will have a lower
`?ow temperature than layer 23.
`For example, the flow properties of dielectrics depos
`ited from BPTEOS are substantially influenced by the
`percentages of included boron and phosphorous. Con
`sequently, one might use BPTEOS to form thermal
`stress relief layer 23 if layer 23 includes lesser amounts
`of dopants from ?ller material 25 so that the flow tem
`perature of layer 25 remains below the flow tempera
`ture of layer 23. Alternatively, a thermal stress-relief
`layer 23 formed from TEOS with a small amount of
`phosphorous and no signi?cant amount of boron
`(known by the acronym PTEOS) may be used, pro
`
`45
`
`55
`
`NVIDIA Corp.
`Exhibit 1111
`Page 006
`
`

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`O
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`5
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`25
`
`35
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`4,952,524
`5
`6
`vided the phosphorous content is adjusted so that the
`produce the con?guration shown in FIG. 8. FIG. 8
`?ow temperature of layer 25 remains below the flow
`illustrates the wafer with trenches 51 and 53 filled and
`temperature of layer 23. It should also be noted that the
`upper surface 71 of silicon ready for further processing,
`flow temperature of filler material 25 should desirably
`such as device formation, according to procedures
`be higher than the temperatures of all subsequent fur
`known in the semiconductor art.
`nace heat treatments to which the wafer is subjected.
`FIG. 8 shows that the upper surfaces 531 and 511 of
`After ?ller material 25 has been deposited, it is ?owed
`trenches 51 and 53 protrude somewhat beyond upper
`by heating it, either in a furnace or by a rapid thermal
`surface 71 of the silicon wafer. The protrusions 531 and
`anneal (RTA) process. The resulting structure after
`511, which are typically a few hundred Angstroms, are
`advantageous because they help prevent parasitic chan
`flow is illustrated in FIG. 6. If BPTEOS is used for
`layer 25, with the speci?ed amounts of boron and phos
`nel formation around the sidewalls of the trench, which
`phorous, it may be flowed at a temperature of between
`may occur with trenches formed by conventional pro
`850° C. and 950° C. for i; to 2 hours in an atmosphere of
`cesses. A parasitic channel may be formed when the
`either nitrogen or oxygen. Alternatively, the BPTEOS
`gate runner contacts exposed oxide on the trench side
`may be rapidly thermal annealed (RTA) at lOOO° C. for
`wall. If the exposed oxide is thinner than the gate oxide
`of an adjacent MOS transistor, the parasitic channel
`30-60 sec.
`The structure of FIG. 6 is next subjected to an etch
`causes increased transistor leakage current. (A discus
`back planarization technique to planarize the surface of
`sion and diagram of parasitic channel formation is con
`the wafer. Various etchback planarization techniques
`tained in Kurosawa et al., “A New Birds’-Beak Free
`Field Isolation Technology for VLSI Devices”, IEEE
`are well-known to those skilled in the art. Typically, a
`photoresist 81 is deposited on top of layer 25. The pho
`IEDM Technical Digest, pp. 384-387, 1981.)
`The presence of protrusions 531 and 511 is ensured by
`toresist 81 is spun to create a planar upper surface. Then
`the combination photoresist and layer 25 is etched with
`layer 15. Layer 15 serves as an etch-stop for the planari
`zation etch-back process and helps to govern the height
`an etchant that attacks both materials at the same rate.
`of protrusions 531 and 511.
`U.S. ‘Pat. No. 4,481,070 issued to Thomas et al. illus
`trates an etchback planarization technique.
`As mentioned before, the technique just described
`If trench 51 is very narrow (i.e., has a high aspect
`works nicely to ?ll trenches of various sizes on the same
`ratio), voids may be formed in layer 25 after it is depos
`wafer. Returning to FIG. 5, it will be noted, as men
`ited. To prevent voids, a repeated ?ow and etchback
`tioned before, that narrow trench 51 has a relatively
`procedure can be performed. The repeated flow and
`narrow dimple, 61, in layer 25. By contrast, wide trench
`etchback procedure can be accomplished by those
`53 has a much wider dimple, 63 in layer 25. However,
`the planarization step illustrated by FIG. 6, permits
`skilled in the art in separate reactors, or in a single reac
`tor. During the repeated flow and etchback procedure,
`adequate ?lling of wide trench 53, as well as narrow
`a photoresist material is applied to the surface of layer
`trench 51.
`25 and planarized, for example, by spinning. Then, the
`Another advantage of the present invention is that
`combination photoresist and layer 25 are etched down
`relatively few crystalline defects are generated in sili
`ward for some distance. Layer 25 is then heated to its
`con substrate 11 during the ?ll-in sequence illustrated in
`?ow temperature. Then, another photoresist is applied
`FIGS. 3-6. Thermal stress-relief layer 23 softens during
`the deposition and subsequent heating of ?ller material
`and the entire process repeated one or more times.
`Referring to FIG. 5, the height of trench 53 is de
`25. The soft layer 23 absorbs the thermal stresses gener
`ated during the deposition and subsequent heating of
`noted by hz. The thickness of layer 25 within trench 53
`is denoted by b3. It is desirable that h3 be greater than
`layer 25, thus preventing, or at least reducing, the oc
`hz so that the trench will be completely ?lled before
`currence of defects and dislocations in layer 21 or sub
`?ow and etchback begins. The thickness, h] of layer 25
`strate 11. Furhermore, subsequent heat treatments per
`above the upper surface of the wafer is, typically, equal
`formed after the creation and filling of trenches 51 and
`to h3. Dimples, or hollows,-61 and 63, may be noted in
`53 are not likely to induce cracks, defects, or disloca
`the upper surface of layer 25 above trenches 51 and 53,
`tions in substrate 11. During subsequent heat treat
`respectively. Because trench ‘53 is wider than trench 51,
`ments, both dielectrics 25 and 23 soften and absorb
`thermally generated stresses.
`dimple 63 is wider than dimple 61, due to the fairly
`conformal properties of layer- 25. Of course, no matter
`Layer 21 (and, to a lesser extent, layer 23) serves as
`how wide the trench, it will‘be virtually completely
`diffusion barriers. They prevent dopants which may be
`?lled if the thickness of deposited layer 25 is chosen to
`used in filler material 25 from diffusing into the sub
`be equal to or greater than thedepth of the trench.
`strate.
`FIG. 7 illustrates the wafer after photoresist 81 and
`The above-described technique exhibits a variety of
`advantages over prior art techniques. One already-men
`layer 25 have been etched back until the upper surface
`of layer 15 (typically silicon nitride or polysilicon) has
`tioned prior art technique creates a silicon dioxide block
`within the trench itself. The block effectively partitions
`been reached. Comparisons of FIGS. 6 and 7 shows that
`the upper portion of layer 23 has also been removed.
`a large trench into two or more smaller trenches. How
`The upper portion of layer 23 may be removed by the
`ever, creation of the block requires an additional mask.
`same etchback procedure if layer 23 is, for example
`Applicants’ invention avoids the use of such an addi
`tional mask. An additional advantage of applicants’
`TEOS or BPTEOS and layer 25 is formed from
`invention is the prevention of parasitic transistor forma
`BPTEOS. Should layer 23 be a material which is not
`easily etched by the procedure which etches layer 25
`tion. Convex protrusions 511 and 531 are instrumental
`in preventing parasitic transistor-formation. The pres
`and photoresist 81, it may be stripped by a separate
`procedure using a different etchant.
`ence of protrusions 511 and 531 is ensured by mask layer
`When the con?guration depicted in FIG. 7 is
`15 (which is subsequently etched away). By contrast,
`reached, layers 15, 13 and a small portion of layer 23
`some prior art trench designs have concave upper sur
`which is adjacent those layers may be stripped away to
`faces which, under various circumstances, may increase
`
`50
`
`45
`
`65
`
`NVIDIA Corp.
`Exhibit 1111
`Page 007
`
`

`

`4,952,524
`7
`the liklihood of parasitic transistor formation. For ex
`ample, the structure shown in FIG. 15 of the Becker et
`al. article (as noted above) has a concave upper surface.
`The sides of the trench have spacers which are formed
`by depositing and then etching TEOS. However, in a
`manufacturing environment, the spacers cannot be con
`sistently made with an upper surface which is smooth
`with the top of the silicon substrate. Some overetching
`will inevitably occur on some spacers. Consequently,
`the trench will have a region of exposed silicon on its
`sidewall (above the slightly overetched spacer). Subse
`quent normal device processing steps may create a para
`sitic device at the upper exposed portion of the trench
`wall.
`A few other advantages of the inventive design are
`also worthy of mention. Prior art trenches ?lled with
`polysilicon may exhibit voids or seams which may trap
`various impurities. The impurities may later escape and
`cause device reliability problems. Applicants’ invention
`may be practiced, as mentioned before, with a repeated
`flow and etchback procedure which is very helpful in
`eliminating voids in the filler material. Furthermore,
`polysilicon is not an ideal insulator, having a resistivity
`of roughly l06Q-cm. The oxides employed in appli
`cants’ trench have resistivities approximately eight or
`ders of magnitude greater—thus, providing better isola
`tion.
`The present invention is not limited to trenches with
`straight sidewalls. FIG. 9 illustrates two trenches 151
`and 153 with slanted sidewalls. Trench 151 is “V”
`shaped with slanted walls 163 and 165 and bottom 161.
`Trench 153 has a ?at bottom and slanted sidewalls 173
`and 175. Various methods for making trenches with
`slanted sidewalls are known to those skilled in the art.
`These methods include wet chemical etches utilizing
`KOH or plasma taper etches.
`Both trenches are ?lled and processed in the manner
`previously described. The resulting structures shown in
`FIG. 9 contain layers 121, 123, and 125 which are akin
`to layers 21, 23, and 25 of FIG. 8.
`Other embodiments of the inventive principles dis
`closed herein are also contemplated, including use with
`Groups III~V substrates, such as gallium arsenide.
`We claim:
`1. A method of semiconductor device fabrication
`comprising:
`forming a trench into a substrate;
`forming a diffusion barrier layer in said trench;
`characterized by the further steps of
`depositing a thermal stress-relief layer upon said bar
`rier layer;
`depositing a ?ller material upon said thermal stress
`relief layer, said ?ller material having an outer
`surface and ?lling said trench, said ?ller material
`having a ?ow temperature which is lower than the
`flow temperature of said thermal stress relief layer;
`heating said ?ller material to at least its flow tempera
`ture to smooth said outer surface; and etching back
`said upper surface of ?ller material.
`2. The method of claim 1 wherein said substrate is
`silicon.
`3. The method of claim 1 wherein said thermal stress
`relief layer is formed by deposition of a material chosen
`from the group consisting of tetraethoxysilane, diace
`toxyditertiarybutoxysilane, and tetramethylcyclotet
`rasiloxane.
`4. The method of claim 1 wherein said thermal stress
`relief layer is borophosphosilicate glass.
`
`35
`
`8
`5. The method of claim 1 wherein said ?ller material
`is formed by deposition of a material chosen from the
`group consisting of: tetraethoxysilane, diacetoxyditer
`tiarybutoxysilane, and tetramethylcyclotetrasiloxane,
`together with dopants to promote ?owability.
`6. The method of claim 1 wherein said diffusion bar
`rier is silicon dioxide.
`7. The method of claim 1 wherein said filler material
`contains 3i§ percent each boron and phosphorous by
`weight.
`8. The method of claim 1 wherein said etching-back
`step includes the steps of:
`depositing a resist material upon said outer surface of
`said ?ller material;
`planarizing said resist; and,
`etching said resist and said ?ller material to expose
`the outer surface of said filler material.
`9. The method of claim 1, wherein said heating step
`and said etching-back step are performed more than
`once.
`10. The method of claim 1, wherein said heating step
`is performed in a furnace at 950° C.i50° C.
`11. The method of claim 1, wherein said heating step
`is accomplished by rapid thermal annealing at
`1050:50" C.
`12. The method of claim 1 wherein said filler material
`contains dopants and wherein said thermal stress relief
`layer contains dopants in a lesser concentration than
`said ?ller material.
`13. A method for semiconductor device manufacture
`comprising:
`depositing a first silicon dioxide layer upon a surface
`of a silicon substrate;
`depositing a layer of silicon nitride upon said first
`layer of silicon dioxide;
`selectively etching through said silicon dioxide layer
`and said silicon nitride layer into said silicon sub
`strate to form at least one trench, said trench hav
`ing sidewalls and a bottom, a portion of said ?rst
`silicon dioxide layer, and said silicon nitride layer
`remaining on said silicon surface;
`forming a second silicon dioxide layer on said side
`walls and said bottom of said trench;
`depositing a thermal stress relief layer upon said sec
`ond silicon dioxide layer, said thermal stress relief
`layer being formed by the decomposition of an
`oxide precursor gas, said thermal stress relief layer
`defining a cavity within said trench;
`depositing a flowable ?ller material into said cavity,
`said filler material being produced by the decom
`position of an oxide percursor gas, together with
`boron and phosphorous, said ?ller material being
`thick enough to substantially ?ll said cavity and to
`have a thickness above said surface of said silicon
`substrate, said flowable ?ller material having a
`flow temperature lower than the flow temperature
`of said thermal stress relief layer;
`heating said ?owable ?ller material to cause said filler
`material to flow;
`etching back said filler material, together with said
`portion of said first silicon dioxide layer remaining
`on said silicon surface and together with the said
`portion of said silicon nitride layer remaining on
`said silicon surface to expose said silicon surface
`and to create an upper surface on said filler mate
`rial which protrudes slightly above said silicon
`surface.
`
`*
`
`*
`
`*
`
`* *
`
`15
`
`25
`
`45
`
`55
`
`65
`
`NVIDIA Corp.
`Exhibit 1111
`Page 008
`
`