(19) Japan Patent Office (JP)
`
`(12) Japanese Unexamined Patent
`Application Publication (A)
`
`
`(51) Int. Cl.6
`H 01 L 21/06
`
`
`
`
`Identification codes
`
`
`
`JPO file numbers
`
`7210-4M
`
`(11) Japanese Unexamined Patent
`Application Publication
`H7-86158
`(43) Publication date: March 31, 1995
`
`Technical indications
`
`FI
`
`H 01 L
`
`
`
`
`27/06
`
`
`
`
`Request for examination: Not yet requested; Number of claims: 6; FD (Total of 10 pages)
`
`Japanese Patent Application
`H5-189021
`
`June 30, 1993
`
`(21) Application number
`
`(22) Date of application
`
`
`
`
`
`
`
`
`(71) Applicant
`
`
`
`
`(72) Inventor
`
`
`
`
`(72) Inventor
`
`
`(74) Agent
`
`000002185
`Sony Corporation
`6-7-35 Kita Shinagawa, Shinagawa-ku,
`Tokyo-to
`
`Hiroaki YASUSHIGE
`℅ Sony Corporation
`6-7-35 Kita Shinagawa, Shinagawa-ku,
`Tokyo-to
`
`Norikazu OUCHI
`℅ Sony Corporation
`6-7-35 Kita Shinagawa, Shinagawa-ku,
`Tokyo-to
`Jun TAKATSUKI, Patent Attorney
`
`
`(54) [TITLE OF THE INVENTION] BICMOS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
`THEREOF
`
`
`
`
`
`(With amendment)
`(57) Abstract
`[PURPOSE] To provide a technology relating to a
`BiCMOS
`semiconductor device having bipolar
`transistors and MOS transistors having an LDD
`structure in which inconveniences as a result of
`overetching are resolved.
`
`[CONSTITUTION] In a BiCMOS semiconductor
`device having a bipolar transistor Tr3 and a MOS
`transistor Tr1 of an LDD structure, a conductive film
`7d identical to a gate electrode 7 of the MOS transistor
`is formed around a base region 14b of the bipolar
`this conductive film 7d
`is
`transistor Tr3 and
`electrically isolated from the base region through an
`isolation region 5 or the like.
`
`
`
`
`
`NVIDIA Corp.
`Exhibit 1109
`Page 001
`
`

`

`(2) Japanese Unexamined Patent Application Publication H07-86158
`
`[Scope of Patent Claims]
`[Claim 1] A BiCMOS semiconductor device having
`bipolar transistors and MOS transistors having an LDD
`structure, characterized in that a conductive film
`identical to a gate electrode of said MOS transistor is
`formed around the base region of said bipolar transistor
`and said conductive film is electrically isolated from
`the base region.
`[Claim 2] A manufacturing method of a BiCMOS
`semiconductor device having bipolar transistors and
`MOS
`transistors
`having
`an LDD
`structure,
`characterized in that the manufacturing method of a
`BiCMOS semiconductor device comprises
`a process of forming an insulating film over the entire
`surface after the formation of the LDD region and the
`gate electrode of said MOS transistor,
`a process of forming an opening in an insulating film of
`the base region of said bipolar transistor and carrying
`out an ion implantation to form a base region,
`a process of covering said opening by a resist, and
`a process of performing an anisotropic etching process
`to said insulating film.
`[Claim 3] A manufacturing method of a BiCMOS
`semiconductor device having bipolar transistors and
`MOS
`transistors
`having
`an LDD
`structure,
`characterized in that the manufacturing method of a
`BiCMOS semiconductor device comprises
`a process of forming a dummy pattern around the base
`region of said bipolar transistor simultaneously with the
`gate electrode of said MOS transistor,
`a process of forming an insulating film over the entire
`surface after the formation of the LDD region of the
`MOS transistor,
`a process of opening the insulating film of the base
`region of the bipolar transistor on said dummy pattern
`and carrying out an ion implantation to form the base
`region,
`a process of forming a resist pattern that covers the base
`region on the inside of said opening and on top of the
`dummy pattern, and
`a process of performing an anisotropic etching process
`to said insulating film.
`[Claim 4] A BiCMOS semiconductor device having
`MOS transistors of an LDD structure and bipolar
`transistors of a lateral structure, characterized in that
`the BiCMOS semiconductor device has a substrate
`surface of the base region of said bipolar transistor
`covered with an insulating film identical to an LDD
`sidewall of said MOS transistor.
`[Claim 5] A manufacturing method of a BiCMOS
`semiconductor device having MOS transistors of an
`LDD structure and bipolar transistors of a lateral
`structure, characterized
`in
`that
`the manufacturing
`method of a BiCMOS semiconductor device comprises
`a process of forming an insulating film over the entire
`surface after the formation of the LDD region and the
`gate electrode of said MOS transistor,
`a process of masking the top of the base region of said
`bipolar transistor with the insulating film formed over
`the entire surface, and
`
`a process of performing an anisotropic etching process
`to the insulating film formed over the entire surface.
`[Claim 6] A manufacturing method of a BiCMOS
`semiconductor device having MOS transistors of an
`LDD structure and bipolar transistors of a lateral
`structure, characterized
`in
`that
`the manufacturing
`method of a BiCMOS semiconductor device comprises
`a process of forming an insulating film over the entire
`surface after the formation of the LDD region and the
`gate electrode of said MOS transistor,
`a process of masking the top of the base region of said
`bipolar transistor with the insulating film formed over
`the entire surface,
`a process of simultaneously forming a sidewall in the
`side surface of the gate electrode of a MOS transistor
`by performing an anisotropic etching process to the
`insulating film formed over the entire surface and
`forming an insulating film that determines a base width
`on top of the base region of the bipolar transistor, and
`a process of simultaneously forming source and drain
`regions of a MOS transistor as well as emitter and
`collector regions of a bipolar transistor.
`[Detailed Description of the Invention]
`[0001]
`[Industrial Application] The present invention relates to
`a BiCMOS semiconductor device and a manufacturing
`method therefor. In particular, it pertains to a BiCMOS
`semiconductor device having bipolar transistors and
`MOS transistors having an LDD structure, and a
`manufacturing method therefor.
`[0002]
`[Description of the Prior Art] FIG. 12-FIG. 17 show a
`manufacturing process of a BiCMOS semiconductor
`device having MOS transistors Tr1 of an LDD structure
`and bipolar transistors Tr3 of a [lateral] structure of a
`prior art example.
`[0003] As shown in FIG. 12, an N+ embedded layer 2 is
`formed in a PMOS section Tr2 and NPN transistor part
`Tr3 by carrying out an arsenic ion implantation at 40
`keV and 5 E15 and thermal diffusion to P-type Si
`substrate 1. Then, an N-type Si epitaxial layer 3 of 1 Ω
`cm is formed at a thickness of 2.0 µm.
`[0004] P-wells 4p are formed by carrying out a boron
`ion implantation to the PMOS section Tr2 and the
`isolation region at 320 keV and 7 E12, and N-wells 4n
`are
`formed by carrying out a phosphorus
`ion
`implantation to the NMOS section Tr1 at 180 keV and
`8 E11.
`[0005] An SiO2 film 5 having a thickness of 800 nm is
`formed in the isolation region of the Si epitaxial layers
`3 by the usual LOCOS technique. A gate oxide film 6
`having a thickness of 20 nm is formed in the active
`region.
`[0006] Next, as shown in FIG. 13, an N+ sinker region
`8 of a collector electrode extraction is formed by
`carrying out a phosphorus ion implantation to NPN
`transistor part Tr3 at 50 keV and 5 E15. After the gate
`electrode 7 is formed with a poly Si film doped with
`phosphorus, a phosphorus ion implantation is carried
`
`
`
`NVIDIA Corp.
`Exhibit 1109
`Page 002
`
`

`

`(3) Japanese Unexamined Patent Application Publication H07-86158
`
`out to NMOS section Tr1 at 25 keV and 5 E13 to form
`a low-concentration N+ drain region 9.
`[0007] As shown in FIG. 14, a 300-nm SiO2 film 12 is
`formed over the entire surface by CVD. This SiO2 film
`is used to form LDD sidewalls.
`[0008] As shown in FIG. 15, the sidewalls 10 are
`formed in the side surfaces of the gate electrodes 7 of
`MOS transistor parts Tr1 and Tr2 by performing an
`anisotropic etching process to the entire surface.
`[0009] As shown in FIG. 16, a resist pattern 31 that
`opens the base region of NPN transistor part Tr3 is
`formed, and a base region 32 of NPN transistor part Tr3
`is formed by carrying out a boron ion implantation at
`35 keV and 1 E14.
`ion
`in FIG. 17, an arsenic
`[0010] As shown
`implantation is carried out at 70 keV and 7 E15 to the
`source and drain regions 11 of NMOS section Tr1 as
`well as the emitter 11e and the collector 11c of the
`NPN transistor part Tr3. Next, a boron ion implantation
`is carried out at 25 keV and 1 E15 to the source and
`drain regions 14 of PMOS section Tr2 and the base
`extraction region 14b of NPN transistor part Tr3.
`[0011] Thereafter, a thick interlayer dielectric film
`consisting of BPSG, etc. is formed over the entire
`surface, and a contact hole is formed. A BiCMOS
`semiconductor device is formed by smoothing by heat
`treatment and forming an electrode (not shown in the
`drawing).
`conventional BiCMOS
`the
`[0012] However,
`semiconductor device has the following problems.
`is
`[0013] When an anisotropic etching process
`performed over the entire surface to form LDD
`sidewalls 10 as shown in FIG. 18, the surface of the
`base region 32 of NPN transistor part Tr3 is exposed to
`over-etching. At this point, the surface of the Si-
`substrate 1 is exposed, causing an etching damage.
`Thereby, problems such as increase in the leakage
`current occur.
`[0014] As shown in FIG. 16, there are the following
`problems since a base ion implantation is performed
`with a resist mask using the resist pattern 31.
`[0015] Namely, there are the following problems:
` Increase of variations in Tr characteristics due to
`dose error by the outgas from the resist at the time of
`ion implantation
`[0016]  Increase in the leakage current by the knock-
`on of contaminants to the Si substrate by the plasma at
`the time of resist removal.
`[0017] FIGS. 19-24 show a BiCMOS semiconductor
`device having MOS transistors of an LDD structure and
`bipolar transistors of a lateral structure of another prior
`art example.
`[0018] As shown in FIG. 19, N+ embedded layers 2 are
`formed in the LPNP Tr section and PMOS section by
`
`
`
`
`
`
`
`
`
`carrying out an arsenic ion implantation at 40 keV and
`5 E15 and thermal diffusion to a P-type Si substrate 1.
`Then, an N-type Si epitaxial layer 3 of 1 Ω cm is
`formed at a thickness of 2.0 µm.
`[0019] P-wells 4p are formed by carrying out a boron
`ion implantation to PMOS section Tr2 and an isolation
`region at 320 keV and 7 E12, and N-wells 4n are
`formed by carrying out a phosphorus ion implantation
`to NMOS section Tr1 and LPNP transistor part Tr3 at
`180 keV and 8 E11.
`[0020] SiO2 films 5 of 800 nm thickness are formed in
`the isolation region of the Si epitaxial layers 3 by the
`usual LOCOS technique. Gate oxide films 6 of 20 nm
`thickness are formed in the active region.
`[0021] As shown in FIG. 20, an N+ sinker region 8 of
`base electrode extraction is formed by carrying out a
`phosphorus ion implantation to LPNP transistor part
`Tr3 at 50 keV and 5 E15. After the gate electrodes 7 are
`formed with a poly Si film doped with phosphorus, a
`phosphorus ion implantation is carried out to NMOS
`section Tr1 at 25 keV and 5E13 to form a low-
`concentration N+ drain region 9.
`[0022] As shown in FIG. 21, a 300-nm SiO2 film 12 is
`formed over the entire surface by CVD. This SiO2 film
`12 is used to form LDD sidewalls.
`[0023] As shown in FIG. 22, sidewalls 10 are formed in
`the side surfaces of the gate electrodes 7 of MOS
`transistor parts Tr1 and Tr2 by performing an
`anisotropic etching process over the entire surface.
`Then, source and drain regions 11 are formed by
`carrying out an arsenic ion implantation to NMOS
`section Tr1 at 70 keV and 7 E15.
`[0024] As shown in FIG. 23, the source and drain
`regions 14 of PMOS section Tr2, as well as the emitter
`14e and the collector region 14c of LPNP transistor part
`Tr3 are formed by forming a mask 23 that opens the
`emitter and collector region of PMOS section Tr2 and
`LPNP transistor part Tr3 and carrying out a boron ion
`implantation at 25 keV and 1 E15.
`[0025] As shown in FIG. 24, a thick interlayer
`dielectric film 19 consisting of BPSG, etc. is formed
`over the entire surface, and a contact hole is formed. A
`BiCMOS
`semiconductor device
`is
`formed by
`smoothing by heat treatment and forming an electrode.
`[0026] Said conventional BiCMOS semiconductor
`technology also had the following problems.
`[0027] When performing an anisotropic etching process
`over the entire surface to form LDD sidewalls as shown
`in FIG. 25, the surface of the base region 22 of LPNP
`transistor Tr2 is exposed to over-etching. At this time,
`the Si-substrate surface is exposed, causing an etching
`damage. Thereby, problems occur, such as deterioration
`of Hfe by the increase in recombination current of the
`base and an increase in the leakage current between an
`
`
`
`
`NVIDIA Corp.
`Exhibit 1109
`Page 003
`
`

`

`(4) Japanese Unexamined Patent Application Publication H07-86158
`
`emitter and a collector.
`[0028]
`[Objects of the Invention] The present invention solves
`the problems mentioned above and aims to provide a
`BiCMOS
`semiconductor device
`that
`solved
`the
`inconvenience as the result of over-etching, and a
`manufacturing method for
`the same regarding
`the
`technology pertaining to the BiCMOS semiconductor
`device having bipolar transistors and MOS transistors
`having an LDD structure.
`[0029]
`[Means for Solving the Problem] The invention of Claim
`1 of this patent application is a BiCMOS semiconductor
`device having bipolar transistors and MOS transistors
`having an LDD structure, characterized
`in
`that a
`conductive film identical to the gate electrode of said
`MOS transistor is formed around the base region of said
`bipolar transistor, and said conductive film is electrically
`isolated from the base region, thereby achieving said
`objective.
`[0030] The invention of Claim 2 of this patent application
`is a manufacturing method of a BiCMOS semiconductor
`device having bipolar transistors and MOS transistors of
`an LDD structure, characterized in that the manufacturing
`method of a BiCMOS semiconductor device comprises a
`process of forming an insulating film over the entire
`surface after the formation of the LDD region and the
`gate electrode of said MOS transistor, a process of
`forming an opening in an insulating film of the base
`region of the bipolar transistor and carrying out an ion
`implantation to form the base region, a process of
`covering said opening by a resist, and a process of
`performing an anisotropic etching process
`to said
`insulating film, thereby achieving said objective.
`[0031] The invention of Claim 3 of this application is a
`manufacturing method of a BiCMOS semiconductor
`device having bipolar transistors and MOS transistors of
`an LDD structure, characterized in that the manufacturing
`method of a BiCMOS semiconductor device comprises a
`process of forming a dummy pattern around the base
`region of the bipolar transistor simultaneously with the
`gate electrode of the MOS transistor, a process of forming
`an insulating film over the entire surface after the
`formation of the LDD region of the MOS transistor, a
`process of opening the insulating film of the base region
`of the bipolar transistor on said dummy pattern and
`carrying out an ion implantation to form the base region, a
`process of forming a resist pattern that covers the base
`region on the inside of said opening and the top of the
`dummy pattern, and a process of performing an
`anisotropic etching process to said insulating film,
`thereby achieving said objective.
`[0032] The invention of Claim 4 of this patent application
`is a BiCMOS semiconductor device having MOS
`transistors of an LDD structure and bipolar transistors of a
`lateral structure, characterized in that the BiCMOS
`semiconductor device has a substrate surface of the base
`region of the bipolar transistor covered with an insulating
` film identical to the LDD sidewall of the MOS
`
`transistor, thereby achieving said objective.
`
`[0033] The invention of Claim 5 of this patent application is
`a manufacturing method of a BiCMOS semiconductor
`device having MOS transistors of an LDD structure and
`bipolar transistors of a lateral structure, characterized in that
`the manufacturing method of a BiCMOS semiconductor
`device comprises a process of forming an insulating film
`over the entire surface after the formation of the LDD
`region and the gate electrode of said MOS transistor, a
`process of masking the top of the base region of said bipolar
`transistor with the insulating film formed over the entire
`surface, and a process of performing an anisotropic etching
`process to the insulating film formed over the entire surface,
`thereby achieving said objective.
`[0034] The invention of Claim 6 of this patent application is
`a manufacturing method of a BiCMOS semiconductor
`device having MOS transistors of an LDD structure and
`bipolar transistors of a lateral structure, characterized in that
`the manufacturing method of a BiCMOS semiconductor
`device comprises a process of forming an insulating film
`over the entire surface after the formation of the LDD
`region and the gate electrode of said MOS transistor, a
`process of masking the top of the base region of said bipolar
`transistor with the insulating film formed over the entire
`surface, a process of simultaneously forming a sidewall in a
`gate electrode side surface of a MOS transistor by
`performing an anisotropic etching process to the insulating
`film formed over the entire surface and forming an
`insulating film that determines a base width on the base
`region of
`the bipolar
`transistor, and a process of
`simultaneously forming source and drain regions of a MOS
`transistor as well as emitter and collector regions of a
`bipolar transistor, thereby achieving said objective.
`[0035]
`[Operation] The invention of Claims 1-3 of this application
`can solve the problems described above by opening the top
`of the base region of the NPN transistor part [that is covered
`with] the insulating film that forms the LDD sidewalls and
`subjecting the insulating film as a mask to a base ion
`implantation. When performing an anisotropic etching
`process to form LDD sidewalls, the base region surface can
`be prevented from being exposed to over-etching by
`covering the base region surface of the NPN transistor part
`with a resist.
`[0036] According to this invention, since the base region of
`the NPN transistor part is not exposed to over-etching when
`performing the anisotropic etching process over the entire
`surface to form the LDD sidewalls, etching damage does not
`occur on the Si-substrate surface, so there are no problems
`such as an increase in the leakage current and others. It is
`also possible to prevent an increase of variations in
`transistor characteristics and increase of the leakage current
`by performing a base ion implantation to the insulating film
`used as a mask.
`[0037] According to the invention of the present invention
`claims 4-6, the base region surface can be prevented from
`being exposed to over-etching by using the insulating film
`that forms the LDD sidewalls to mask the top of the base
`region of the LPNP Tr section.
`[0038] It is possible to minimize additional process by
`using the insulating film mask as the mask of the ion
`implantation that forms emitter and collector regions.
`
`
`
`NVIDIA Corp.
`Exhibit 1109
`Page 004
`
`

`

`(5) Japanese Unexamined Patent Application Publication H07-86158
`
`[0039] Since according to this invention the base region
`surface of the LPNP transistor part is not exposed to
`over-etching when an anisotropic etching process is
`performed over the entire surface to form LDD
`sidewalls, etching damage does not occur to the Si-
`substrate surface, so problems, such as deterioration of
`Hfe and an increase in the leakage current, are solved.
`[0040]
`[Examples of Embodiments] The examples of
`embodiments of the present invention are described
`below with reference to the drawings. And it shall be
`readily understood that the present invention is not
`limited to the examples of the embodiments.
`[0041] This example of embodiment is described with
`reference to FIG. 1 showing a completed configuration
`and FIG. 2-FIG. 7 showing a manufacturing process. In
`a BiCMOS semiconductor device having a MOS
`transistor Tr1 of an LDD structure, and a bipolar
`transistor Tr3 as shown in FIG. 1, a conductive film 7d
`identical to the gate electrode 7 of the MOS transistor is
`formed around the base region 14b of the bipolar
`transistor Tr3, and this conductive film 7d is electrically
`isolated from the base region by an isolation region 5.
`[0042] Next,
`the manufacturing process of
`this
`BiCMOS semiconductor device is described. As shown
`in FIG. 2, N+ embedded layers 2 are formed in PMOS
`section Tr2 and NPN transistor part Tr3 by carrying out
`an arsenic ion implantation at 40 keV and 5 E15 and
`thermal diffusion to the P-type Si substrate 1. N-type Si
`epitaxial layers 3 of 1 Ω cm are then formed at a
`thickness of 2.0 µm. P-wells 4p are formed by carrying
`out a boron ion implantation to PMOS section Tr2 and
`isolation region at 320 keV and 7 E12, and N-wells 4n
`are
`formed by carrying out a phosphorus
`ion
`implantation to NMOS section Tr1 at 180 keV and 8
`E11.
`[0043] An SiO2 film 5 having a thickness of 800 nm is
`formed in the isolation region of the Si epitaxial layers
`3 by the usual LOCOS technique. A gate oxide film 6
`having a thickness of 20 nm is formed in an active
`region.
`[0044] As shown in FIG. 3, an N+ sinker region 8 of
`collector electrode extraction is formed by carrying out
`a phosphorus ion implantation to NPN transistor part
`Tr3 at 50 keV and 5 E15. A gate electrode 7 and a
`dummy pattern 7d are formed with the poly Si film
`doped with phosphorus. The dummy pattern 7d is
`formed so as to surround the base region. Then, the
`phosphorus ion implantation is carried out to NMOS
`section Tr1 at 25 keV and 5 E13 to form a low-
`concentration N+ drain region 9.
`[0045] As shown in FIG. 4, a resist pattern 33 that
`opens the base region of NPN transistor part Tr3 is
`formed after forming the SiO2 film 12 over the entire
`surface. At this time, the edge of the opening is made
`until it reaches the dummy pattern 7d.
`[0046] As shown in FIG. 5, the insulating film of the
`base region is removed by wet etching. At this time, the
`dummy pattern 7d serves as an etching stopper. After
`forming an oxide film 34 to prevent channeling, a base
`
`region 35 of NPN transistor part Tr3 is formed by
`carrying out a boron ion implantation at 35 keV and 1
`E14.
`[0047] At this time, since the base ion implantation Ib
`is performed using the insulating film 5 as a mask,
`there are no problems such as dose error by the outgas
`from a resist, plasma contaminant knock-on, or the like
`to the Si substrate 1 at the time of resist removal, etc.
`[0048] As shown in FIG. 6, a resist pattern 36 that
`covers the base region is formed. This pattern is made
`to be inside the opening and come on top of the dummy
`pattern 7d.
`[0049] As shown in FIG. 7, sidewalls 10 and 37 are
`formed, respectively, on the side surfaces of the gate
`electrodes 7 of the MOS transistor and the side surfaces
`of the dummy pattern 7d by performing an anisotropic
`etching process over the entire surface. The base region
`surface is not exposed to over-etching since the top of
`the base region of NPN transistor part Tr3 is covered
`with the resist pattern.
`[0050] The case where there is no dummy pattern 7d is
`considered here. When the resist pattern 36 was formed
`slightly outside the opening due to mask alignment shift,
`the SiO2 film 12 of the overlap part remains thin. When
`the resist pattern 36 was formed slightly inside the
`opening due to mask alignment shift, the SiO2 film 5 of
`the field is shaved at the time of anisotropic etching.
`Forming the dummy pattern 7d can prevent said
`problem caused by mask alignment shift.
`[0051] As shown in FIG. 1, an arsenic ion implantation
`is carried out at 70 keV and 7 E15 to the source and
`drain regions 11 of NMOS section Tr1 as well as the
`emitter 11e and the collector region 11c of NPN
`transistor part. Next, a boron ion implantation is carried
`out at 25 keV and 1 E15 to the source and drain regions
`14 of the PMOS section, as well as the base extraction
`region 14b of NPN transistor part.
`[0052] Then, a thick interlayer dielectric film consisting
`of BPSG or the like is formed over the entire surface,
`and a contact hole
`is
`formed. A BiCMOS
`semiconductor device is completed by performing
`smoothing by heat treatment and forming an electrode
`(not shown in the drawing).
`the description above,
`[0053] As
`is clear from
`according to this example of embodiment, when an
`anisotropic etching process is performed extensively to
`form LDD sidewalls, the base region surface of the
`NPN transistor part is not exposed to over-etching.
`Therefore, there are no problems such as an increase in
`the leakage current, because etching damage does not
`occur on the Si-substrate surface.
`[0054] There will be no contaminant knock-on to the Si
`substrate and outgas from the resist by performing a
`base ion implantation using an insulating film as a
`mask, and it is possible to prevent the increase of
`variations in transistor characteristics and increase of
`the leakage current.
`[0055] Example of Embodiment 2
`This example of embodiment
`reference to FIG. 8-FIG. 11.
`
`is described with
`
`
`
`NVIDIA Corp.
`Exhibit 1109
`Page 005
`
`

`

`(6) Japanese Unexamined Patent Application Publication H07-86158
`
`the
`is a cross-sectional view showing
`[FIG. 4]
`manufacturing process of the semiconductor device of
`Embodiment 1 in order (3).
`the
`[FIG. 5]
`is a cross-sectional view showing
`manufacturing process of the semiconductor device of
`Embodiment 1 in order (4).
`the
`[FIG. 6]
`is a cross-sectional view showing
`manufacturing process of the semiconductor device of
`Embodiment 1 in order (5).
`the
`[FIG. 7]
`is a cross-sectional view showing
`manufacturing process of the semiconductor device of
`Embodiment 1 in order (6).
`[FIG. 8] is a cross-sectional view showing the structure
`of the semiconductor device of Embodiment 2.
`the
`[FIG. 9]
`is a cross-sectional view showing
`manufacturing process of the semiconductor device of
`Embodiment 2 in order (1).
`[FIG. 10] is a cross-sectional view showing the
`manufacturing process of the semiconductor device of
`Embodiment 2 in order (2).
`[FIG. 11] is a cross-sectional view showing the
`manufacturing process of the semiconductor device of
`Embodiment 2 in order (3).
`[FIG. 12] is a figure showing the process of the
`conventional example 1 (1).
`[FIG. 13] is a figure showing the process of the
`conventional example 1 (2).
`[FIG. 14] is a figure showing the process of the
`conventional example 1 (3).
`[FIG. 15] is a figure showing the process of the
`conventional example 1 (4).
`[FIG. 16] is a figure showing the process of the
`conventional example 1 (5).
`[FIG. 17] is a figure showing the process of the
`conventional example 1 (6).
`[FIG. 18] is a figure showing the problem of the
`conventional example 1.
`[FIG. 19] is a figure showing the process of the
`conventional example 2 (1).
`[FIG. 20] is a figure showing the process of the
`conventional example 2 (2).
`[FIG. 21] is a figure showing the process of the
`conventional example 2 (3).
`[FIG. 22] is a figure showing the process of the
`conventional example 2 (4).
`[FIG. 23] is a figure showing the process of the
`conventional example 2 (5).
`[FIG. 24] is a figure showing the process of the
`conventional example 2 (6).
`[FIG. 25] is a figure showing the problem of the
`conventional example 2.
`[Explanations of references]
`Tr1 MOS transistor
`Tr3 Bipolar transistor
`7 Gate electrode
`7 d Conductive film
`
`[0056] First, the processes shown in FIG. 19-FIG. 21
`similar
`to
`that of
`the conventional example are
`performed.
`[0057] As shown in FIG. 21, after the SiO2 film 12 is
`formed over the entire surface, a resist pattern 23 that
`masks the top of the base region of LPNP transistor part
`Tr3 as shown in FIG. 9 is formed.
`[0058] As shown in FIG. 10, sidewalls 10 are formed
`on the side surfaces of the gate electrodes 7 of the MOS
`transistor by performing an anisotropic etching process
`extensively. At this time, the SiO2 film 26 remains on
`top of the base region of LPNP transistor part Tr3 from
`the resist pattern 23. For this reason, the surface of the
`base region 22 is not exposed to over-etching. As
`compared to the conventional example, only a process
`of forming this resist pattern is added.
`[0059] Source and drain regions 11 are then formed by
`carrying out an arsenic ion implantation to the NMOS
`section at 70 keV and 7 E15.
`[0060] The source and drain regions 14 of PMOS
` as well as the emitter 14e and the collector
`section Tr2
`region 14c of the LPNP transistor part Tr3 are formed
`by forming a mask 25 that opens except for the base
`electrode extraction of PMOS section Tr2 and LPNP
`transistor part Tr3 and carrying out a boron ion
`implantation at 25 keV and 1 E15, as shown in FIG. 11.
`[0061] As shown in FIG. 8, a thick interlayer dielectric
`film 19 consisting of BPSG or the like is formed over
`the entire surface, and a contact hole is formed. A
`BiCMOS
`semiconductor device
`is
`formed by
`smoothing by heat treatment and forming an electrode.
`[0062] As
`is clear from
`the description above,
`according to this example of embodiment, when an
`anisotropic etching process is performed extensively to
`form LDD sidewalls, the base region surface of the
`LPNP transistor part is not exposed to over-etching.
`Therefore, an etching damage does not occur on the Si-
`substrate surface, and problems such as deterioration of
`Hfe and an increase in the leakage current do not occur.
`It is possible to realize a highly efficient and high
`quality LPNP transistor at low cost by minimum
`additional process.
`[0063]
`[Effect of the Invention] As described above, the
`present invention provides a BiCMOS semiconductor
`device that solved the inconvenience as the result of
`over-etching and a manufacturing method for the same
`regarding the technology relating to the BiCMOS
`semiconductor device having bipolar transistors and
`MOS transistors having an LDD structure.
`[Brief Description of the Drawings]
`[FIG. 1] is a cross-sectional view showing the structure
`of the semiconductor device of Embodiment 1.
`the
`is a cross-sectional view showing
`[FIG. 2]
`manufacturing process of the semiconductor device of
`Embodiment 1 in order (1).
`the
`[FIG. 3]
`is a cross-sectional view showing
`manufacturing process of the semiconductor device of
`Embodiment 1 in order (2).
`
`
`
`NVIDIA Corp.
`Exhibit 1109
`Page 006
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`

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`(7) Japanese Unexamined Patent Application Publication H07-86158
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`EMITTER
`
`[FIG. 1]
`The semiconductor device of Embodiment 1
`CONDUCTIVE FILM
` COLLECTOR
`
`
`BASE
`
`
`
`[FIG. 2]
`
`Process (1) of Embodiment 1
`
`SUBSTRATE
`
`
`
`SUBSTRATE
`
`
`
`
`
`[FIG. 3]
`
`Process (2) of Embodiment 1
`DUMMY PATTERN
`
`
`
`RESIST MASK
`
`
`
`[FIG. 9]
`Process (1) of Embodiment 2
`
`[FIG. 4]
`
`Process (3) of Embodiment 1
`
`
`
`RESIST PATTERN
`
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`NVIDIA Corp.
`Exhibit 1109
`Page 007
`
`

`

`(8) Japanese Unexamined Patent Application Publication H07-86158
`
`[FIG. 5]
`
`Process (4) of Embodiment 1
`BASE ION IMPLANTATION
`
`[FIG. 8]
`
`Semiconductor device of Embodiment 2
`
`OXIDE
`FILM
`
`BASE
`
`[FIG. 6]
`
`Process (5) of Embodiment 1
`RESIST PATTERN
`
`[FIG. 10]
`
`Process (2) of Embodiment 2
`
`[FIG. 7]
`
`Process (6) of Embodiment 1
`
`SIDE WALL
`
`SIDE WALL
`
`
`
`[FIG. 11]
`
`Process (3) of Embodiment 2
`
`[FIG. 12]
`
`Process (1) of conventional example 1
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`NVIDIA Corp.
`Exhibit 1109
`Page 008
`
`

`

`(9) Japanese Unexamined Patent Application Publication H07-86158
`
`[FIG. 13]
`
`Process (2) of conventional example 1
`GATE
`ELECTRODE
`
`[FIG. 14]
`
`Process (3) of conventional example 1
`
`[FIG. 15]
`
`Process (4) of conventional example 1
`SIDE WALL
`
`[FIG. 16]
`
`Process (5) of conventional example 1
`RESIST PATTERN
`
`BASE ION
`IMPLANTATION
`
`BASE
`
`
`
`
`
`
`
`
`
`
`
`
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`
`
`
`
`
`
`[FIG. 17]
`
`
`Process (6) of conventional example 1
`
`
`EMITTER BASE COLLECTOR
`
`[FIG. 18]
`
`Explanation drawing of problem of