Original Copy
`
`IPC
`classification
`code
`
`Main classification
`Sub classification
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`
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`
`
`Form examination
`section
`
`Application number: 021255
`Person in charge
`Examiner
`[Sealed:] Eui Seok
`[Sealed:] Dae Kyu
`Chung, [Aug 27,
`Park, [Aug 29,
`1994]
`1994]
`
`Patent Application (1)
`
`[Stamped:]
`Application Dept.
`Korean Intellectual
`Property Office
`Aug. 27, 1994
`Received
`No.
`Name
`
`Address
`Name
`
`Representative Director Jeong Hwan Moon, Gold Star Electron
`Co., Ltd.
`
`Soon Seok Yang Attorney code
`
`
`
`Tel
`
`Applicant's
`Code
`Phone No.
`
`
`
`
`
`
`Received by
`
`Applicant
`
`Attorney
`
`Address
`Name
`
`
`Jeung Sang Lee
`
`Resident registration
`number
`
`
`
`Nationality
`
`
`Fabrication Method for Semiconductor Device
`Country of
`Type of
`Date of
`application
`application
`application
`
`Application
`number
`
`Inventor
`
`Address
`Name of invention
`
`Priority claim in accordance
`with the provisions of the
`Patent Law (Article 54 or
`55)
`
`
`
`
`The application is filed as described above in accordance with Article 42 of the Patent Law.
`
`
`
`
`To: Commissioner of the Korean Industrial Property Office
`The review of the application is requested as described above in accordance with Article 60 of the Patent Law.
`
`
`
`To: Commissioner of the Korean Industrial Property Office
`Attachments:
`1. 2 copies of the application
`
`
`2. 3 copies of Specifications, Abstract and Drawings
`
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`3. 1 copy of Power of Attorney
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`
`
`Republic of
`Korea
`
`Verification
`document
`Attach
`Unatta
`ed
`ched
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`August 27, 1994
`
`
`Agent: Soon Seok Yang, Patent Attorney
`
`Agent: Soon Seok Yang, Patent Attorney
`
`Basic
`
`Applic
`ation
`fee
`
`Additi
`on
`Priority claim fee
`
`076
`
`Fees
`17
`pages
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`Pages
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`Cases
`4/11
`Items
`
`18,000 Won
`
` Won
`
` Won
`
`277,000 Won
`
`295,000
`
`Review request
`fee
`Total
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`
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`Tel: 569-4653, 569-4654, Fax: 569-4655
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` -
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` Soon Seok Yang Patent Law Office -
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`NVIDIA Corp.
`Exhibit 1107
`Page 001
`
`

`

`SPECIFICATIONS
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`
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`1. Name of invention
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`A Method for Fabricating Semiconductor Device
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`
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`2. Brief Explanation of the Drawings
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`FIG. 1 and FIG. 2 are the drawings of the prior art and FIGs. 3 to 6 illustrate the technology of the
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`present invention.
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`* Explanation on the numbers marked for the major parts of the drawings
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`11, 21, 31: semiconductor substrate
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`13, 23, 33: source and drain region
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`14', 24', 25', 34-1: sidewall
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`15, 25, 35: interlayer insulation film
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`12, 22, 32: field oxide layer
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`14, 24, 34: gate
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`44-3: connection line
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`57: step
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`34-1, 34-2, 44-2, 54-2, 64-2, 67: etch stop layer 16, 26, 36: conductive layer
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`
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`3. Detailed Explanation of the Invention
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`
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`The present invention relates to a method for fabricating a semiconductor device, and specifically
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`pertains to a method for fabricating a semiconductor device, in which the characteristics of the device are
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`improved by securing an align margin upon formation of the contact hole.
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`FIG. 1 (a) is a cross-sectional view of a source and drain region according to the prior art, and
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`FIG. 1 (b) illustrates the problem of the prior art.
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`078
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`(17 – 1)
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`NVIDIA Corp.
`Exhibit 1107
`Page 002
`
`

`

`
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`In order to make the structure illustrated in FIG. 1 (a), the active region is isolated by a field
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`oxide layer (12) on a semiconductor substrate (11) and a MOS gate (14) is formed by depositing gate
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`oxide layer, poly and gate caps in this sequence and then etching them.
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`
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`After forming a low concentration impurity region by the following ion implantation process and
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`forming a gate sidewall (14') using a deposition and etch-back process, a source and drain region (13) is
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`made by implanting the sidewall into the mask in order to form a high concentration impurity region.
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`A contact hole that opens the source and drain region is formed by depositing an interlayer
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`insulation film (15) on the following transistor and etching the interlayer insulation film.
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`And then, the process is completed by depositing a conductive layer (16) to form a junction
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`contact with the source and drain region of the transistor.
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`As illustrated in FIG. 1 (b), the prior art described above depended on the alignment accuracy of a
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`photographic process for the adjustment of the thickness of the interlayer insulation film to secure a
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`sufficient breakdown voltage between gate and junction contact.
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`
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`However, when a mis-alignment occurs, the gate sidewall (14') is damaged as shown in the area
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`B or the field oxide layer that separates an active region is also damaged (area A of the drawing) and thus,
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`it becomes the cause of junction leakage.
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`(17 - 2) 079
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`NVIDIA Corp.
`Exhibit 1107
`Page 003
`
`

`

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`Therefore, a structure illustrated FIG. 2 was proposed in an effort to improve this problem.
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`
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`FIG. 2 (a) is a cross-sectional view showing an improvement over the structure in FIG. 1, and
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`FIG. 2 (b) is the cross-sectional view of a problematic area of FIG. 2 (a).
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`As illustrated in FIG. 2 (a), after forming a transistor using a general method, an interlayer
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`insulation film (25) is deposited for interlayer isolation and a contact hole is formed by etching the
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`interlayer insulation film so that the source and drain region of the transistor is to be opened.
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`
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`In this drawing, the number 21 represents a semiconductor substrate, 22 represents a field oxide
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`layer, 24 represents a gate, and 24' represents a gate sidewall.
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`Subsequently, in order to enhance the characteristics of a breakdown voltage by securing an
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`alignment margin, a sidewall (25') is formed on the side wall of the interlayer insulation film within the
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`contact hole using a deposition and etch-back process.
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`And then, a conductive layer (26) is formed within the contact hole by depositing conductive
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`material.
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`However, as illustrated in FIG. 2 (b), the process forming a sidewall on the side wall of the
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`interlayer insulation film within a contact hole can have a problem caused by the breakdown voltage on
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`the area C when the contact hole is laid over the jaw of a gate as the contact alignment deviates from the
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`margin.
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`(17 - 3)
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`080
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`NVIDIA Corp.
`Exhibit 1107
`Page 004
`
`

`

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`Further, when a contact hole has been defined in a small size that is below a certain size
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`according to the tendency of high density integration, the inside of the contact hole is filled by the process
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`forming a sidewall on the side wall of the interlayer insulation film, and a problem happens to the opening
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`of the contact (Area D of the drawing) due to this and a problem is also encountered in the scale-down of
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`a device.
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`
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`The present invention has been conceived to solve these problems and it relates to the structure of
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`a semiconductor device in which a process alignment margin is secured when forming a contact hole by
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`forming an etch stop layer on the contact hole area to protect the lower insulation layer and a method for
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`fabricating this structure.
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`The method of the present invention comprises of a) a step of fabricating a transistor by making a
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`source and drain region which is formed by doping impurity on the gate in the active region on a
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`semiconductor substrate and the substrate around the gate; b) a step of forming an etch stop layer around
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`said source and drain region by depositing a material having a high etch selectivity with an interlayer
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`insulation film, which is going to be formed in a later process, to the front of said transistor and then,
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`conducting etch-back using an anisotropic etching process; and c) a step of opening the source and drain
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`region by forming a contact hole within the range of the etch stop layer inside the sidewall using a photo
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`lithography process after depositing the insulating material for interlayer isolation to the front, and then
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`connecting the conductive layer to the opened area in a method for fabricating a semiconductor device.
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`(17 - 4) 081
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`NVIDIA Corp.
`Exhibit 1107
`Page 005
`
`

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`FIG. 3 illustrates the semiconductor device fabricating process in accordance with the present
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`invention.
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`One embodiment of the present invention can be explained referring to drawings as follows:
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`As illustrated in FIG. 3 (a), an active region is isolated electrically from the surrounding active
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`regions by forming a field oxide layer (32) on a semiconductor substrate (31), and a MOS gate (34) is
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`formed by depositing and etching gate oxide layer, poly and gate cap in order.
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`
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`After forming a low concentration impurity region by the following ion implantation process and
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`forming a gate sidewall (34-1) using a deposition and etch-back process, a source and drain region (33) is
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`made by implanting sidewall into mask to form a high concentration impurity region.
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`Up to this process, it is conducted in the same way with the process of the prior art.
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`Subsequently, as illustrated in FIG. 3 (b), an etch stop layer (34-2) of the contact etching process
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`is formed around the impurity region in the form of a sidewall by depositing a material having a high etch
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`selectivity with an interlayer insulation film, which is going to be formed in a later process to the surface
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`of the gate sidewall and then, conducting etch-back.
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`(17 - 5) 082
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`NVIDIA Corp.
`Exhibit 1107
`Page 006
`
`

`

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`At this time, the etch stop layer is formed with conductive or non-conductive material, and it is
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`formed in the form of a sidewall through a deposition and etch-back process using the step area formed on
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`the lower layer without any additional mask.
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`As illustrated in FIG. 3 (c), a contact hole is formed by depositing an interlayer insulation film
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`(35) and etching the interlayer insulation film ensuring that it doesn't deviate from the range of the etch
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`stop layer (34-2).
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`As illustrated in FIG. 3 (d), the junction contact with the source and drain region of the transistor
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`is to be formed with the conductive layer (36) composed of conductive material.
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`FIG. 4 illustrates the second embodiment of the present invention. This is a method of forming an
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`etch stop layer (44-2) using an internal connection line (44-3) passing adjacently or the step of a dummy
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`pattern when the step at the lower layer used to form the etch stop layer in the first embodiment is not
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`sufficient.
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`FIG. 5 is the drawing of the third embodiment of the present invention.
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`When the step at the lower layer used to form the etch stop layer is not sufficient and the method
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`of the second embodiment can't be used, the step for forming an etch stop layer (54-2) is secured in this
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`method using the step (57) randomly formed by etching the semiconductor substrate using the oxide
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`layers on the substrate (field oxide layer, gate sidewall, cap oxide layer) as mask.
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`(17 - 6) 083
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`NVIDIA Corp.
`Exhibit 1107
`Page 007
`
`

`

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`FIG. 6 is another embodiment illustrating the device according to the present invention.
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`This is a method of forming another etch stop layer (67) on the source and drain region prior to
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`forming an etch stop layer to prevent the damage to the lower layer caused by the anisotropic etching
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`when an etch stop layer (64-2) is formed in the embodiments 1 to 5.
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`In this case, the material of the etch stop layer can be conductive or non-conductive and when it is
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`formed using non-conductive material, it is removed by etching when forming the contact hole.
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`The effects of the present invention are as follows:
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`First, since the etch stop layer formed additionally in the present invention can be formed through
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`self-alignment without a separate mask, there is no additional process.
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`Secondly, since the heavily stressed site is protected by the etch stop layer, the area in which
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`junction leakage can happen can be protected from the etching process.
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`Thirdly, the breakdown voltage between a gate and a contact can be secured only with the
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`adjustment of the thickness of a gate sidewall by protecting the gate sidewall from being peeled by the
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`etch stop layer.
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`Fourthly, an alignment margin can be secured easily at contact photographing.
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`Fifthly, after forming the contact hole, the scale-down of the contact hole is easy since a separate
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`sidewall within the hole is not used.
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`(17 - 7) 084
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`NVIDIA Corp.
`Exhibit 1107
`Page 008
`
`

`

`4. Scope of Patent Claims
`
`
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`1. A method for fabricating a semiconductor device which comprises of
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`a) a step of fabricating a transistor by making a source and drain region which is formed by
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`doping impurity on the gate in the active region on a semiconductor substrate and the substrate around the
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`gate;
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`b) a step of forming an etch stop layer around said source and drain region by depositing a
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`material having a high etch selectivity with an interlayer insulation film, which is going to be formed in a
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`later process, to the front of said transistor and then, conducting etch-back using an anisotropic etching
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`process; and
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`c) a step of opening the source and drain region by forming a contact hole within the range of the
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`etch stop layer inside the sidewall using a photo lithography process after depositing the insulating
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`material for interlayer isolation to the front, and then connecting the conductive layer to the opened area.
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`
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`2. The method for fabricating a semiconductor device in Claim 1, wherein the sidewall for etch
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`stop is composed of a conductive material.
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`3. The method for fabricating a semiconductor device in Claim 1, wherein the sidewall for etch
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`stop is composed of a non-conductive material.
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`(17 - 8) 085
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`NVIDIA Corp.
`Exhibit 1107
`Page 009
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`

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`4. The method for fabricating a semiconductor device in Claim 1, wherein the sidewall is formed
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`using the step at the lower layer.
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`5. The method for fabricating a semiconductor device in Claim 1, wherein the sidewall uses either
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`the step of the connection line at the adjacent lower layer or uses the step by forming an adjacent dummy
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`pattern.
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`6. A method for fabricating a semiconductor device which comprises of
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`a) a step of fabricating a transistor by making a source and drain region which is formed by
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`doping impurity on the gate in the active region on a semiconductor substrate and the substrate around the
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`gate;
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`b) a step of forming the second etch stop layer on said source and drain region;
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`c) a step of forming the first etch stop layer around said source and drain region by depositing a
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`material having a high etch selectivity with an interlayer insulation film, which is going to be formed in a
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`later process, to the front of said transistor and then, conducting etch-back using an anisotropic etching
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`process; and
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`(17-9) 086
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`NVIDIA Corp.
`Exhibit 1107
`Page 010
`
`

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`d) a step of opening the source and drain region by forming a contact hole within the range of the
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`etch stop layer inside the sidewall using a photo lithography process after depositing the insulating
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`material for interlayer isolation to the front, and then connecting the conductive layer to the opened area.
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`7. The method for fabricating a semiconductor device in Claim 6, wherein the first etch stop layer
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`is composed of a conductive material.
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`8. The method for fabricating a semiconductor device in Claim 6, wherein the first etch stop layer
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`is composed of a non-conductive material.
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`9. The method for fabricating a semiconductor device in Claim 6, wherein the second etch stop
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`layer is composed of a conductive material.
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`10. The method for fabricating a semiconductor device in Claim 6, wherein the second etch stop
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`layer is composed of a non-conductive material and it is removed together when the compared to is
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`formed.
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`(17 - 10) 087
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`NVIDIA Corp.
`Exhibit 1107
`Page 011
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`

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`11. A method for fabricating a semiconductor device which comprises of
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`a) a step of fabricating a transistor by making a source and drain region which is formed by
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`doping impurity on the gate in the active region defined by a field oxide layer on a semiconductor
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`substrate and the substrate around the gate;
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`b) a step of forming a step on the substrate in the source and drain region by etching the
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`semiconductor substrate using the insulation layer and field oxide layer forming the transistor as a mask,
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`c) a step of forming the etch stop layer around said source and drain region using said step of the
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`substrate by depositing a material having a high etch selectivity with an interlayer insulation film, which
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`is going to be formed in a later process, to the front of said transistor and then, conducting etch-back
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`using an anisotropic etching process; and
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`d) a step of opening the source and drain region by forming a contact hole within the range of the
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`etch stop layer inside the sidewall using a photo lithography process after depositing the interlayer
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`insulation film to the front, and then connecting the conductive layer to the opened area.
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`12. The method for fabricating a semiconductor device in Claim 11, wherein the first etch stop
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`layer is composed of a conductive material.
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`(17 - 11) 088
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`NVIDIA Corp.
`Exhibit 1107
`Page 012
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`

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`13. The method for fabricating a semiconductor device in Claim 11, wherein the first etch stop
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`layer is composed of a non-conductive material.
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`14. The method of fabricating the semiconductor device which comprises of a gate for which gate
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`oxide layer and conductive layer gate cap are formed on the active region defined by a field oxide layer
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`on a semiconductor substrate and a gate sidewall is formed, a transistor composed of a source and drain
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`region, an interlayer insulation film formed on the transistor, a contact hole which opens the source and
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`drain region of the transistor and penetrates the above interlayer insulation film, and the conductive layer
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`filling the contact hole, wherein a material having a high etch selectivity with the interlayer insulation
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`film is formed under the interlayer insulation film in the area surrounding the source and drain region.
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`15. The semiconductor device in Claim 14, wherein the material having a high etch selectivity is
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`conductive.
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`(17 - 12) 089
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`NVIDIA Corp.
`Exhibit 1107
`Page 013
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`

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`Abstract
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`
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`The present invention relates to the structure of a semiconductor device in which a process
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`alignment margin is secured when forming a contact hole by forming an etch stop layer on the contact
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`hole area to protect the lower insulation layer and a method for fabricating this structure.
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`
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`The present invention fabricates a semiconductor device using a method comprised of a) a step of
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`fabricating a transistor by making a source and drain region which is formed by doping impurity on the
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`gate in the active region on a semiconductor substrate and the substrate around the gate; b) a step of
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`forming an etch stop layer around said source and drain region by depositing a material having a high etch
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`selectivity with an interlayer insulation film, which is going to be formed in a later process, to the front of
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`said transistor and then, conducting etch-back using an anisotropic etching process; and c) a step of
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`opening the source and drain region by forming a contact hole within the range of the etch stop layer
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`inside the sidewall using a photo lithography process after depositing the insulating material for interlayer
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`isolation to the front, and then connecting the conductive layer to the opened area.
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`(17 - 13) 090
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`NVIDIA Corp.
`Exhibit 1107
`Page 014
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`

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`FIG. 1
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`(b)
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`(a)
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`FIG. 2
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`(17 - 14) 091
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`NVIDIA Corp.
`Exhibit 1107
`Page 015
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`

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`(b)
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`FIG. 3
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`(b)
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`(c)
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`(17 - 15)
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`NVIDIA Corp.
`Exhibit 1107
`Page 016
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`

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`(d)
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`FIG. 4
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`FIG. 5
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`(17 - 16) 093
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`NVIDIA Corp.
`Exhibit 1107
`Page 017
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`

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`FIG. 6
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`(17-17) 094
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`NVIDIA Corp.
`Exhibit 1107
`Page 018
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`

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`Ed
`
`TRANSPERFECT
`
`City of New York, State ofNew York, County of New York
`
`1, Kelly Kim, hereby certify that the following document is, to the best of my
`
`knowledge and belief, a true and accurate translation from Korean to English
`
`“KR App. No. 1994/021255”
`
`
`
`Kelly Kim
`
`Sworn to before me this
`
`Tuesday, April 28, 2015
`
`
`
`Signature, Notary Public”
`
`
`
`AIIY $93. m
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`c -
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`NataryNo'I01LE6314554
`Quallflad In RIchmond Conn
`Commisslon Explres Nov 10I 2 18'
`
`
`
`
`
`
`
`Stamp, Notary Public—
`
`LANGUAGE AND TECHNOLOGY SOLUTIONS FOR GLOBAL BUSINESS
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`NVIDIA Corp.
`Exhibit 1107
`Page 019
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`NVIDIA Corp.
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`Exhibit 1 107
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`NVIDIA Corp.
`Exhibit 1107
`Page 027
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`Exhibit 1 107
`Page 028
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`NVIDIA Corp.
`Exhibit 1107
`Page 028
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`Exmbfl1107
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`Page 029
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`Exhibit 1 107
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`Page 030
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`NVIDIA Corp.
`Exhibit 1 107
`Page 031
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`NVIDIA Corp.
`Exhibit 1107
`Page 031
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